Information processing apparatus, method, chip, and device

Abstract

Embodiments of the present application disclose an information processing device, method, chip and equipment. The method comprises: obtaining a current command and prefetch address information by a generating module, and generating a sideband signal according to the current command and the prefetch address information, the sideband signal being used for representing the prefetch address information; sending the current command and the sideband signal to an analyzing module; receiving the current command and the sideband signal by the analyzing module, and analyzing and processing the sideband signal according to the current command to determine the prefetch address information. In this way, the generating module can send the prefetch address information to the analyzing module in the form of the sideband signal, so that no additional AXI write channel needs to be added, and the bandwidth of the original AXI write channel does not need to be occupied, thereby improving the performance of the equipment.

Description

Technical Field

[0001] This application relates to the field of information technology, and in particular to an information processing apparatus, method, chip, and device. Background Technology

[0002] In related technologies, the System Memory Management Unit (SMMU) and Direct Memory Access (DMA) can exchange information. To improve performance and reduce read / write access latency, DMA can prefetch address information to the SMMU via the Advanced Extensible Interface (AXI) write channel.

[0003] However, when DMA sends prefetch address information through the AXI write channel, it usually has the following drawbacks: on the one hand, if DMA uses the original AXI read channel to send prefetch address information, an additional AXI write channel is required; on the other hand, if DMA uses the original AXI write channel to send prefetch address information, it consumes additional bandwidth, thus affecting performance. Summary of the Invention

[0004] This application provides an information processing apparatus, method, chip, and device that, when the DMA transmits prefetch address information to the SMMU, does not require adding an additional AXI write channel, nor does it occupy the bandwidth of the original AXI write channel and thus affect performance.

[0005] In a first aspect, embodiments of this application provide an information processing apparatus, which includes a generation module and a parsing module, wherein:

[0006] The generation module is used to obtain the current command and prefetch address information, and generate sideband signals based on the current command and prefetch address information. The sideband signals are used to represent the prefetch address information; and send the current command and sideband signals to the parsing module.

[0007] The parsing module is used to receive the current command and sideband signals, and to parse and process the sideband signals according to the current command to determine the prefetch address information.

[0008] Secondly, embodiments of this application provide an information processing method, the method comprising:

[0009] The current command and prefetch address information are obtained through the generation module, and sideband signals are generated based on the current command and prefetch address information. The sideband signals are used to represent the prefetch address information. The current command and sideband signals are sent to the parsing module.

[0010] The parsing module receives the current command and sideband signals, and processes the sideband signals according to the current command to determine the prefetch address information.

[0011] Thirdly, embodiments of this application provide a chip for implementing the information processing method described in the second aspect above.

[0012] Specifically, the chip includes a processor for retrieving and running a computer program from a memory, causing a device equipped with the chip to perform the information processing method described in the second aspect above.

[0013] Fourthly, embodiments of this application provide an electronic device that includes the information processing apparatus described in the first aspect above.

[0014] Fifthly, embodiments of this application also provide another electronic device, including a processor and a memory. The memory is used to store a computer program, and the processor is used to call and run the computer program stored in the memory to perform the information processing method described in the second aspect above.

[0015] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by at least one processor, implements the information processing method described in the second aspect above.

[0016] In a seventh aspect, embodiments of this application provide a computer program product, including computer program instructions that cause a computer to perform the information processing method described in the second aspect above.

[0017] Eighthly, embodiments of this application provide a computer program that, when run on a computer, causes the computer to perform the information processing method described in the second aspect above.

[0018] This application provides an information processing apparatus, method, chip, and device. The information processing apparatus may include a generation module and a parsing module. The generation module is used to acquire the current command and prefetch address information, and generate a sideband signal based on the current command and prefetch address information, the sideband signal being used to characterize the prefetch address information; it also sends the current command and sideband signal to the parsing module. The parsing module is used to receive the current command and sideband signal, and parse the sideband signal according to the current command to determine the prefetch address information. In this way, the generation module can send the prefetch address information to the parsing module in the form of a sideband signal, instead of sending it through the existing AXI read or write channel. Therefore, when the DMA transmits the prefetch address information to the SMMU, it does not require adding an additional AXI write channel, nor does it occupy the bandwidth of the existing AXI write channel, thereby improving device performance. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the composition structure of an information processing device provided in an embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the composition structure of another information processing device provided in the embodiments of this application.

[0021] Figure 3 This is a schematic diagram of the composition structure of another information processing device provided in the embodiments of this application.

[0022] Figure 4 This is a schematic diagram of the framework of an electronic device provided in an embodiment of this application.

[0023] Figure 5 This is a flowchart illustrating an information processing method provided in an embodiment of this application.

[0024] Figure 6 This is a schematic structural diagram of an electronic device provided in an embodiment of this application.

[0025] Figure 7 This is a schematic structural diagram of another electronic device provided in the embodiments of this application.

[0026] Figure 8 This is a schematic structural diagram of a chip provided in an embodiment of this application. Detailed Implementation

[0027] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0029] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] It should also be noted that the terms "first, second, and third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0031] In related technologies, the SMMU and peripherals can exchange information. The peripherals can send address information to the SMMU, and after receiving the address information, the SMMU can provide page table translation functionality to convert the address information into the correct physical address information.

[0032] It should be understood that the address information sent by the peripheral device to the SMMU is usually virtual address information. After receiving the virtual address information, the SMMU usually needs to convert the virtual address information to obtain the physical address information corresponding to the virtual address information.

[0033] It should also be understood that when a peripheral sends address information to the SMMU, it can be understood as the DMA in the peripheral sending address information to the SMMU.

[0034] It should be noted that DMA typically sends address information to the SMMU via the AXI write channel.

[0035] For example, the DMA can send the current address information to the SMMU through the AXI write channel. After receiving the current address information, the SMMU can convert the current address information to obtain the physical address information corresponding to the current address information.

[0036] In multimedia systems, DMA typically accesses memory via AXI. To improve performance and reduce read / write latency, DMA can prefetch address information (prefetch command) to the SMMU via the AXI write channel. Upon receiving this prefetch address information, the SMMU can convert it into physical address information, allowing it to retrieve the page table in advance. This avoids the problem of the SMMU receiving the actual address information before retrieving the page table, thus improving performance and reducing read / write latency. The operation of the SMMU retrieving the page table in advance is called prefetching.

[0037] However, since the AXI read channel and AXI write channel are generally used independently, when the DMA sends prefetch address information to the SMMU through the AXI write channel, it usually has the following drawbacks: On the one hand, if the DMA uses the existing AXI read channel to send prefetch address information, an additional AXI write channel is required. On the other hand, if the DMA uses the existing AXI write channel to send prefetch address information, it consumes additional bandwidth, thus affecting performance; in addition, since the prefetch command (prefetch address information) is inserted into the normal write address command, it also affects the original write channel control.

[0038] Based on this, embodiments of this application provide an information processing apparatus, which may include a generation module and a parsing module. The generation module is used to acquire the current command and prefetch address information, and to generate a sideband signal based on the current command and prefetch address information, the sideband signal being used to characterize the prefetch address information; it also sends the current command and sideband signal to the parsing module. The parsing module is used to receive the current command and sideband signal, and to parse the sideband signal based on the current command to determine the prefetch address information. In this way, the generation module can send the prefetch address information to the parsing module in the form of a sideband signal, instead of sending it through the existing AXI read channel or AXI write channel. Thus, when the DMA transmits prefetch address information to the SMMU, neither an additional AXI write channel nor the bandwidth of the existing AXI write channel is required, thereby improving device performance.

[0039] Figure 1 This is a schematic diagram of the structural composition of an information processing device 100 provided in an embodiment of this application. Figure 1 As shown, the information processing device 100 includes a generation module 110 and a parsing module 120, wherein:

[0040] The generation module 110 is used to acquire the current command and prefetch address information, and generate sideband signals based on the current command and prefetch address information. The sideband signals are used to characterize the prefetch address information. The current command and sideband signals are sent to the parsing module.

[0041] The parsing module 120 is used to receive the current command and the sideband signal, and to parse and process the sideband signal according to the current command to determine the prefetch address information.

[0042] It should be noted that the generation module 110 can be integrated into the DMA mentioned in the foregoing embodiments.

[0043] In this embodiment of the application, the current command is known to the generation module 110, so the generation module 110 can directly obtain the current command.

[0044] In some embodiments, the current command may include a read command and / or a write command.

[0045] It should be noted that the read command can be used to perform a read operation on the storage unit indicated by the address information in order to read the data information corresponding to that address information.

[0046] For example, if the address information is prefetch address information, the read command can be used to perform a read operation on the storage unit indicated by the prefetch address information in order to read the data information corresponding to the prefetch address information.

[0047] It should also be noted that the write command can be used to perform a write operation on the storage unit indicated by the address information, so as to write the data information corresponding to that address information.

[0048] For example, if the address information is prefetch address information, the write command can be used to perform a write operation on the storage unit indicated by the prefetch address information to write data information corresponding to the prefetch address information.

[0049] It should be noted that the prefetched address information can be address information at a certain time after the current time, or address information within a certain period after the current time. In other words, the prefetched address information can be predicted future address information. The number of prefetched address information can be one or more, and this application embodiment does not limit this.

[0050] In some embodiments, the generation module 110 can also be used to acquire current data information and determine prefetch address information based on the current data information.

[0051] It should be noted that the current data information is known to the generation module 110, so the generation module 110 can directly obtain the current data information.

[0052] For example, in a multimedia system, taking image processing as an example, the current data information may include at least one of the following: the width and height of the image, the size of each pixel in the image, and the address where the data in the image is stored.

[0053] It should be understood that the generation module 110 determines the prefetch address information based on the current data information, which can be understood as the generation module 110 calculating the address information to be read and written in the future based on the known read and write data information.

[0054] In some embodiments, the current command may carry the current address information.

[0055] It should be noted that the current address information can be the address information at the current moment.

[0056] In some embodiments, the generation module 110 can also be used to determine the prefetching method and the current address information carried in the current command, and to perform conversion processing on the prefetching address information according to the prefetching method and the current address information to generate a sideband signal.

[0057] The prefetching method can be any of the following:

[0058] Positive offset continuous positive prefetch mode, positive offset interval negative prefetch mode, positive offset interval positive prefetch mode, positive offset continuous negative prefetch mode, negative offset continuous positive prefetch mode, negative offset interval positive prefetch mode, negative offset continuous negative prefetch mode, and negative offset interval negative prefetch mode.

[0059] In some embodiments, the sideband signal may include at least one of the following:

[0060] Offset, number of prefetches, prefetch interval, prefetch mode, prefetch direction, and interval direction.

[0061] Let offset be denoted as offset, number of prefetches as number, step as prefetch interval, mode as mode, offset_direct as prefetch direction, and step_direct as interval direction. Then the definitions of each part of the sideband signal are shown in Table 1.

[0062] Table 1

[0063] offset The offset of the current address information relative to the prefetched address information; space is the unit of offset. number Indicates the number of prefetched address information step When there are multiple prefetched address pieces, the interval between each two prefetched address pieces is... mode Based on the offset, is the prefetch performed continuously or at step intervals? offset_direct The direction of the prefetch address relative to the current address; positive direction is addition, negative direction is subtraction. step_direct After offset, the direction between every two prefetches is either positive for addition or negative for subtraction.

[0064] It should be noted that the value of space can be 4KB or other values. In practical applications, it can be defined according to system requirements. This application does not limit this.

[0065] For example, assuming there are three prefetch address information, where curr_addr is the current address information, and the prefetching method is positive offset continuous positive prefetching, the prefetch address information is converted according to the prefetching method and the current address information. The first prefetch address information is curr_addr + offset * space, the second prefetch address information is curr_addr + offset * space + space, and the third prefetch address information is curr_addr + offset * space + 2 * space. Based on the converted prefetch address information, the sideband signal described in Table 1 can be obtained.

[0066] For example, assuming there are three prefetch address information, where curr_addr is the current address information, and the prefetching method is positive offset interval negative prefetching, the prefetch address information is converted according to the prefetching method and the current address information. The first prefetch address information is curr_addr + offset * space, the second prefetch address information is curr_addr + offset * space - step * space, and the third prefetch address information is curr_addr + offset * space - 2 * step * space. Based on the converted prefetch address information, the sideband signal described in Table 1 can be obtained.

[0067] It should be noted that for the six prefetching methods—positive offset interval positive prefetch, positive offset continuous negative prefetch, negative offset continuous positive prefetch, negative offset interval positive prefetch, negative offset continuous negative prefetch, and negative offset interval negative prefetch—the corresponding exemplary descriptions can be found in the two examples mentioned above, and will not be repeated here.

[0068] It should also be noted that the sideband signal obtained by the parsing module 120 may be sent by the generation module 110, and the current command obtained by the parsing module 120 may be obtained through the AXI read channel and / or the AXI write channel.

[0069] In some embodiments, sending the current command and sideband signal to the parsing module may include sending the current command and sideband signal to the parsing module via a first bus bridge.

[0070] For example, the first bus bridge may be an AXI bus bridge.

[0071] In some embodiments, based on Figure 1 The information processing device 100 shown, such as Figure 2 As shown, the information processing device 100 may further include a merging module 210, wherein:

[0072] The merging module 210 can be used to merge the current command and the sideband signal to generate the target command and send the target command to the parsing module 120;

[0073] The parsing module 120 can also be used to receive target commands from the merging module 210, and the target commands include the current command and sideband signals.

[0074] It should be noted that the merging module 210 sending the target command to the parsing module 120 may include: the merging module 210 sending the target command to the parsing module 120 through the first bus bridge.

[0075] It should also be noted that both the merging module 210 and the generating module 110 can be integrated into the DMA.

[0076] It should also be noted that the sideband signal obtained by the merging module 210 may be sent by the generation module 110; the current command obtained by the merging module 210 may be obtained by the merging module through the AXI read channel and / or AXI write channel.

[0077] In some embodiments, the parsing module 120 can also be used to determine the current address information carried in the current command, and to parse and process the sideband signal according to the current address information to determine the prefetch address information.

[0078] It should be noted that, in the embodiments of this application, based on Figure 1 The information processing device 100 shown, such as Figure 3 As shown, the information processing device 100 may further include a memory management module 310, wherein:

[0079] The memory management module 310 is used to receive prefetch address information from the parsing module 120, and perform address mapping based on the prefetch address information to determine physical address information; wherein, the physical address information is used to indicate the storage unit to be read or written.

[0080] It should be noted that the memory management module 310 may be the SMMU mentioned in the aforementioned embodiments.

[0081] For example, the memory management module 310 can provide a page table translation function to convert prefetch address information into correct physical address information and perform read and write operations on the memory cell indicated by the physical address information according to the current command.

[0082] This application provides an information processing apparatus, which may include a generation module and a parsing module. The generation module is used to acquire the current command and prefetch address information, and to generate a sideband signal based on the current command and prefetch address information, the sideband signal being used to characterize the prefetch address information; it also sends the current command and sideband signal to the parsing module. The parsing module is used to receive the current command and sideband signal, and to parse the sideband signal according to the current command to determine the prefetch address information. In this way, the generation module can send the prefetch address information to the parsing module in the form of a sideband signal, instead of sending it through the existing AXI read or write channel. Therefore, when the DMA transmits the prefetch address information to the SMMU, it does not require adding an additional AXI write channel, nor does it occupy the bandwidth of the existing AXI write channel, thereby improving device performance.

[0083] The information processing device provided in the above embodiments will be described in detail below in conjunction with specific application scenarios.

[0084] Figure 4A schematic diagram of the framework of an electronic device according to an embodiment of this application is shown. Figure 4 As shown, the electronic device includes a generation module 410, a merging module 420, a parsing module 430, and a memory management module 440. The generation module 410 and the merging module 420 can be integrated into a DMA read module and / or a DMA write module. The DMA read module may also include an AXI read channel, and the DMA write module may also include an AXI write channel.

[0085] It should be noted that the number of DMA read modules can be one or more; the number of DMA write modules can also be one or more, and this application embodiment does not limit this.

[0086] In some embodiments, the current command may include a read command and / or a write command.

[0087] It should be understood that the AXI read channel represents the regular AXI read control logic, which can be used to transmit read commands; if an additional AXI write channel is added on top of the AXI read channel, the AXI read channel can also be used to transmit address information.

[0088] It should also be understood that the AXI write channel represents the regular AXI write control logic and can be used to transmit write commands; in addition, the AXI write channel can also be used to transmit address information.

[0089] Figure 4 The functions of each module in the electronic device shown are as follows.

[0090] (1) Generation module 410: also known as prefetch information generation module 410. Generation module 410 can be generation module 110 in the aforementioned embodiments. Generation module 410 is added to a conventional AXI read channel or AXI write channel. This generation module 410 can obtain the current command and prefetch address information, and generate sideband signals based on the current command and prefetch address information.

[0091] Among them, the sideband signal is used to characterize the prefetch address information.

[0092] In this embodiment of the application, the current command is known to the generation module 410, so the generation module 410 can directly obtain the current command.

[0093] It should be noted that the prefetched address information can be address information at a certain time after the current time, or address information within a certain period after the current time. In other words, the prefetched address information can be predicted future address information. The number of prefetched address information can be one or more, and this application embodiment does not limit this.

[0094] In some embodiments, the generation module 410 can also be used to acquire current data information and determine prefetch address information based on the current data information.

[0095] It should be noted that the current data information is known to the generation module 410, so the generation module 410 can directly obtain the current data information.

[0096] For example, in a multimedia system, taking image processing as an example, the current data information may include at least one of the following: the width and height of the image, the size of each pixel in the image, and the address where the data in the image is stored.

[0097] It should be understood that the generation module 410 determines the prefetch address information based on the current data information, which can be understood as the generation module 410 calculating the address information to be read and written in the future based on the known read and write data information.

[0098] In some embodiments, the current command may carry the current address information.

[0099] It should be noted that the current address information can be the address information at the current moment.

[0100] In some embodiments, the generation module 410 can also be used to determine the prefetching method and the current address information carried in the current command, and to perform conversion processing on the prefetching address information according to the prefetching method and the current address information to generate a sideband signal.

[0101] The prefetching method can be any of the following:

[0102] Positive offset continuous positive prefetch mode, positive offset interval negative prefetch mode, positive offset interval positive prefetch mode, positive offset continuous negative prefetch mode, negative offset continuous positive prefetch mode, negative offset interval positive prefetch mode, negative offset continuous negative prefetch mode, and negative offset interval negative prefetch mode.

[0103] In some embodiments, the sideband signal may include at least one of the following: offset, prefetch quantity, prefetch interval, prefetch mode, prefetch direction, and interval direction. The definitions of each part of the sideband signal may be as shown in Table 1 above.

[0104] For example, when the prefetching method is positive offset continuous positive prefetching, the first prefetch address is curr_addr + offset * space, the second prefetch address is curr_addr + offset * space + space, the third prefetch address is curr_addr + offset * space + 2 * space, and so on; when the prefetching method is positive offset interval negative prefetching, the first prefetch address is curr_addr + offset * space, the second prefetch address is curr_addr + offset * space - step * space, the third prefetch address is curr_addr + offset * space - step * space, and so on. The address information is fetched as curr_addr + offset * space - 2 * step * space, etc., where curr_addr represents the address information of the current AXI command (current address information), the number of address information to be fetched is determined by number, and space represents the unit of offset. For positive offset interval positive prefetch, positive offset continuous negative prefetch, negative offset continuous positive prefetch, negative offset interval positive prefetch, negative offset continuous negative prefetch, and negative offset interval negative prefetch, the calculation method of the prefetch address information is similar to that of positive offset continuous positive prefetch and positive offset interval negative prefetch, the difference is that the positive and negative calculation signs and step need to be modified.

[0105] In some embodiments, after the generation module 410 obtains the sideband signal, it can send the sideband signal to the merging module 420.

[0106] (2) Merging module 420: The merging module 420 can be the merging module 210 in the aforementioned embodiments. It can be used to merge the current command and the sideband signal to generate the target command.

[0107] It should also be noted that the sideband signal obtained by the merging module 420 can be sent by the generation module 410; the current command obtained by the merging module 420 can be obtained through the AXI read channel and / or the AXI write channel.

[0108] In some embodiments, the merging module 420 can send the target command to the parsing module 430 via the AXI bus bridge.

[0109] In some embodiments, the merging module 420 may also send the current command to the memory management unit 440.

[0110] (3) Parsing module 430: also known as prefetch sideband signal parsing module 430. Parsing module 430 can be parsing module 120 in the foregoing embodiments. Parsing module 430 can be used to receive a target command from merging module 420, the target command including the current command and sideband signals, and to parse the sideband signals according to the current command to determine the prefetch address information.

[0111] In some embodiments, the parsing module 430 can also be used to determine the current address information carried in the current command, and to parse and process the sideband signal according to the current address information to determine the prefetch address information.

[0112] In some embodiments, the parsing module 430 may send prefetch address information to the memory management module 440.

[0113] Furthermore, the parsing module 430 can send the current command to the memory management module 440.

[0114] (4) Memory Management Module 440: Also known as SMMU. Memory Management Module 440 can be Memory Management Module 310 in the aforementioned embodiments. Memory Management Module 440 can be used to receive prefetch address information from Parsing Module 430, and perform address mapping based on the prefetch address information to determine physical address information.

[0115] The physical address information is used to indicate the storage unit where the read / write operation is to be performed.

[0116] In some embodiments, the memory management module 440 may receive a current command from the parsing module 430; and / or, the memory management module 440 may also receive a current command from the merging module 420.

[0117] For example, the memory management module 440 can provide a page table translation function to convert prefetch address information into correct physical address information and perform read and write operations on the memory cell indicated by the physical address information according to the current command.

[0118] In this embodiment, by using sideband signals to transmit prefetch address information, the prefetch function can be implemented without affecting the original design. It does not require adding a write channel to the AXI read channel, nor does it consume additional bandwidth, thus avoiding any impact on performance. Because a unified prefetch sideband signal parsing module is used, any changes to the SMMU can be made to the prefetch sideband signal parsing module without affecting the DMA read or write design.

[0119] In the embodiments of this application, on the one hand, the technical solution provided by the embodiments of this application is simple to integrate. It can add a prefetch information generation module without affecting any original design, and can merge the result (prefetch address information) into the sideband signal of AXI. On the other hand, the technical solution provided by the embodiments of this application can also simplify the design. It can realize the prefetch function without adding an AXI write channel to the AXI read channel. Furthermore, since the technical solution provided by the embodiments of this application transmits the prefetch address information through the sideband signal, it does not need to occupy the write channel to send the prefetch address information, and will not consume bandwidth, thus not affecting the performance.

[0120] The preferred embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this application, various simple modifications can be made to the technical solutions of this application, and these simple modifications all fall within the protection scope of this application. For example, the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this application will not describe the various possible combinations separately. Furthermore, various different embodiments of this application can also be arbitrarily combined, as long as they do not violate the spirit of this application, they should also be considered as the content disclosed in this application. Moreover, without conflict, the various embodiments and / or the technical features in the various embodiments described in this application can be arbitrarily combined with the prior art, and the resulting technical solutions should also fall within the protection scope of this application.

[0121] Based on the same inventive concept as the foregoing embodiments. Figure 5 A flowchart illustrating an information processing method provided in an embodiment of this application is shown. Figure 5 As shown, the information processing method may include the following steps:

[0122] S510 obtains the current command and prefetch address information through the generation module, and generates a sideband signal based on the current command and prefetch address information. The sideband signal is used to represent the prefetch address information. The current command and sideband signal are sent to the parsing module.

[0123] The S520 receives the current command and sideband signals through the parsing module, and performs parsing and processing on the sideband signals according to the current command to determine the prefetch address information.

[0124] It should be noted that, in the embodiments of this application, the information processing method can be applied to an information processing device or an electronic device integrated with such a device. The electronic device can be implemented in various forms, such as smartphones, tablets, laptops, handheld computers, personal digital assistants (PDAs), portable media players (PMPs), navigation devices, wearable devices, digital cameras, etc., and is not limited thereto.

[0125] It should also be noted that the generation module can be integrated into the DMA mentioned in the foregoing embodiments.

[0126] In this embodiment of the application, the current command is known to the generation module, so the current command can be directly obtained through the generation module.

[0127] In some embodiments, the current command may include a read command and / or a write command.

[0128] It should be noted that the read command can be used to perform a read operation on the storage unit indicated by the address information in order to read the data information corresponding to that address information.

[0129] For example, if the address information is prefetch address information, the read command can be used to perform a read operation on the storage unit indicated by the prefetch address information in order to read the data information corresponding to the prefetch address information.

[0130] It should also be noted that the write command can be used to perform a write operation on the storage unit indicated by the address information, so as to write the data information corresponding to that address information.

[0131] For example, if the address information is prefetch address information, the write command can be used to perform a write operation on the storage unit indicated by the prefetch address information to write data information corresponding to the prefetch address information.

[0132] It should be noted that the prefetched address information can be address information at a certain time after the current time, or address information within a certain period after the current time. In other words, the prefetched address information can be predicted future address information. The number of prefetched address information can be one or more, and this application embodiment does not limit this.

[0133] In some embodiments, obtaining prefetch address information through the generation module may include: obtaining current data information through the generation module; and determining prefetch address information based on the current data information.

[0134] It should be noted that the current data information is known to the generation module, so the current data information can be obtained directly through the generation module.

[0135] For example, in a multimedia system, taking image processing as an example, the current data information may include at least one of the following: the width and height of the image, the size of each pixel in the image, and the address where the data in the image is stored.

[0136] It should be understood that determining the prefetch address information based on the current data information can be understood as calculating the address information to be read and written in the future based on the known read and write data information.

[0137] In some embodiments, the current command may carry the current address information.

[0138] It should be noted that the current address information can be the address information at the current moment.

[0139] In some embodiments, the generation module generates a sideband signal based on the current command and prefetch address information, which may include: the generation module determining the prefetch method and the current address information carried in the current command; and performing conversion processing on the prefetch address information based on the prefetch method and the current address information to generate the sideband signal.

[0140] The prefetching method can be any of the following:

[0141] Positive offset continuous positive prefetch mode, positive offset interval negative prefetch mode, positive offset interval positive prefetch mode, positive offset continuous negative prefetch mode, negative offset continuous positive prefetch mode, negative offset interval positive prefetch mode, negative offset continuous negative prefetch mode, and negative offset interval negative prefetch mode.

[0142] In some embodiments, the sideband signal may include at least one of the following:

[0143] Offset, number of prefetches, prefetch interval, prefetch mode, prefetch direction, and interval direction.

[0144] The definitions of each part of the sideband signal can be shown in Table 1 above.

[0145] In some embodiments, sending the current command and sideband signal to the parsing module may include sending the current command and sideband signal to the parsing module via a first bus bridge.

[0146] For example, the first bus bridge may be an AXI bus bridge.

[0147] In some embodiments, receiving the current command and sideband signals through the parsing module may include: merging the current command and sideband signals through the merging module to generate a target command, and sending the target command to the parsing module; receiving the target command from the merging module through the parsing module, wherein the target command includes the current command and sideband signals.

[0148] It should be noted that sending the target command to the parsing module can include sending the target command to the parsing module via the first bus bridge.

[0149] It should also be noted that both the merging module and the generating module can be integrated into the DMA.

[0150] It should also be noted that the sideband signal obtained by the merging module can be sent by the generation module; the current command obtained by the merging module can be obtained through the AXI read channel and / or the AXI write channel.

[0151] In some embodiments, parsing and processing the sideband signal according to the current command to determine the prefetch address information may include: determining the current address information carried in the current command; and parsing and processing the sideband signal according to the current address information to determine the prefetch address information.

[0152] It should be noted that, in the embodiments of this application, the method may further include: receiving prefetch address information from the parsing module through the memory management module, and performing address mapping based on the prefetch address information to determine physical address information; wherein, the physical address information is used to indicate the storage unit to be read or written.

[0153] It should be noted that the memory management module can be the SMMU mentioned in the aforementioned embodiments.

[0154] For example, the memory management module can provide page table translation functionality to convert prefetched address information into correct physical address information, and perform read and write operations on the memory cell indicated by the physical address information according to the current command.

[0155] This application provides an information processing method. A generation module acquires the current command and prefetch address information, and generates a sideband signal based on the current command and prefetch address information. The sideband signal represents the prefetch address information. The current command and sideband signal are sent to a parsing module. The parsing module receives the current command and sideband signal, and parses the sideband signal according to the current command to determine the prefetch address information. This allows the generation module to send the prefetch address information to the parsing module in the form of a sideband signal, instead of sending it through the existing AXI read or write channel. Therefore, when the DMA transmits the prefetch address information to the SMMU, it does not require an additional AXI write channel, nor does it occupy the bandwidth of the existing AXI write channel, thereby improving device performance.

[0156] Those skilled in the art should understand that the description of the information processing method in the embodiments of this application can be understood with reference to the description of the information processing device in the embodiments of this application.

[0157] Figure 6 This is a schematic structural diagram of an electronic device 600 provided in an embodiment of this application. Figure 6 As shown, the electronic device 600 includes a processor 610 and a memory 620. The memory 620 can store computer programs, and the processor 610 can call and run the computer programs from the memory 620 to implement the methods in the embodiments of this application.

[0158] The memory 620 can be a separate device independent of the processor 610, or it can be integrated into the processor 610.

[0159] In some embodiments, such as Figure 6 As shown, the electronic device 600 may also include a transceiver 630, which the processor 610 can control to communicate with other devices. Specifically, it can send information or data to other devices or receive information or data sent by other devices.

[0160] The transceiver 630 may include a transmitter and a receiver. The transceiver 630 may further include antennas, and the number of antennas may be one or more.

[0161] In some embodiments, such as Figure 7 As shown, this application embodiment also provides another composition of electronic device 700, wherein electronic device 700 may include the information processing device 100 as described in any of the foregoing embodiments.

[0162] Figure 8 This is a schematic structural diagram of a chip provided in an embodiment of this application. For example... Figure 8As shown, chip 800 includes processor 810, which can call and run computer programs from memory to implement the methods in the embodiments of this application.

[0163] In some embodiments, such as Figure 8 As shown, chip 800 may further include memory 820. Processor 810 can retrieve and run computer programs from memory 820 to implement the methods described in this embodiment.

[0164] The memory 820 can be a separate device independent of the processor 810, or it can be integrated into the processor 810.

[0165] In some embodiments, the chip 800 may further include an input interface 830. The processor 810 can control the input interface 830 to communicate with other devices or chips; specifically, it can acquire information or data sent by other devices or chips.

[0166] In some embodiments, the chip 800 may further include an output interface 840. The processor 810 can control the output interface 840 to communicate with other devices or chips; specifically, it can output information or data to other devices or chips.

[0167] In some embodiments, the chip can be applied to the electronic device described in this application, which will not be elaborated further here for the sake of brevity.

[0168] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0169] It is understood that the processor in the embodiments of this application may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0170] It is also understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate Synchronous DRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0171] It is also understood that the above-described memory is exemplary and not a limiting description. For example, the memory in the embodiments of this application may also be Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Dynch Link Dynamic Random Access Memory (SLDRAM), and Direct Rambus RAM (DRRAM), etc. In other words, the memory in the embodiments of this application is intended to include, but is not limited to, these and any other suitable types of memory.

[0172] This application also provides a computer-readable storage medium for storing computer programs.

[0173] In some embodiments, the computer-readable storage medium may be applied to the electronic device in the embodiments of this application, and when the computer program is executed by at least one processor, it implements the corresponding processes implemented by the electronic device in the various methods of the embodiments of this application. For the sake of brevity, these will not be described in detail here.

[0174] This application also provides a computer program product, including computer program instructions.

[0175] In some embodiments, the computer program product can be applied to the electronic device in the embodiments of this application, and the computer program instructions cause the computer to execute the corresponding processes implemented by the electronic device in the various methods of the embodiments of this application. For the sake of brevity, they will not be described in detail here.

[0176] This application also provides a computer program.

[0177] In some embodiments, the computer program can be applied to the electronic device in the embodiments of this application. When the computer program is run on a computer, it causes the computer to execute the corresponding processes implemented by the electronic device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0178] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0179] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and unit can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0180] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0181] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0182] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0183] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0184] It should be understood that in the various method embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0185] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0186] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0187] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0188] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0189] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0190] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An information processing device, characterized in that, The information processing device includes a generation module and a parsing module, wherein: The generation module is used to acquire the current command and prefetch address information, and to generate a sideband signal based on the current command and the prefetch address information; the sideband signal includes at least one of the following: offset, prefetch quantity, prefetch interval, prefetch mode, prefetch direction, and interval direction, and the sideband signal is used to characterize the prefetch address information; and to send the current command and the sideband signal to the parsing module. The parsing module is used to receive the current command and the sideband signal, and to parse the sideband signal according to the current command to determine the prefetch address information.

2. The apparatus according to claim 1, characterized in that, The generation module is also used to acquire current data information and determine the prefetch address information based on the current data information.

3. The apparatus according to claim 1, characterized in that, The generation module is further configured to determine the prefetching method and the current address information carried in the current command, and to perform conversion processing on the prefetching address information according to the prefetching method and the current address information to generate the sideband signal.

4. The apparatus according to claim 3, characterized in that, The prefetching method is any one of the following: Positive offset continuous positive prefetch mode, positive offset interval negative prefetch mode, positive offset interval positive prefetch mode, positive offset continuous negative prefetch mode, negative offset continuous positive prefetch mode, negative offset interval positive prefetch mode, negative offset continuous negative prefetch mode, and negative offset interval negative prefetch mode.

5. The apparatus according to claim 1, characterized in that, The information processing device further includes a merging module, wherein: The merging module is used to merge the current command and the sideband signal to generate a target command, and send the target command to the parsing module; The parsing module is further configured to receive the target command from the merging module, and the target command includes the current command and the sideband signal.

6. The apparatus according to claim 1, characterized in that, The parsing module is further configured to determine the current address information carried in the current command, and to parse the sideband signal based on the current address information to determine the prefetch address information.

7. The apparatus according to any one of claims 1 to 6, characterized in that, The device further includes a memory management module, wherein: The memory management module is used to receive the prefetch address information from the parsing module, and perform address mapping based on the prefetch address information to determine the physical address information; wherein, the physical address information is used to indicate the storage unit to be read or written.

8. The apparatus according to any one of claims 1 to 6, characterized in that, The current command includes read commands and / or write commands.

9. An information processing method, characterized in that, The method includes: The current command and prefetch address information are obtained by the generation module, and a sideband signal is generated based on the current command and the prefetch address information. The sideband signal includes at least one of the following: offset, prefetch quantity, prefetch interval, prefetch mode, prefetch direction, and interval direction. The sideband signal is used to characterize the prefetch address information. The current command and the sideband signal are sent to the parsing module. The parsing module receives the current command and the sideband signal, and performs parsing processing on the sideband signal according to the current command to determine the prefetch address information.

10. The method according to claim 9, characterized in that, Obtaining the prefetch address information includes: Get current data information; The prefetch address information is determined based on the current data information.

11. The method according to claim 9, characterized in that, The step of generating sideband signals based on the current command and the prefetch address information includes: Determine the prefetching method and the current address information carried in the current command; The prefetch address information is converted according to the prefetch method and the current address information to generate the sideband signal.

12. The method according to claim 11, characterized in that, The prefetching method is any one of the following: Positive offset continuous positive prefetch mode, positive offset interval negative prefetch mode, positive offset interval positive prefetch mode, positive offset continuous negative prefetch mode, negative offset continuous positive prefetch mode, negative offset interval positive prefetch mode, negative offset continuous negative prefetch mode, and negative offset interval negative prefetch mode.

13. The method according to claim 9, characterized in that, The step of receiving the current command and the sideband signal through the parsing module includes: The current command and the sideband signal are merged by the merging module to generate a target command, which is then sent to the parsing module. The parsing module receives the target command from the merging module, and the target command includes the current command and the sideband signal.

14. The method according to claim 9, characterized in that, The step of parsing and processing the sideband signal according to the current command to determine the prefetch address information includes: Determine the current address information carried in the current command; The sideband signal is parsed and processed based on the current address information to determine the prefetch address information.

15. The method according to any one of claims 9 to 14, characterized in that, The method further includes: The memory management module receives the prefetch address information from the parsing module and performs address mapping based on the prefetch address information to determine the physical address information; wherein, the physical address information is used to indicate the storage unit to be read or written.

16. The method according to any one of claims 9 to 14, characterized in that, The current command includes read commands and / or write commands.

17. A chip, characterized in that, Includes: a processor for retrieving and running a computer program from memory, causing a device on which the chip is mounted to perform the method as described in any one of claims 9 to 16.

18. An electronic device, characterized in that, The electronic device includes an information processing apparatus as described in any one of claims 1 to 8.

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