A chip packaging structure design method and related equipment

Abstract

The present application discloses a design method and related equipment for a chip packaging structure, including a packaging substrate, a bare chip and a packaging cover; the bare chip is located on one side of the packaging substrate and is electrically connected to the packaging substrate; the packaging cover is located on the side of the bare chip away from the packaging substrate, and the packaging cover and the packaging substrate form a closed space, and the bare chip is located in the closed space; the packaging cover includes a first part and a second part; the second part is located around the first part, the thickness of the first part is greater than the thickness of the second part, and the bare chip is fixed between the first part and the packaging substrate, so that the first part with larger thickness and heavier weight can resist the warping of the chip packaging structure and protect the bare chip from damage, and the second part with smaller thickness and lighter weight can reduce the weight of the entire packaging cover, reduce the risk of process problems such as solder joint collapse and bridging in the chip packaging structure due to the excessive weight of the packaging cover, and improve the packaging yield of the chip packaging structure.

Description

[0001] This application is a divisional application of the invention patent with the invention name "A chip packaging structure, its design method and related equipment", application number 202211498279.1, and the application date of the parent case is November 28, 2022. Technical Field

[0002] The present application relates to the field of chip packaging technology, and in particular to a design method for a chip packaging structure and related equipment. Background Art

[0003] As the size of chip packaging structures becomes larger and larger, the packaging cover in the chip packaging structure is also getting thicker to resist the increasing warping of the chip packaging structure after undergoing the heating process and protect the key components of the chip packaging structure from damage. However, this will result in a heavier packaging cover, which may easily lead to problems such as solder joint collapse and bridging in the chip packaging structure. Summary of the Invention

[0004] The present application discloses a chip packaging structure design method and related equipment to reduce the risk of problems such as solder joint collapse and bridging in the chip packaging structure.

[0005] In a first aspect, the present application discloses a design method for a chip packaging structure, the chip packaging structure comprising a packaging substrate, a bare die, and a packaging cover, wherein the bare die is located on one side of the packaging substrate and is electrically connected to the packaging substrate, the packaging cover is located on a side of the bare die facing away from the packaging substrate, and the packaging cover and the packaging substrate enclose a closed space, the bare die is located within the closed space, the packaging cover comprises a first portion and a second portion, the second portion being located around the first portion, the thickness of the first portion being greater than the thickness of the second portion, and the bare die being fixed between the first portion and the packaging substrate, the design method comprising: The method includes obtaining structural parameters of the package substrate and the bare die; determining multiple sets of structural parameters of the package cover based on the structural parameters of the package substrate and the bare die, wherein the structural parameters of the first portion and / or the second portion in the multiple sets of structural parameters are different; simulating the chip package structure based on the structural parameters of the package substrate, the structural parameters of the bare die, and the multiple sets of structural parameters of the package cover to obtain multiple deformation values ​​of the chip package structure, wherein the multiple deformation values ​​correspond one-to-one to the multiple sets of structural parameters; and determining the structural parameter corresponding to the smallest of the multiple deformation values ​​as the optimal structural parameter of the chip package structure. The first portion with the optimal structural parameters is used to resist warping of the chip package structure and protect the bare die from damage, while the second portion with the optimal structural parameters is used to reduce the weight of the entire package cover, thereby reducing the risk of process problems such as solder joint collapse and bridging in the chip package structure caused by excessive weight of the package cover, thereby improving the packaging yield of the chip package structure.

[0006] In some optional examples, the structural parameters include at least shape, material and size, and determining the multiple sets of structural parameters of the packaging cover shell includes: combining multiple shapes, multiple materials and multiple sizes of the first part and the second part in the packaging cover shell to obtain multiple sets of structural parameters of the packaging cover shell.

[0007] In some optional examples, the cross-sectional shape of the first portion includes a trapezoid.

[0008] In some optional examples, the first part includes a first surface and a second surface arranged opposite to each other, the area of ​​the first surface is greater than or equal to the area of ​​the bare chip, and the first surface is fixedly connected to the bare chip; the second part includes a third surface and a fourth surface arranged opposite to each other, the second surface and the fourth surface are located in the same plane, and the distance between the first surface and the plane is greater than the distance between the third surface and the plane, so as to increase the height of the enclosed space and improve the heat dissipation capacity of the enclosed space for the bare chip.

[0009] In some optional examples, the first part also includes a fifth surface, which is located between the first surface and the second surface; the fifth surface includes a plane, and the angle between the fifth surface and the first surface is an acute angle or an obtuse angle; or, the fifth surface is a curved surface, and the curved surface protrudes in a direction away from the first part, so as to alleviate the problem of stress concentration at the edge of the die through the fifth surface, reduce the risk of die breakage, and improve its reliability.

[0010] In some optional examples, the first part includes a first surface, which is used to be fixedly connected to the bare chip; the first surface has a plurality of micro grooves, which are used to accommodate connecting materials between the first surface and the bare chip to avoid excessive flow of connecting materials due to the heavy weight of the packaging cover, thereby avoiding affecting the connection effect between the packaging cover and the bare chip due to excessive flow of connecting materials.

[0011] In some optional examples, the first part includes a microchannel, which is at least partially located inside the first part. The microchannel is used to dissipate heat from the packaging cover and the bare chip through a coolant flowing therein, so as to improve the heat dissipation capacity of the packaging cover and extend the service life of the chip packaging structure.

[0012] In some optional examples, the packaging cover shell is surrounded by packaging retaining walls; the packaging retaining walls are used to be fixedly connected to the packaging substrate so that the packaging cover shell and the packaging substrate form a closed space for accommodating the bare chip; the packaging retaining wall has reinforcing ribs or ribs on the side surface facing the packaging substrate to prevent warping of the packaging substrate due to its excessive size.

[0013] In a second aspect, the present application discloses a computer device comprising a memory and a processor; the memory is used to store instructions; the processor is used to execute the chip packaging structure design method as described in any one of the above items according to the instructions stored in the memory.

[0014] In a third aspect, the present application discloses a computer-readable storage medium storing instructions for executing the chip packaging structure design method as described in any one of the above items.

[0015] In a fourth aspect, the present application discloses a computer program for executing instructions of the chip packaging structure design method as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0017] Figure 1This is a schematic cross-sectional view of a chip packaging structure disclosed in this application.

[0018] Figure 2 This is a schematic top view of a chip packaging structure disclosed in an embodiment of the present application.

[0019] Figure 3 for Figure 2 The chip packaging structure is shown as a schematic cross-sectional view along cutting line AA′.

[0020] Figure 4 This is a bottom-view structural diagram of a package cover in a chip package structure disclosed in an embodiment of the present application.

[0021] Figure 5 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application.

[0022] Figure 6 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application.

[0023] Figure 7 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application.

[0024] Figure 8 This is a bottom-view structural diagram of a package cover in another chip package structure disclosed in an embodiment of the present application.

[0025] Figure 9 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application.

[0026] Figure 10 This is a bottom-view structural diagram of a package cover in another chip package structure disclosed in an embodiment of the present application.

[0027] Figure 11 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application.

[0028] Figure 12 This is a schematic top view of another chip packaging structure disclosed in an embodiment of the present application.

[0029] Figure 13 for Figure 12 The chip packaging structure is shown as a schematic cross-sectional view along cutting line BB′.

[0030] Figure 14 This is a schematic diagram of the structure of a microfluidic channel disclosed in an embodiment of the present application.

[0031] Figure 15 This is a schematic top view of another chip packaging structure disclosed in an embodiment of the present application.

[0032] Figure 16 for Figure 15 The chip packaging structure is shown as a schematic cross-sectional view along cutting line CC′.

[0033] Figure 17 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application.

[0034] Figure 18 This is a flow chart of a chip packaging structure design method disclosed in an embodiment of the present application.

[0035] Figure 19 This is a schematic structural diagram of a packaging cover shell disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will describe the technical solutions in the embodiments of this application in conjunction with the accompanying drawings. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0037] The current chip packaging structure is mostly a flip chip structure, which is a pinless structure. Figure 1 As shown, Figure 1 The cross-sectional view of a chip package structure disclosed in this application includes a bare die 22, a package substrate 21, and a package cover 20. The bare die 22 is fixed between the package substrate 21 and the package cover 20, and the bare die 22 can be electrically connected to the package substrate 21 via solder balls 220.

[0038] like Figure 1 As shown, the package cover 20 and the package substrate 21 enclose an enclosed space for accommodating the die 22 and providing mechanical protection for the die 22. As chip packaging structures grow larger, the package cover 20 becomes thicker to prevent the chip packaging structure from warping during the heating process and protect key components of the chip packaging structure, such as the die 22, from damage. However, the thicker the package cover 20, the heavier it is. An overweight package cover 20 can cause problems in the chip packaging structure, such as collapsed solder joints where the solder balls 210 are located and bridging between adjacent solder joints.

[0039] Based on this, the present application discloses a chip packaging structure, in which the thickness of the portion of the packaging cover corresponding to the bare chip is greater than the thickness of the surrounding portion, thereby reducing the weight of the packaging cover and reducing the risk of problems such as solder joint collapse and bridging in the chip packaging structure.

[0040] As an optional implementation of the disclosure of this application, the embodiment of this application discloses a chip packaging structure, which can also be called a chip, and the chip includes a processor chip and a server chip. Figure 2 and Figure 3 As shown, Figure 2 This is a schematic top view of a chip packaging structure disclosed in an embodiment of the present application. Figure 3 for Figure 2 The chip packaging structure shown is a schematic cross-sectional view along the cutting line AA′. The chip packaging structure includes a packaging substrate 21 , a bare chip 22 and a packaging cover 20 .

[0041] The bare die 22 is located on one side of the package substrate 21 and is electrically connected to the package substrate 21. The package cover 20 is located on the side of the bare die 22 away from the package substrate 21. The package cover 20 and the package substrate 21 form a closed space, and the bare die 22 is located in the closed space.

[0042] The package cover 20 includes a first portion 201 and a second portion 202, wherein the second portion 202 is located around the first portion 201. The thickness of the first portion 201 is greater than that of the second portion 202. The die 22 is fixed between the first portion 201 and the package substrate 21.

[0043] During the packaging process of the die 22, the die 22 is heated to establish an electrical connection between the die 22 and the packaging substrate 21. However, due to the mismatch in thermal expansion coefficients between the packaging substrate 21 and the die 22, the chip package structure may warp. By making the thickness of the first portion 201 greater than the thickness of the second portion 202, the thicker and heavier first portion 201 can resist warping of the chip package structure, protecting the die 22 from damage and reducing the probability of chip package failure. The thinner and lighter second portion 202 reduces the weight of the entire package cover 20, reducing the risk of process problems such as solder joint collapse and bridging caused by the excessive weight of the package cover 20 during the packaging process.

[0044] In some embodiments of the present application, Figure 2 As shown, the first portion 201 is located in the middle area of ​​the package cover 20, and the second portion 202 is located at the peripheral edge area of ​​the package cover 20, so that the first portion 201 can be evenly dissipated with heat through the second portion 202 located around the first portion 201. Of course, the present application is not limited to this, and in other embodiments, the first portion 201 can also be located at the edge area of ​​the package cover 20, but it should be understood that the position of the first portion 201 corresponds to the position of the die 22, or in other words, the position of the first portion 201 is determined by the position of the die 22.

[0045] In some embodiments of the present application, Figure 3 As shown, the package cover 20 is surrounded by package retaining walls 203, which are used to be fixedly connected to the package substrate 21, so that the package cover 20 and the package substrate 21 form a closed space for accommodating the die 22. Of course, the present application is not limited to this. In other embodiments, the package cover 20 can also be a flat plate structure, and the space between it and the package substrate 21 can be sealed with a sealing glue to form a closed space for accommodating the die 22.

[0046] In some embodiments of the present application, Figure 3 and Figure 4 As shown, Figure 4 This is a schematic diagram of the bottom-up structure of a package cover in a chip package structure disclosed in an embodiment of the present application. The first portion 201 includes a first surface S1 and a second surface S2 arranged opposite to each other. The area of ​​the first surface S1 is greater than or equal to the area of ​​the bare die 22, and the first surface S1 is fixedly connected to the bare die 22. The second portion 202 includes a third surface S3 and a fourth surface S4 arranged opposite to each other. The second surface S2 and the fourth surface S4 are located in the same plane, and the distance D1 between the first surface S1 and the above plane is greater than the distance D2 between the third surface S3 and the above plane.

[0047] That is, the first portion 201 and the second portion 202 are coplanar on the side facing away from the die 22, while the first portion 201 and the second portion 202 have different heights on the side facing the die 22, such that the thickness of the first portion 201 is greater than the thickness of the second portion 202. It will be appreciated that the thickness of the package retaining wall 203 must be greater than or equal to the thickness of the first portion 201, for example, D3 must be greater than D1, so that the package retaining wall 203 and the package substrate 21 can enclose a closed space to accommodate the die 22.

[0048] Of course, the present application is not limited thereto. In other embodiments, such as Figure 5 As shown, Figure 5 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application. The first surface S1 and the third surface S3 are located in the same plane, and the distance D4 between the second surface S2 and the plane is greater than the distance D5 between the fourth surface S4 and the plane.

[0049] That is, the first portion 201 and the second portion 202 are coplanar on one side close to the die 22 , and have different heights on the other side away from the die 22 , so that the thickness of the first portion 201 is greater than that of the second portion 202 .

[0050] In some embodiments of the present application, Figure 3As shown, the first portion 201 further includes a fifth surface S5, the fifth surface S5 is located between the first surface S1 and the second surface S2, the fifth surface S5 includes a plane, and the angle α between the fifth surface S5 and the first surface S1 is an obtuse angle. Alternatively, as Figure 5 As shown, the included angle α between the fifth surface S5 and the first surface S1 is an acute angle.

[0051] Of course, the present application is not limited thereto. In other embodiments, such as Figure 6 As shown, Figure 6 FIG. 1 is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application. The angle α between the fifth surface S5 and the first surface S1 can also be a right angle. In other embodiments, such as Figure 7 As shown, Figure 7 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application. The fifth surface S5 is a curved surface, and the curved surface bulges in a direction away from the first portion 201 .

[0052] In some embodiments of the present application, Figure 8 and Figure 9 As shown, Figure 8 This is a bottom view of the package cover in another chip package structure disclosed in an embodiment of the present application. Figure 9 This is a schematic cross-sectional view of another chip package structure disclosed in an embodiment of the present application. A first portion 201 includes a first surface S1, which is used for fixed connection to a die 22. Alternatively, the first surface S1 is the surface fixedly connected to the die 22. The first surface S1 has a plurality of microgrooves 200, which are used to accommodate a connecting material 23 between the first surface S1 and the die 22.

[0053] Based on this, while the first portion 201 with a larger thickness is used to resist the warping of the die and the second portion 202 with a smaller thickness is used to reduce the weight of the package cover 20, by providing multiple micro grooves 200 on the first surface S1, not only can the contact area between the connecting material 23 and the first surface S1 and the die 22 be increased, but also the connecting material 23 can be prevented from excessive flow, thereby enhancing the connection effect between the die 22 and the package cover 20.

[0054] In some embodiments, as Figure 8 As shown, the micro grooves 200 are strip grooves, and a plurality of micro grooves 200 are arranged in parallel. Of course, the present application is not limited thereto. In other embodiments, the plurality of micro grooves 200 can also be square or circular grooves arranged in an array, etc., which will not be repeated here.

[0055] In some embodiments of the present application, Figure 9As shown, the die 22 is electrically connected to the package substrate 21 via solder balls 220, and the first portion 201 is fixedly connected to the die 22 via a connecting material 23. A filler 221 is provided between the die 22 and the package substrate 21 to protect the solder balls 220.

[0056] In addition, the bottom of the package substrate 21 also has a plurality of solder balls 210 electrically connected to a PCB (Printed Circuit Board), etc., and in some embodiments, the plurality of solder balls 210 are arranged in a grid-like pattern. Therefore, the package structure is also called a BGA (Ball Grid Array) package structure.

[0057] In some embodiments of the present application, package cover 20 comprises a metal cover, and connection material 23 comprises a metal solder material, wherein the metal solder material further comprises indium. In other embodiments, connection material 23 may also comprise silicone grease, etc., which will not be further described here. Based on this, the metal solder material with good thermal conductivity can establish a heat dissipation channel between die 22 and first portion 201, thereby effectively dissipating heat from die 22.

[0058] In some embodiments, the metal cover is made of copper or copper alloy to further suppress warping of the die 22. In addition, the surface of the metal cover can be nickel-plated or gold-plated to achieve good wetting of metal welding materials such as indium and achieve reliable welding results.

[0059] In some embodiments, as Figure 10 and Figure 11 As shown, Figure 10 This is a bottom view of the package cover in another chip package structure disclosed in an embodiment of the present application. Figure 11 This is a schematic cross-sectional view of another chip package structure disclosed in an embodiment of the present application. The side of the package retaining wall 203 facing the package substrate 21 has reinforcing ribs 205, also known as fins. These ribs 205 are fixedly connected to the package substrate 21 to prevent warping of the package substrate 21 due to its oversize. The package retaining wall 203 is fixedly connected to the package substrate 21 via adhesive 204, and the reinforcing ribs 205 are also fixedly connected to the package substrate 21 via adhesive 204.

[0060] In some embodiments, as Figure 10As shown, the reinforcing ribs 205 extend along the long sides of the package cover 20, and two reinforcing ribs 205 are located on either side of the first portion 201 to support the second portion 202, which has a smaller thickness, and prevent warping of the package substrate 21 due to its oversized size. Of course, the present application is not limited to this. In other embodiments, the reinforcing ribs 205 may also extend along the short sides or diagonals of the package cover 20, which will not be repeated here.

[0061] In some embodiments of the present application, Figure 12 and Figure 13 As shown, Figure 12 This is a schematic top view of another chip packaging structure disclosed in an embodiment of the present application. Figure 13 for Figure 12 The schematic cross-sectional view of the chip package structure along cutting line BB′ shows that the first portion 201 includes a microchannel 206, which is at least partially located within the first portion 201. The microchannel 206 is used to dissipate heat from the package cover 20 and the die 22 via a coolant flowing therein. The coolant can include a liquid such as water or alcohol, or a gas such as ammonia or sulfur dioxide. It should be noted that gases such as ammonia and sulfur dioxide are commonly used as refrigerants in refrigeration equipment such as air conditioners.

[0062] In the embodiment of the present application, the package cover 20 may include one microchannel 206 or multiple microchannels 206. The present embodiment and the accompanying drawings illustrate only one microchannel 206 as an example, and the present invention is not limited thereto. In some embodiments, multiple microchannels 206 may be arranged in parallel or in a cross-arrangement according to actual needs, which will not be further described here.

[0063] like Figure 13 As shown, microfluidic channel 206 is connected to the exterior of package cover 20 via inlet 210 and outlet 211. This allows components such as a motor and mechanical pump outside package cover 20 to inject coolant into microfluidic channel 206 through inlet 210. The coolant then flows through microfluidic channel 206, removing heat from package cover 20 and die 22, before exiting microfluidic channel 206 through outlet 211, dissipating heat from package cover 20 and die 22. Furthermore, due to the greater thickness of first portion 201, the microfluidic channel 206 within first portion 201 can have a larger channel diameter or a longer channel length, thereby improving the heat dissipation capability of microfluidic channel 206.

[0064] In some embodiments of the present application, the microchannels 206 are arranged in a preset pattern so that the microchannels 206 evenly cover the die 22, thereby achieving uniform heat dissipation for the die 22. Figure 14 As shown, Figure 14This is a schematic structural diagram of a microfluidic channel disclosed in an embodiment of the present application. The microfluidic channel 206 includes a plurality of first flow channels 212 and a plurality of second flow channels 213. The first flow channels 212 extend along a first direction Y, and the second flow channels 213 extend along a second direction X. The first direction Y intersects with the second direction X. In addition, the plurality of first flow channels 212 are arranged in sequence along the second direction X, and the second flow channel 212 is located between two adjacent first flow channels 212, so that the two adjacent first flow channels 212 are connected end to end to form a bow-shaped microfluidic channel.

[0065] Of course, the present application is not limited thereto, and in other embodiments, the plurality of first flow channels 212 and the plurality of second flow channels 213 form a U-shaped micro-channel. In other embodiments, the micro-channel 21 may also be a micro-channel of other shapes, which will not be described in detail here.

[0066] In some embodiments of the present application, Figure 15 and Figure 16 As shown, Figure 15 This is a schematic top view of another chip packaging structure disclosed in an embodiment of the present application. Figure 16 for Figure 15 The cross-sectional structure diagram of the chip package structure along the cutting line CC′ is shown. The second portion 202 has a vent hole 207. The vent hole 207 is used to connect the enclosed space where the bare chip 22 is located with the outside to remove volatile gases generated by the flux when the bare chip 22 is soldered to the package substrate 21.

[0067] In some embodiments, as Figure 17 As shown, Figure 17 This is a schematic cross-sectional view of another chip packaging structure disclosed in an embodiment of the present application. The packaging substrate 21 is further provided with a passive device 24. The passive device 24 includes a decoupling capacitor, which is used to reduce the noise impact of other devices in the circuit on the bare chip 22.

[0068] As another optional implementation of the present disclosure, an embodiment of the present disclosure discloses an electronic device including the chip packaging structure disclosed in any of the above embodiments. The electronic device may be a smartphone, a tablet computer, a digital camera, a server, or the like.

[0069] As another optional implementation of the disclosure of this application, the embodiment of this application discloses a design method for a chip packaging structure. The chip packaging structure can be the chip packaging structure disclosed in any of the above embodiments, such as Figure 18 As shown, Figure 18 This is a flow chart of a chip packaging structure design method disclosed in one embodiment of the present application. The design method includes:

[0070] S181: Obtain structural parameters of the package substrate and structural parameters of the bare chip;

[0071] In some embodiments of the present application, the package substrate and the bare die can be designed using package electrical design software running on a computer device. Based on this, the structural parameters of the package substrate and the structural parameters of the bare die can be obtained from the package electrical design software. That is, the structural parameters in the embodiments of the present application can be the structural parameters of the package substrate design and the structural parameters of the bare die design. Of course, the present invention is not limited to this. In other embodiments, the structural parameters of the package substrate and the bare die can be analyzed to obtain the structural parameters of the package substrate and the structural parameters of the bare die. Among them, the structural parameters of the package substrate include the structural parameters of the metal layer, the routing layer, and the solder balls in the package substrate, and the structural parameters of the bare die include the structural parameters of the bare die body and the solder balls.

[0072] S182: Determine multiple sets of structural parameters of the package cover according to the structural parameters of the package substrate and the structural parameters of the bare chip;

[0073] In embodiments of the present application, a computer running package structure design software can be used to design a package cover that matches the package substrate and the die based on the structural parameters of the package substrate and the die, and to determine multiple sets of structural parameters for the package cover. The structural parameters of the package cover include structural parameters of a first portion and a second portion. Furthermore, the structural parameters of the first portion and / or the second portion in each of the multiple sets of structural parameters are different.

[0074] S183: simulating the chip package structure according to the structural parameters of the package substrate, the structural parameters of the bare chip, and the multiple sets of structural parameters of the package cover to obtain multiple deformation values ​​of the chip package structure; the multiple deformation values ​​correspond to the multiple sets of structural parameters in a one-to-one manner;

[0075] In embodiments of the present application, packaging structure design software can be used to perform 3D modeling of the chip package structure based on the structural parameters of the package substrate, the structural parameters of the bare die, and multiple sets of structural parameters of the package cover. This results in multiple 3D models, each of which has a set of structural parameters for the package cover. The chip package structure is then simulated based on the multiple 3D models to obtain multiple deformation values ​​for the chip package structure. The multiple deformation values ​​correspond one-to-one to the multiple sets of structural parameters. These deformation values ​​can represent the amount of warpage of the chip package structure after thermal deformation.

[0076] S184: Determine the structural parameter corresponding to the smallest of the multiple deformation values ​​as the optimal structural parameter of the chip packaging structure.

[0077] In an embodiment of the present application, the optimal structural parameters of the first part and the second part can be determined based on the structural parameters corresponding to the smallest of multiple deformation values, so that the first part with a larger thickness, heavier weight and optimal structural parameters can be used to better resist the warping of the chip packaging structure, protect the bare chip from damage, and reduce the probability of failure of the chip packaging structure. The second part with a smaller thickness, lighter weight and optimal structural parameters can be used to minimize the weight of the entire packaging cover, reducing the risk of process problems such as solder joint collapse and bridging between solder joints due to the excessive weight of the packaging cover during the packaging process.

[0078] In some optional examples, the structural parameters include at least shape, material and size, and determining multiple sets of structural parameters of the package cover shell includes: combining multiple shapes, multiple materials and multiple sizes of the first part and the second part of the package cover shell to obtain multiple sets of structural parameters of the package cover shell.

[0079] like Figure 19 As shown, Figure 19 This is a schematic diagram of the structure of a package cover disclosed in an embodiment of the present application. Although the thickness of the first portion is greater than the thickness of the second portion in multiple sets of structural parameters for the package cover, the dimensions of parameters such as H, L, T1, T2, W, and D can vary across these multiple sets of structural parameters. The materials used for the package cover can also vary, and the shapes, such as cross-sectional shapes, of the first and / or second portions can also vary across these multiple sets of structural parameters. By adjusting the shapes, materials, and dimensions of the first and second portions as variable parameters, multiple combinations of shapes, materials, and dimensions can be obtained, allowing calculation of deformation values ​​for these different combinations.

[0080] In some embodiments, the range of T1 is 1mm to 3mm, the range of T2 is 2mm to 4mm, the range of L is 4mm to 5mm, the range of W is greater than or equal to 2mm, the range of D is 1mm to 2mm, and the range of H can be determined according to the thickness of the die, which will not be repeated here.

[0081] In some optional examples, the cross-sectional shape of the first portion includes a trapezoidal shape to alleviate the problem of stress concentration at the edge of the die, reduce the risk of die cracking, and improve its reliability. Of course, the present invention is not limited to this. In other embodiments, the cross-sectional shape of the first portion includes an arc shape, which will not be repeated here.

[0082] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application discloses a computer device, including a memory and a processor; the memory is used to store instructions; the processor is used to execute any of the above chip packaging structure design methods according to the instructions stored in the memory.

[0083] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application discloses a computer-readable storage medium on which instructions for executing any of the above chip packaging structure design methods are stored.

[0084] As another optional implementation of the contents disclosed in this application, an embodiment of the present invention further discloses a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the chip packaging structure design method disclosed in any of the above embodiments.

[0085] The computer program product may be written in any combination of one or more programming languages ​​to implement the program code for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0086] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The above embodiments merely represent several implementation methods of this specification. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of this specification, and these modifications and improvements fall within the scope of protection of this specification. Therefore, the scope of protection of the patent in this specification shall be based on the appended claims.

Claims

1. A method for designing a chip packaging structure, characterized in that: The chip packaging structure includes a packaging substrate, a bare die, and a packaging cover. The bare die is located on one side of the packaging substrate and is electrically connected to the packaging substrate. The packaging cover is located on a side of the bare die facing away from the packaging substrate, and the packaging cover and the packaging substrate form a closed space. The bare die is located in the closed space. The packaging cover includes a first portion and a second portion. The second portion is located around the first portion, and the thickness of the first portion is greater than that of the second portion. The bare die is fixed between the first portion and the packaging substrate. The design method includes: Acquiring structural parameters of the packaging substrate and structural parameters of the bare chip; Determining multiple sets of structural parameters of the package cover based on the structural parameters of the package substrate and the structural parameters of the bare die, wherein the structural parameters of the first portion and / or the second portion in the multiple sets of structural parameters are different; the first portion includes a first surface and a second surface disposed opposite to each other, the area of ​​the first surface is greater than or equal to the area of ​​the bare die, and the first surface is fixedly connected to the bare die; the second portion includes a third surface and a fourth surface disposed opposite to each other, the second surface and the fourth surface are located in the same plane, and the distance between the first surface and the plane is greater than the distance between the third surface and the plane; Simulating the chip packaging structure according to the structural parameters of the packaging substrate, the structural parameters of the bare chip, and multiple sets of structural parameters of the packaging cover to obtain multiple deformation values ​​of the chip packaging structure, where the multiple deformation values ​​correspond to the multiple sets of structural parameters in a one-to-one manner; The structural parameter corresponding to the smallest of the multiple deformation values ​​is determined as the optimal structural parameter of the chip packaging structure.

2. The design method according to claim 1, characterized in that: The structural parameters include at least shape, material and size, and determining the multiple sets of structural parameters of the package cover includes: Multiple shapes, multiple materials, and multiple sizes of the first part and the second part of the package cover are combined to obtain multiple groups of structural parameters of the package cover.

3. The design method according to claim 2, characterized in that: The cross-sectional shape of the first portion includes a trapezoid.

4. The design method according to claim 1, characterized in that: The first portion further includes a fifth surface, the fifth surface being located between the first surface and the second surface; The fifth surface includes a plane, and the angle between the fifth surface and the first surface is an acute angle or an obtuse angle; or, The fifth surface is a curved surface, and the curved surface is convex in a direction away from the first portion.

5. The design method according to claim 1, characterized in that: The first portion includes a first surface, the first surface being fixedly connected to the die; The first surface has a plurality of micro grooves, and the micro grooves are used to accommodate a connection material between the first surface and the die.

6. The design method according to claim 1, characterized in that: The first portion includes a microchannel, which is at least partially located inside the first portion. The microchannel is used to dissipate heat from the package cover and the die through a coolant flowing through the microchannel.

7. The design method according to claim 1, characterized in that: The package cover is surrounded by a package retaining wall; the package retaining wall is located between the package cover and the package substrate, so that the package cover and the package substrate form the closed space; The packaging retaining wall is fixedly connected to the packaging substrate, and a surface of the packaging retaining wall facing the packaging substrate is provided with reinforcing ribs or ribs.

8. A computer device, characterized in that: including memory and processor; The memory is used to store instructions; The processor is configured to execute the chip packaging structure design method according to any one of claims 1 to 7 according to the instructions stored in the memory.

9. A computer-readable storage medium, characterized in that Instructions for executing the chip packaging structure design method according to any one of claims 1 to 7 are stored thereon.

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