Equivalent verification method, device and equipment of multi-layer netlist framework and medium

Abstract

The application provides a multi-layer netlist framework equivalence verification method, device, equipment and medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: obtaining at least one chip pin in the chip layer of a target multi-layer netlist framework, the target multi-layer netlist framework comprising at least one dielectric layer; taking each chip pin as a starting point, taking other chip pins, dielectric pins of the dielectric layer and / or top layer transmission ports of the target multi-layer netlist framework as end points, determining the connection network corresponding to each chip pin through a pre-set connection relationship in the target multi-layer netlist framework; counting the number of top layer transmission ports, chip pins and dielectric pins corresponding to each connection network, and taking the connection network whose number meets the first condition as the first connection network; disconnecting the connection path corresponding to the dielectric pin from the first connection network to obtain the second connection network; and performing equivalence verification on the target multi-layer netlist framework based on the second connection network.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an equivalent verification method, apparatus, device, and medium for a multilayer netlist framework. Background Technology

[0002] For 2.5D / 3D multilayer integrated circuit design, there are generally two netlist frameworks for description: Framework A is a description method based on Register Transfer Level (RTL) circuits; Framework B is a description method based on physical implementation.

[0003] Currently, since frame A typically does not include black boxes and logic cones, while frame B typically does, this difference makes it impossible to effectively compare point matching of the netlists of the two frames, thus making it difficult to effectively verify the logical equivalence of frame A and frame B. Summary of the Invention

[0004] This invention provides an equivalent verification method, apparatus, device, and medium for multi-layer netlist frames, to solve the problem in the prior art that it is difficult to effectively verify the logical equivalence between frame A and frame B.

[0005] This invention provides an equivalent verification method for a multi-layer netlist framework, comprising:

[0006] In the chip layer of the target multi-layer netlist framework, at least one chip pin is obtained; wherein the target multi-layer netlist framework includes at least one dielectric layer;

[0007] Starting from each of the aforementioned chip pins, and ending at other chip pins not serving as starting points, the dielectric pins of the dielectric layer, and / or the top-level transmission port of the target multi-layer netlist framework, a connection network corresponding to each of the aforementioned chip pins is determined through pre-set connection relationships in the target multi-layer netlist framework; wherein, the connection network includes at least one connection path;

[0008] The number of top-level transmission ports, chip pins, and medium pins corresponding to each of the aforementioned connection networks is counted, and the connection network whose number satisfies the first condition is designated as the first connection network.

[0009] Disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network;

[0010] Based on the second connection network, the target multi-layer netlist framework is subjected to equivalent verification.

[0011] According to the equivalent verification method of a multi-layer netlist framework provided by the present invention, when the dielectric layer is an interposer, the number satisfies a first condition, including at least one of the following:

[0012] The number of top-level transmission ports is 0, the number of chip pins is 1, the number of ubump pins in the medium pins is 1, and the number of C4bump pins in the medium pins is 0.

[0013] The number of top-level transmission ports is 0, the number of chip pins is 2, the number of ubump pins in the medium pins is 2, and the number of C4bump pins in the medium pins is 0.

[0014] The number of top-level transmission ports is 1, the number of chip pins is k, the number of ubump pins in the medium pins is k, and the number of C4bump pins in the medium pins is 1, where k is an integer greater than 0.

[0015] According to the equivalent verification method of a multi-layer netlist framework provided by the present invention, after counting the number of top-level transmission ports, chip pins, and medium pins corresponding to each of the connected networks, the method further includes:

[0016] If there is a number of third connection networks in each of the aforementioned connection networks that satisfy the second condition, an alarm message is output; wherein the alarm message is used to indicate that the third connection network has an unreasonable design and the corresponding reason.

[0017] According to the equivalent verification method of a multi-layer netlist framework provided by the present invention, the number satisfying the second condition is set to the number not satisfying the first condition.

[0018] According to the present invention, an equivalent verification method for a multi-layer netlist framework is provided, wherein the equivalent verification of the target multi-layer netlist framework based on the second connection network includes:

[0019] Obtain the fourth connection network corresponding to the pre-set reference multi-layer netlist framework;

[0020] Based on the second connection network and the fourth connection network, verify whether the target multi-layer netlist framework and the reference multi-layer netlist framework are equivalent.

[0021] According to the present invention, an equivalence verification method for a multi-layer netlist framework, wherein verifying whether the target multi-layer netlist framework and the reference multi-layer netlist framework are equivalent based on the second connection network and the fourth connection network includes:

[0022] Compare point matching between the second connection network and the fourth connection network;

[0023] If the comparison point matches successfully, the target multi-layer netlist frame and the reference multi-layer netlist frame are determined to be equivalent.

[0024] The present invention also provides an equivalent verification device for a multi-layer netlist framework, comprising:

[0025] An acquisition module is used to acquire the chip pins of at least one chip in the chip layer of a target multi-layer netlist framework; wherein the target multi-layer netlist framework includes at least one dielectric layer;

[0026] The determination module is used to determine the connection network corresponding to each chip pin, starting from each chip pin and ending at other chip pins not used as starting points, the dielectric pins of the dielectric layer, and / or the top-level transmission port of the target multi-layer netlist framework, through the connection relationships pre-set in the target multi-layer netlist framework; wherein, the connection network includes at least one connection path;

[0027] The statistics module is used to count the number of top-level transmission ports, chip pins and medium pins corresponding to each of the connection networks, and to identify the connection networks whose counts meet a first condition as the first connection network.

[0028] The processing module is used to disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network;

[0029] The verification module is used to perform equivalent verification on the target multi-layer netlist framework based on the second connection network.

[0030] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement an equivalent verification method for any of the multi-layer netlist frameworks described above.

[0031] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements an equivalent verification method for a multi-layer netlist framework as described above.

[0032] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements an equivalent verification method for any of the multi-layer netlist frameworks described above.

[0033] The method, apparatus, device, and medium for equivalent verification of multi-layer netlist frameworks provided by this invention include a target multi-layer netlist framework comprising at least one medium layer, which can be understood as a framework B including a black box and a logic cone. Based on path analysis, this invention rewrites framework B, i.e., the target multi-layer netlist framework, to make the target multi-layer netlist framework equivalent to a framework excluding the black box and logic cone. Then, the equivalent framework is compared with the actual framework A excluding the black box and logic cone for equivalent verification, which can effectively verify the logical equivalence of the two and improve the accuracy of logical equivalence verification. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1 This is one of the flowcharts illustrating the equivalent verification method for the multi-layer netlist framework provided by this invention;

[0036] Figure 2 This is a structural diagram of framework A in the related technology;

[0037] Figure 3 This is a structural diagram of framework B in the related technology;

[0038] Figure 4 This is a cross-sectional schematic diagram of a multi-layer netlist framework in related technologies;

[0039] Figure 5 This is a schematic diagram of the marked disconnection position in the equivalent verification method of the multi-layer netlist framework provided by the present invention;

[0040] Figure 6 This is a schematic diagram of the modified second connection network in the equivalent verification method of the multi-layer netlist framework provided by the present invention;

[0041] Figure 7 This is a schematic diagram of an unreasonable design in the equivalent verification method of the multi-layer netlist framework provided by this invention;

[0042] Figure 8 This is the second schematic diagram of an unreasonable design in the equivalent verification method of the multi-layer netlist framework provided by this invention;

[0043] Figure 9 This is the third schematic diagram of an unreasonable design in the equivalent verification method of the multi-layer netlist framework provided by this invention;

[0044] Figure 10This is the fourth schematic diagram of an unreasonable design in the equivalent verification method of the multi-layer netlist framework provided by this invention;

[0045] Figure 11 This is the second flowchart illustrating the equivalent verification method for the multi-layer netlist framework provided by this invention.

[0046] Figure 12 This is a schematic diagram of the structure of the equivalent verification device for the multi-layer netlist framework provided by the present invention;

[0047] Figure 13 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0049] The equivalent verification method, apparatus, equipment, and medium of the multi-layer netlist framework of the present invention are described below with reference to the accompanying drawings.

[0050] Figure 1 This is one of the flowcharts illustrating the equivalent verification method for the multi-layer netlist framework provided by this invention, such as... Figure 1 As shown, the method includes steps 101 to 105; wherein:

[0051] Step 101: Obtain the chip pins of at least one chip in the chip layer of the target multi-layer netlist framework; wherein the target multi-layer netlist framework includes at least one dielectric layer;

[0052] Step 102: Starting from each chip pin, and ending at other chip pins not used as starting points, the dielectric pins of the dielectric layer, and / or the top-level transmission port of the target multi-layer netlist framework, determine the connection network corresponding to each chip pin through the pre-set connection relationships in the target multi-layer netlist framework; wherein, the connection network includes at least one connection path;

[0053] Step 103: Count the number of top-level transmission ports, chip pins and medium pins corresponding to each of the connection networks, and take the connection network whose number meets the first condition as the first connection network;

[0054] Step 104: Disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network;

[0055] Step 105: Based on the second connection network, perform equivalent verification on the target multi-layer netlist framework.

[0056] In related technologies, for 2.5D / 3D multilayer integrated circuit design, there are usually two netlist frameworks for description: Framework A is an RTL-based description method; Framework B is a physical implementation-based description method.

[0057] For example, Figure 2 This is a structural diagram of framework A in the related technology, such as... Figure 2 As shown, frame A includes a chip layer, which may include chip 1 and chip 2. The chips can be directly connected, for example, the c1 pin of chip 1 is connected to the c2 pin of chip 2 through net_c1c2. Chip 1 may also include an unconnected floating pin f1 forming net_f1. The pins of chip 1 and chip 2 can also be brought out to the top-level transmission port. For example, chip 1 is brought out to the top-level transmission port port_a1 through the a1 pin, and chip 2 is brought out to the top-level transmission port port_pg2 through the d2 pin and pg2 pin.

[0058] Figure 3 This is a structural diagram of framework B in the related technology, such as... Figure 3 As shown, in addition to the chip layer, frame B also includes a dielectric layer between the chip layer and the top-level transmission port. Taking the dielectric layer as an interposer as an example, for the connection between chips, chip 1 and chip 2 need to be connected through the interposer. Specifically, the c1 pin of chip 1, the c1_u pin of the interposer, the c2 pin of chip 2, and the c2_u pin of the interposer are connected to form net_c1c2. For the unconnected pin f1 of chip 1, it is connected to the f1_u pin of the interposer to form net_f1. For the pins brought out to the top-level transmission port, specifically the a1 pin of chip 1, the a1_u pin and the a1_c4 pin of the interposer, and the port_a1 port of the top layer are connected. The d2 pin and the pg2 pin of chip 2, the d2_u pin, the pg2_u pin and the pg2_c4 pin of the interposer, and the port_pg2 of the top layer are connected.

[0059] Figure 4 This is a cross-sectional schematic diagram of a multi-layer netlist framework in related technologies, such as... Figure 4 As shown, the chips in the chip layer are connected through a medium layer (interposer in the figure), or connected to the top-level transmission port through a medium layer.

[0060] According to the above Figure 2, Figure 3 and Figure 4 As can be seen, frame A typically does not include black boxes and logic cones (which can be understood as the dielectric layer), while frame B typically includes black boxes and logic cones. This difference makes it impossible to effectively compare point matching between the netlists of the two frames, making it difficult to effectively verify the logical equivalence between frame A and frame B. Verification failures are common, resulting in low accuracy in verifying logical equivalence.

[0061] To address the aforementioned issues, this invention proposes the following technical concept: rewriting the netlist of framework B based on path analysis, making it equivalent to a netlist excluding black boxes and logic cones, thereby enabling point matching with the netlist of framework A and effectively verifying the logical equivalence between framework A and framework B.

[0062] Specifically, rewriting the target multi-layer netlist framework, which includes at least one dielectric layer, can be understood as rewriting the framework B, which includes a black box and a logic cone.

[0063] First, obtain the chip pins of at least one chip in the target multi-layer netlist framework. In one embodiment, all chip pins of the chip in the chip layer can be obtained.

[0064] Iterate through the chip pins obtained in the previous step, and perform the following operation on each chip pin:

[0065] Using the chip pins obtained above as the starting point, and other chip pins not used as the starting point, the medium pins of the medium layer, and / or the top-level transmission port of the target multi-layer netlist framework as the ending point, the connection network corresponding to the chip pin is determined through the connection relationship set in the target multi-layer netlist framework. The connection network may include at least one connection path.

[0066] For example, connecting pin C1 of chip 1, pin C1_u of interposer, pin C2 of chip 2, and pin C2_u of interposer can form a net_c1c2 as a connection network, such as... Figure 3 As shown, the net_c1c2 connection network can include three connection paths. For example, in net_c1c2, the connection between the c1 pin and the c1_u pin of the interposer can be considered as one connection path.

[0067] After determining the connection network corresponding to each chip pin, the number of top-level transmission ports, chip pins, and media pins in each connection network is counted. For interposer, the media pins may include interposerubump pins and interposer C4bump pins. If the number of top-level transmission ports, chip pins, and media pins of a certain connection network meets the first condition, then the connection network can be considered a reasonable design, and thus the connection network can be used as the first connection network.

[0068] After obtaining the first connection network, disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network. After modifying all the first connection networks of the target multi-layer netlist framework into the second connection network, it can be understood that the target multi-layer netlist framework has been rewritten. Then, based on the modified second connection network, the target multi-layer netlist framework can be equivalently verified.

[0069] For example, with Figure 3 The multi-layer netlist framework shown is the target multi-layer netlist framework. Details of the first connection network in the target multi-layer netlist framework can be found in [link to relevant documentation]. Figure 3 .

[0070] When all connection networks in the target multi-layer netlist framework are of reasonable design, that is, when all connection networks in the target multi-layer netlist framework are first connection networks, disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network.

[0071] Optionally, the connection paths corresponding to the media pins that need to be disconnected can be marked with an "×" in the target multilayer netlist framework. Figure 5 This is a schematic diagram illustrating the marking of disconnection positions in the equivalent verification method for the multi-layer netlist framework provided by this invention, as shown below. Figure 5 As shown, each media pin of the interposer needs to be disconnected from its corresponding connection network.

[0072] Figure 6 This is a schematic diagram of the modified second connection network in the equivalent verification method of the multi-layer netlist framework provided by the present invention, as shown below. Figure 6 As shown, according to Figure 5 By disconnecting at the marked disconnect points, multiple second connection networks can be obtained.

[0073] It can be seen that, Figure 6 The modified target multilayer netlist framework, although still including a media layer, has different connection relationships than... Figure 3 The connection relationships corresponding to the multi-layer netlist framework are equivalent. Therefore, performing equivalence verification on the modified target multi-layer netlist framework can effectively verify logical equivalence and improve the accuracy of logical equivalence verification.

[0074] Optionally, the target multilayer netlist framework includes at least one dielectric layer, which can be an interposer or a fan-out wafer-level package (InFO).

[0075] In the equivalent verification method for a multi-layer netlist framework provided in this embodiment of the invention, the target multi-layer netlist framework, including at least one dielectric layer, can be understood as a framework B including a black box and a logic cone. Based on path analysis, this embodiment of the invention rewrites the framework B, i.e., the target multi-layer netlist framework, to make the target multi-layer netlist framework equivalent to a framework that does not include a black box and a logic cone. Then, the equivalent framework is compared with the actual framework A that does not include a black box and a logic cone for equivalent verification, which can effectively verify the logical equivalence of the two and improve the verification accuracy of logical equivalence.

[0076] Optionally, when the dielectric layer is an interposer, the number satisfying the first condition may include at least one of the following:

[0077] 1) The number of top-level transmission ports is 0, the number of chip pins is 1, the number of ubump pins in the medium pins is 1, and the number of C4bump pins in the medium pins is 0;

[0078] Specifically, the connection type corresponding to this situation is Interposer Floating, which means that the floating chip pins in the chip are connected to the corresponding ubump pins of the interposer. In this case, the connection network is considered to be a reasonable design.

[0079] 2) The number of top-level transmission ports is 0, the number of chip pins is 2, the number of ubump pins in the medium pins is 2, and the number of C4bump pins in the medium pins is 0;

[0080] Specifically, the connection type corresponding to this situation is Interconnect, that is, the chips are interconnected through interposer, and this connection network is considered to be a reasonable design.

[0081] 3) The number of top-level transmission ports is 1, the number of chip pins is k, the number of ubump pins in the medium pins is k, and the number of C4bump pins in the medium pins is 1, where k is an integer greater than 0.

[0082] Optionally, this application does not limit the material of the interposer; for example, it can be a silicon-based interposer or an organic material interposer.

[0083] It should be noted that, in addition to serving as an intermediate layer between the chip layer and the packaging substrate, the interposer also plays a role in redistributing signal lines.

[0084] Specifically, the connection type corresponding to this situation is C4Bump-out, which means that the chip pins in the chip are connected to the top-level transmission port through the interposer. In this case, the connection network is considered to be a reasonable design.

[0085] Optionally, Table 1 below shows the correspondence between the number of elements and the connection type in the interposer's connection network. Based on Table 1, it can be determined whether the number meets the first condition. Specifically, cases 1-3 in the table below are cases where the number meets the first condition.

[0086] Table 1 shows the correspondence between the number of elements and connection types in the interposer's connected network.

[0087]

[0088]

[0089] It should be noted that when the medium layer is InFO, the correspondence between the number of elements and the connection type in the corresponding connection network may differ from that in Table 1. Technicians can make specific designs based on the actual situation.

[0090] Optionally, after counting the number of top-level transmission ports, chip pins, and medium pins corresponding to each of the connection networks, an alarm message may be output if there is a third connection network in each of the connection networks whose number satisfies the second condition; wherein the alarm message is used to indicate that the third connection network has an unreasonable design and the corresponding reason.

[0091] Specifically, after counting the number of top-level transmission ports, chip pins, and media pins corresponding to each connection network, if there is a third connection network in each connection network whose number meets the second condition, then the third connection network is considered to have an unreasonable design. An alarm message can be output to indicate that the third connection network has an unreasonable design, and can also indicate the reason for the unreasonable design. Technicians can modify the third connection network based on the alarm message until the number of top-level transmission ports, chip pins, and media pins in the modified third connection network meets the first condition, that is, it has been modified into a reasonable design.

[0092] Optionally, the number satisfying the second condition is set to the number not satisfying the first condition.

[0093] This can be understood as follows: when the number of top-level transmission ports, chip pins, and media pins corresponding to each connection network does not meet the first condition, it is considered that the number of top-level transmission ports, chip pins, and media pins corresponding to each connection network meets the second condition.

[0094] Optionally, when the dielectric layer is an interposer, the number satisfying the second condition may include at least one of the following:

[0095] 1) The number of top-level transmission ports is 0, the number of chip pins is 2, the number of ubump pins in the medium pins is 0, and the number of C4bump pins in the medium pins is 0;

[0096] Specifically, Figure 7 This is a schematic diagram of one of the unreasonable designs in the equivalent verification method of the multi-layer netlist framework provided by this invention, such as... Figure 7 As shown, when the number of ports / pins for the four types is 0-2-0-0, the reason for the unreasonable design may be that the chips are not interconnected through an interposer, and the interconnection between chips must be through an interposer.

[0097] 2) The number of top-level transmission ports is 1, the number of chip pins is 1, the number of ubump pins in the medium pins is 0, and the number of C4bump pins in the medium pins is 0;

[0098] Specifically, Figure 8 This is the second schematic diagram of an unreasonable design in the equivalent verification method of the multi-layer netlist framework provided by this invention, such as... Figure 8 As shown, when the number of ports / pins for the four types is 1-1-0-0, the reason for the unreasonable design may be that the chip is not connected to the top-level transmission port through the interposer. If the chip pins are connected to the top-level transmission port, they must pass through the interposer and be brought out through C4bump (C4bump-out).

[0099] 3) The number of top-level transmission ports is 0, the number of chip pins is 2, the number of ubump pins in the medium pins is 1, and the number of C4bump pins in the medium pins is 0;

[0100] Specifically, Figure 9 This is the third schematic diagram of an unreasonable design in the equivalent verification method for the multi-layer netlist framework provided by this invention, such as... Figure 9As shown, when the number of ports / pins for the four types is 0-2-1-0, the reason for the unreasonable design may be that the chip pins do not correspond one-to-one with the interposer's ubump. The chip pins must correspond one-to-one with the interposer's ubump.

[0101] 4) The number of top-level transmission ports is 0, the number of chip pins is 1, the number of ubump pins in the medium pins is 0, and the number of C4bump pins in the medium pins is 0.

[0102] Specifically, Figure 10 This is the fourth schematic diagram of an unreasonable design in the equivalent verification method of the multi-layer netlist framework provided by this invention, such as... Figure 10 As shown, when the number of ports / pins for the four types is 0-1-0-0, the reason for the unreasonable design may be that the floating pins of the chip do not correspond to the ubump of the interposer. The floating pins of the chip should correspond to the ubump of the interposer.

[0103] Optionally, the implementation of equivalent verification of the target multi-layer netlist framework based on the second connection network may include:

[0104] Obtain the fourth connection network corresponding to the pre-set reference multi-layer netlist framework;

[0105] Based on the second connection network and the fourth connection network, verify whether the target multi-layer netlist framework and the reference multi-layer netlist framework are equivalent.

[0106] Specifically, the pre-set reference multi-layer netlist framework does not include black boxes and logic cones, and may specifically exclude the medium layer, that is, the reference multi-layer netlist framework can be used as framework A;

[0107] Obtain the fourth connection network in the reference multi-layer netlist framework. Based on the modified second and fourth connection networks, verify whether the target multi-layer netlist framework and the reference multi-layer netlist framework are equivalent.

[0108] Optionally, the implementation of verifying whether the target multi-layer netlist framework and the reference multi-layer netlist framework are equivalent based on the second connection network and the fourth connection network may include:

[0109] Compare point matching between the second connection network and the fourth connection network;

[0110] If the comparison point matches successfully, the target multi-layer netlist frame and the reference multi-layer netlist frame are determined to be equivalent.

[0111] Specifically, the equivalentity of the target multi-layer netlist frame and the reference multi-layer netlist frame can be verified by comparing point matching between the second and fourth connection networks. If the comparison point matching is successful, the target multi-layer netlist frame and the reference multi-layer netlist frame are determined to be equivalent; otherwise, the target multi-layer netlist frame and the reference multi-layer netlist frame are determined to be inequivalent.

[0112] The following example illustrates the equivalent verification method for the multi-layer netlist framework provided in this embodiment of the invention.

[0113] Figure 11 This is the second flowchart illustrating the equivalent verification method for the multi-layer netlist framework provided by this invention. Figure 11 As shown, the method includes S1 to S5; wherein:

[0114] S1. Read the reference multi-layer netlist frame (ref.v) and the target multi-layer netlist frame (impl.v). In the design of impl.v, find all chip pins.

[0115] S2. Traverse these chip pins and perform the following operation for each chip pin: starting from itself and ending at other chip pins, media pins, or top-level transmission ports, find connection paths to form a connection network.

[0116] S3. Perform path analysis for each net (analysis method as shown in Table 1). If it is determined to be an unreasonable design, modify it and return to S1; if it is determined to be a reasonable design, mark the media pins (interposer ubump and interposer C4bump) on the path to disconnect these media pins from their respective nets.

[0117] S4. Modify impl.v according to the markings to disconnect these media pins from their respective nets.

[0118] S5. Compare the modified impl.v and ref.v for point matching.

[0119] This invention provides an equivalent verification based on existing netlists. Logical equivalence verification fails when using the existing, unmodified impl.v and ref.v; however, by utilizing the multi-layer netlist framework equivalent verification method provided by this invention, and through path analysis and rewriting impl.v, comparison point matching and logical equivalence verification are successfully achieved.

[0120] The equivalent verification apparatus for the multi-layer netlist framework provided by the present invention will be described below. The equivalent verification apparatus for the multi-layer netlist framework described below can be referred to in correspondence with the equivalent verification method for the multi-layer netlist framework described above.

[0121] Figure 12 This is a schematic diagram of the structure of the equivalent verification device for the multi-layer netlist framework provided by the present invention, as shown below. Figure 12 As shown, the equivalent verification device 1200 for a multi-layer netlist framework includes:

[0122] The acquisition module 1201 is used to acquire the chip pins of at least one chip in the chip layer of the target multi-layer netlist framework; wherein the target multi-layer netlist framework includes at least one dielectric layer;

[0123] The determining module 1202 is used to determine the connection network corresponding to each chip pin, starting from each chip pin and ending at other chip pins not used as starting points, the dielectric pins of the dielectric layer, and / or the top-level transmission port of the target multi-layer netlist framework, through the connection relationships preset in the target multi-layer netlist framework; wherein, the connection network includes at least one connection path;

[0124] The statistics module 1203 is used to count the number of top-level transmission ports, chip pins and medium pins corresponding to each of the connection networks, and to take the connection network whose count meets the first condition as the first connection network.

[0125] Processing module 1204 is used to disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network;

[0126] The verification module 1205 is used to perform equivalent verification on the target multi-layer netlist framework based on the second connection network.

[0127] In the equivalent verification device for a multi-layer netlist framework provided in this embodiment of the invention, the target multi-layer netlist framework, including at least one dielectric layer, can be understood as a framework B including a black box and a logic cone. Based on path analysis, this embodiment of the invention rewrites the framework B, i.e., the target multi-layer netlist framework, to make the target multi-layer netlist framework equivalent to a framework that does not include a black box and a logic cone. Then, the equivalent framework is compared with the actual framework A that does not include a black box and a logic cone for equivalent verification, which can effectively verify the logical equivalence of the two and improve the verification accuracy of logical equivalence.

[0128] Optionally, when the dielectric layer is an interposer, the number satisfies the first condition, including at least one of the following:

[0129] 1) The number of top-level transmission ports is 0, the number of chip pins is 1, the number of ubump pins in the medium pins is 1, and the number of C4bump pins in the medium pins is 0;

[0130] 2) The number of top-level transmission ports is 0, the number of chip pins is 2, the number of ubump pins in the medium pins is 2, and the number of C4bump pins in the medium pins is 0;

[0131] 3) The number of top-level transmission ports is 1, the number of chip pins is k, the number of ubump pins in the medium pins is k, and the number of C4bump pins in the medium pins is 1, where k is an integer greater than 0.

[0132] Optionally, the equivalent verification device 1200 for the multi-layer netlist framework further includes:

[0133] The output module is used to output alarm information when there is a number of third connection networks in each of the connection networks that meet the second condition; wherein the alarm information is used to indicate that the third connection network has an unreasonable design and the corresponding reason.

[0134] Optionally, the number satisfying the second condition is set to the number not satisfying the first condition.

[0135] Optionally, the verification module 1205 is specifically used for:

[0136] Obtain the fourth connection network corresponding to the pre-set reference multi-layer netlist framework;

[0137] Based on the second connection network and the fourth connection network, verify whether the target multi-layer netlist framework and the reference multi-layer netlist framework are equivalent.

[0138] Optionally, the verification module 1205 is also specifically used for:

[0139] Compare point matching between the second connection network and the fourth connection network;

[0140] If the comparison point matches successfully, the target multi-layer netlist frame and the reference multi-layer netlist frame are determined to be equivalent.

[0141] Figure 13 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 13 As shown, the electronic device 1300 may include: a processor 1310, a communications interface 1320, a memory 1330, and a communication bus 1340, wherein the processor 1310, the communications interface 1320, and the memory 1330 communicate with each other through the communication bus 1340. The processor 1310 can call logical instructions in the memory 1330 to execute an equivalent verification method for a multi-layer netlist framework, the method including:

[0142] In the chip layer of the target multi-layer netlist framework, at least one chip pin is obtained; wherein the target multi-layer netlist framework includes at least one dielectric layer;

[0143] Starting from each of the aforementioned chip pins, and ending at other chip pins not serving as starting points, the dielectric pins of the dielectric layer, and / or the top-level transmission port of the target multi-layer netlist framework, a connection network corresponding to each of the aforementioned chip pins is determined through pre-set connection relationships within the target multi-layer netlist framework; wherein, the connection network includes at least one connection path;

[0144] The number of top-level transmission ports, chip pins, and medium pins corresponding to each of the aforementioned connection networks is counted, and the connection network whose number satisfies the first condition is designated as the first connection network.

[0145] Disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network;

[0146] Based on the second connection network, the target multi-layer netlist framework is subjected to equivalent verification.

[0147] Furthermore, the logical instructions in the aforementioned memory 1330 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0148] On the other hand, the present invention also provides a computer program product, the computer program product comprising a computer program that can be stored on a non-transitory computer-readable storage medium, wherein when the computer program is executed by a processor, the computer is capable of executing an equivalent verification method for the multi-layer netlist framework provided by the above methods, the method comprising:

[0149] In the chip layer of the target multi-layer netlist framework, at least one chip pin is obtained; wherein the target multi-layer netlist framework includes at least one dielectric layer;

[0150] Starting from each of the aforementioned chip pins, and ending at other chip pins not serving as starting points, the dielectric pins of the dielectric layer, and / or the top-level transmission port of the target multi-layer netlist framework, a connection network corresponding to each of the aforementioned chip pins is determined through pre-set connection relationships within the target multi-layer netlist framework; wherein, the connection network includes at least one connection path;

[0151] The number of top-level transmission ports, chip pins, and medium pins corresponding to each of the aforementioned connection networks is counted, and the connection network whose number satisfies the first condition is designated as the first connection network.

[0152] Disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network;

[0153] Based on the second connection network, the target multi-layer netlist framework is subjected to equivalent verification.

[0154] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements an equivalent verification method for the multi-layer netlist framework provided by the methods described above, the method comprising:

[0155] In the chip layer of the target multi-layer netlist framework, at least one chip pin is obtained; wherein the target multi-layer netlist framework includes at least one dielectric layer;

[0156] Starting from each of the aforementioned chip pins, and ending at other chip pins not serving as starting points, the dielectric pins of the dielectric layer, and / or the top-level transmission port of the target multi-layer netlist framework, a connection network corresponding to each of the aforementioned chip pins is determined through pre-set connection relationships within the target multi-layer netlist framework; wherein, the connection network includes at least one connection path;

[0157] The number of top-level transmission ports, chip pins, and medium pins corresponding to each of the aforementioned connection networks is counted, and the connection network whose number satisfies the first condition is designated as the first connection network.

[0158] Disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network;

[0159] Based on the second connection network, the target multi-layer netlist framework is subjected to equivalent verification.

[0160] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0161] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An equivalent verification method for a multi-layer netlist framework, characterized in that, include: In the chip layer of the target multi-layer netlist framework, at least one chip pin is obtained; wherein the target multi-layer netlist framework includes at least one dielectric layer; Starting from each of the aforementioned chip pins, and ending at other chip pins not serving as starting points, the dielectric pins of the dielectric layer, and / or the top-level transmission port of the target multi-layer netlist framework, a connection network corresponding to each of the aforementioned chip pins is determined through pre-set connection relationships within the target multi-layer netlist framework; wherein, the connection network includes at least one connection path; The number of top-level transmission ports, chip pins, and medium pins corresponding to each of the aforementioned connection networks is counted, and the connection network whose number satisfies the first condition is designated as the first connection network. Disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network; Based on the second connection network, the target multi-layer netlist framework is equivalently verified. When the dielectric layer is an interposer, the number satisfies the first condition, including at least one of the following: The number of top-level transmission ports is 0, the number of chip pins is 1, the number of ubump pins in the medium pins is 1, and the number of C4bump pins in the medium pins is 0. The number of top-level transmission ports is 0, the number of chip pins is 2, the number of ubump pins in the medium pins is 2, and the number of C4bump pins in the medium pins is 0. The number of top-level transmission ports is 1, the number of chip pins is k, the number of ubump pins in the medium pins is k, and the number of C4bump pins in the medium pins is 1, where k is an integer greater than 0.

2. The equivalent verification method for the multi-layer netlist framework according to claim 1, characterized in that, After counting the number of top-level transmission ports, chip pins, and medium pins corresponding to each of the aforementioned connection networks, the method further includes: If there is a number of third connection networks in each of the aforementioned connection networks that satisfy the second condition, an alarm message is output; wherein the alarm message is used to indicate that the third connection network has an unreasonable design and the corresponding reason.

3. The equivalent verification method for the multi-layer netlist framework according to claim 2, characterized in that, The number satisfying the second condition is set to the number not satisfying the first condition.

4. The equivalent verification method for the multi-layer netlist framework according to claim 1, characterized in that, The equivalent verification of the target multi-layer netlist framework based on the second connection network includes: Obtain the fourth connection network corresponding to the pre-set reference multi-layer netlist framework; Based on the second connection network and the fourth connection network, verify whether the target multi-layer netlist framework and the reference multi-layer netlist framework are equivalent.

5. The equivalent verification method for the multi-layer netlist framework according to claim 4, characterized in that, The step of verifying whether the target multi-layer netlist framework and the reference multi-layer netlist framework are equivalent based on the second connection network and the fourth connection network includes: Compare point matching between the second connection network and the fourth connection network; If the comparison point matches successfully, the target multi-layer netlist frame and the reference multi-layer netlist frame are determined to be equivalent.

6. An equivalent verification device for a multi-layer netlist framework, characterized in that, include: An acquisition module is used to acquire the chip pins of at least one chip in the chip layer of a target multi-layer netlist framework; wherein the target multi-layer netlist framework includes at least one dielectric layer; The determination module is used to determine the connection network corresponding to each chip pin, starting from each chip pin and ending at other chip pins not used as starting points, the dielectric pins of the dielectric layer, and / or the top-level transmission port of the target multi-layer netlist framework, through the connection relationships pre-set in the target multi-layer netlist framework; wherein, the connection network includes at least one connection path; The statistics module is used to count the number of top-level transmission ports, chip pins and medium pins corresponding to each of the connection networks, and to identify the connection networks whose counts meet a first condition as the first connection network. The processing module is used to disconnect the connection path corresponding to the medium pin from the first connection network to obtain the second connection network; The verification module is used to perform equivalent verification of the target multi-layer netlist framework based on the second connection network; When the dielectric layer is an interposer, the number satisfies the first condition, including at least one of the following: The number of top-level transmission ports is 0, the number of chip pins is 1, the number of ubump pins in the medium pins is 1, and the number of C4bump pins in the medium pins is 0. The number of top-level transmission ports is 0, the number of chip pins is 2, the number of ubump pins in the medium pins is 2, and the number of C4bump pins in the medium pins is 0. The number of top-level transmission ports is 1, the number of chip pins is k, the number of ubump pins in the medium pins is k, and the number of C4bump pins in the medium pins is 1, where k is an integer greater than 0.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements an equivalent verification method for the multi-layer netlist framework as described in any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements an equivalent verification method for the multi-layer netlist framework as described in any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements an equivalent verification method for the multi-layer netlist framework as described in any one of claims 1 to 5.

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