Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, and relate to the technical field of display, which are used to reduce the voltage drop of common voltage in transmission process and improve the brightness uniformity of the display panel. The display panel comprises a display area and a non-display area; the display area comprises: a plurality of sub-pixels, each of the sub-pixels comprising a pixel driving circuit and a light emitting element electrically connected; a common branch line electrically connected with the plurality of sub-pixels; and the common branch line and the pixel driving circuit are staggered with each other along the thickness direction of the display panel.

Description

[Technical Field]

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. [Background Technology]

[0002] With the continuous development of display technology, consumers' demands for displays are constantly increasing. Currently, various types of displays, including LCD screens and OLED screens, are emerging in large numbers and have developed rapidly. Based on this, display technologies such as 3D display, touch display technology, curved display, ultra-high resolution display, and privacy-protected display are constantly emerging.

[0003] However, current display panels suffer from poor brightness uniformity. 。 [Summary of the Invention]

[0004] In view of this, embodiments of the present invention provide a display panel and a display device to reduce the voltage drop of the common voltage during transmission and improve the brightness uniformity of the display panel.

[0005] On one hand, embodiments of the present invention provide a display panel, including: a display area and a non-display area;

[0006] The display area includes:

[0007] Multiple sub-pixels, each sub-pixel including an electrically connected pixel driving circuit and a light-emitting element;

[0008] A common branch line, electrically connected to multiple sub-pixels;

[0009] Along the thickness direction of the display panel, the common branch line and the pixel driving circuit are staggered.

[0010] On the other hand, embodiments of the present invention provide a display device including the display panel described above.

[0011] The display panel and display device provided in this embodiment of the invention can reduce the voltage drop of the common voltage during transmission by setting a common branch line in the display area of ​​the display panel and electrically connecting the common branch line to multiple sub-pixels, thereby improving the brightness uniformity of multiple sub-pixels located at different positions in the display area and thus enhancing the display uniformity of the display panel.

[0012] Furthermore, along the thickness direction of the display panel, by staggering the common branch line and the pixel driving circuit, the embodiments of the present invention can avoid mutual interference between the common voltage transmitted by the common branch line and the signals transmitted by other structures in the pixel driving circuit that transmit different signals, thereby reducing the coupling capacitance between the common branch line and the pixel driving circuit and improving the accuracy of the signal. [Attached Image Description]

[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 A top view schematic diagram of a display panel provided in an embodiment of the present invention;

[0015] Figure 2 An equivalent circuit diagram of a sub-pixel is provided for an embodiment of the present invention;

[0016] Figure 3 for Figure 2 A wiring diagram of a pixel driving circuit is shown.

[0017] Figure 4 A cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention;

[0018] Figure 5 A top view schematic diagram of another display panel provided in an embodiment of the present invention;

[0019] Figure 6 This is a partially enlarged schematic diagram of the display area of ​​a display panel provided in an embodiment of the present invention;

[0020] Figure 7 for Figure 6 A top view of a semiconductor layer in a semiconductor structure;

[0021] Figure 8 for Figure 6 A top view of the first metal layer in the process;

[0022] Figure 9 for Figure 6 A top view of the second metal layer in the process;

[0023] Figure 10 for Figure 6 A top view of the third metal layer in the process;

[0024] Figure 11 for Figure 6 A top view of the fourth metal layer in the process;

[0025] Figure 12 for Figure 6 A top view of the fifth metal layer in the process;

[0026] Figure 13 for Figure 6 A schematic diagram of a cross-section along BB';

[0027] Figure 14 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention;

[0028] Figure 15 for Figure 14 A top view of the fourth metal layer in the process;

[0029] Figure 16 for Figure 14 A top view of the fifth metal layer in the middle;

[0030] Figure 17 for Figure 14 A schematic diagram of a cross section along CC';

[0031] Figure 18 A top view schematic diagram of another display panel provided in an embodiment of the present invention;

[0032] Figure 19 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention;

[0033] Figure 20 for Figure 19 A top view of a semiconductor layer in a semiconductor structure;

[0034] Figure 21 for Figure 19 A top view of the second metal layer in the process;

[0035] Figure 22 for Figure 19 A top view of the fourth metal layer in the middle;

[0036] Figure 23 for Figure 19 A top view of the third metal layer in the process;

[0037] Figure 24 for Figure 19 A schematic diagram of a cross-section along DD';

[0038] Figure 25 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention;

[0039] Figure 26 for Figure 25 A schematic diagram of a cross-section along EE';

[0040] Figure 27 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention;

[0041] Figure 28 for Figure 27A top view of a semiconductor layer in a semiconductor structure;

[0042] Figure 29 for Figure 27 A top view of the fourth metal layer in the process;

[0043] Figure 30 A partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention;

[0044] Figure 31 for Figure 30 A top view of the fourth metal layer in the process;

[0045] Figure 32 A schematic diagram of yet another display panel provided in an embodiment of the present invention;

[0046] Figure 33 A top view schematic diagram of another display panel provided in an embodiment of the present invention;

[0047] Figure 34 A top view schematic diagram of another display panel provided in an embodiment of the present invention;

[0048] Figure 35 A top view schematic diagram of another display panel provided in an embodiment of the present invention;

[0049] Figure 36 for Figure 35 An enlarged schematic diagram of the middle region R;

[0050] Figure 37 A cross-sectional schematic diagram of another display panel provided in an embodiment of the present invention;

[0051] Figure 38 A schematic diagram of yet another display panel provided in an embodiment of the present invention;

[0052] Figure 39 A schematic diagram of yet another display panel provided in an embodiment of the present invention;

[0053] Figure 40 for Figure 38 An enlarged schematic diagram of region Q in the middle region

[0054] Figure 41 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0055] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0056] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0057] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0058] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0059] This invention provides a display panel, such as... Figure 1 As shown, Figure 1 This is a top view schematic diagram of a display panel provided in an embodiment of the present invention. The display panel 100 includes a display area AA and a non-display area NA, such as... Figure 1 As shown, the display area AA includes sub-pixels 1 and a common branch line 2, which is used to transmit a common voltage. The common branch line 2 is electrically connected to multiple sub-pixels 1 located at different positions within the display area AA to provide a common voltage to the multiple sub-pixels 1 located at different positions. In this embodiment of the invention, the multiple sub-pixels 1 located at different positions within the display area AA require the same common voltage to operate. Sub-pixels 1 need to receive multiple voltages during operation. Some of these voltages may be a common voltage shared by multiple sub-pixels 1.

[0060] The following combination Figure 2 The circuit diagram of sub-pixel 1 shown illustrates the common voltage required for sub-pixel 1 to operate. Figure 2 An equivalent circuit diagram of a sub-pixel is provided in an embodiment of the present invention. The sub-pixel 1 includes a pixel driving circuit 10 and a light-emitting element 11 electrically connected. The pixel driving circuit 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C. The signals required for the operation of the sub-pixel 1 include a first scan signal S1, a second scan signal S2, a light-emitting control signal E, a data voltage Data, a first power supply voltage PVEE, a second power supply voltage PVDD, and a reference voltage Vref.

[0061] Specifically, the first transistor T1 provides the second power supply voltage PVDD to the second node N2 under the control of the light emission control signal E; the second transistor T2 provides the data voltage Data to the second node N2 under the control of the second scan signal S2; the third transistor T3 electrically connects the second node N2 and the third node N3 under the control of the first node N1; the fourth transistor T4 electrically connects the third node N3 and the first node N1 under the control of the second scan signal S2; the fifth transistor T5 provides the reference voltage Vref to the first node N1 under the control of the first scan signal S1; the sixth transistor T6 electrically connects the third node N3 and the fourth node N4 under the control of the light emission control signal E; and the seventh transistor T7 provides the reference voltage Vref to the fourth node N4 under the control of the second scan signal S2. The first electrode of the light-emitting element 11 receives the first power supply voltage PVEE, and the second electrode is electrically connected to the fourth node N4. The first plate of the storage capacitor C receives the second power supply voltage PVDD, and the second plate is electrically connected to the first node N1.

[0062] The pixel driving circuit 10 operates in three phases: a reset phase, a charging phase, and a light-emitting phase. During the reset phase, the fifth transistor T5 is turned on in response to the first scan signal S1, and the reference voltage Vref resets the first node N1 through the fifth transistor T5. During the charging phase, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on in response to the second scan signal S2, and the data voltage Data is written to the second node N2 through the second transistor T2. In this phase, the third transistor T3 is turned on. The potential of the first node N1 continuously changes until the potential Vref of the first node N1 reaches a certain value. N1 Change to V N1 =Data - |Vth|, where Vth is the threshold voltage of the third transistor T3. The reference voltage Vref resets the fourth node N4 through the seventh transistor T7. During the light-emitting phase, the first transistor T1, the sixth transistor T6, and the third transistor T3 are turned on, and the current path between the second power supply voltage PVDD and the first power supply voltage PVEE is opened, thus lighting up the light-emitting element 11.

[0063] based on Figure 2The circuit configuration of the sub-pixel 1 shown in this embodiment of the invention allows the first power supply voltage PVEE required for the operation of multiple sub-pixels 1 located at different positions in the display area AA to be the same, and / or the reference voltage Vref required for the operation of multiple sub-pixels 1 located at different positions in the display area AA to be the same. That is, in this embodiment of the invention, the common voltage includes the aforementioned first power supply voltage PVEE and / or reference voltage Vref. The data voltage Data, the first scan signal S1, the second scan signal S2, and the light emission control signal E are non-common voltages. For example, this embodiment of the invention allows the first power supply voltage PVEE required for the operation of all sub-pixels 1 within the display area AA to be the same, and / or the reference voltage Vref required for the operation of all sub-pixels 1 within the display area AA to be the same.

[0064] Optional, combined Figure 2 and Figure 3 As shown, Figure 3 for Figure 2 The diagram shows a wiring schematic of a pixel driving circuit. The display area also includes a first scan line 31 for transmitting the first scan signal S1, a second scan line 32 for transmitting the second scan signal S2, a light emission control signal line 33 for transmitting the light emission control signal E, a data line 34 for transmitting the data voltage Data, and a second power supply line 35 for transmitting the second power supply voltage PVDD.

[0065] For example, in combination Figure 3 and Figure 4 As shown, Figure 4 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes a substrate 41 and an array film layer 42 and a display film layer 43 formed on the same side of the substrate 41. The display film layer 43 is located on the side of the array film layer 42 away from the substrate 41. The pixel driving circuit 10, the first scan line, the second scan line, the light emission control signal line, the data line, and the second power supply line are all located in the array film layer 42. For example, as shown... Figure 4 As shown, common branch 2 is also located in array film layer 42.

[0066] Optional, such as Figure 4As shown, the array film layer 42 includes a first insulating layer IS1, a semiconductor layer S, a second insulating layer IS2, a first metal layer M1, a third insulating layer IS3, a second metal layer M2, a fourth insulating layer IS4, a third metal layer M3, a fifth insulating layer IS5, a fourth metal layer M4, a sixth insulating layer IS6, a fifth metal layer M5, and a passivation layer PV, which are sequentially formed on one side of the substrate 41. The pixel driving circuit 10, the first scan line, the second scan line, the light emission control signal line, the data line, the second power line, and the common branch line 2 can be respectively set in the corresponding conductive layers in the array film layer 42 according to different design requirements. The specific wiring in the array film layer 42 will be introduced later, and will not be repeated here.

[0067] like Figure 4 As shown, the display film layer 43 includes a pixel definition layer 431 and a light-emitting element 11. The light-emitting element 11 includes a first electrode 111, a light-emitting layer 110, and a second electrode 112. The second electrode 112 is electrically connected to the pixel driving circuit 10. Optionally, as... Figure 4 As shown, the pixel driving circuit 10 is electrically connected to the second electrode 112 via a connection electrode 12. The connection electrode 12 includes a first sub-connection electrode 121, a second sub-connection electrode 122, and a third sub-connection electrode 123 stacked together. The pixel defining layer 431 includes an opening 4310 that exposes at least a portion of the second electrode 112. At least a portion of the light-emitting layer 110 is located within the opening 4310. Figure 4 As shown, a planarization layer PLN is also included between the second electrode 112 and the passivation layer PV. It should be noted that, for the sake of simplicity in the illustration, [the following text is incomplete and requires further context]. Figure 4 Only the sixth transistor T6, which is electrically connected to the light-emitting element 11, is shown in the pixel driving circuit 10. The other thin-film transistors in the pixel driving circuit 10 are shown in... Figure 3 Not shown in the image.

[0068] In this embodiment of the invention, along the thickness direction h3 of the display panel, the common branch 2 is offset from the pixel driving circuit 10. It should be noted that, in this embodiment of the invention, the region where the pixel driving circuit 10 is located is the region where each thin-film transistor and storage capacitor C is located within the pixel driving circuit 10. Figure 2 Taking the pixel driving circuit 10 with a 7T1C structure having seven thin-film transistors and one storage capacitor as an example, combined with... Figure 3 As shown, the region PA where the pixel driving circuit 10 is located is Figure 3 The area enclosed by the dashed box. The common branch 2 is offset from the pixel driving circuit 10, that is, the common branch 2 is offset from each thin-film transistor in the pixel driving circuit 10, and also offset from the storage capacitor C in the pixel driving circuit 10.

[0069] In this embodiment of the invention, by setting a common branch line 2 in the display area AA of the display panel, and electrically connecting the common branch line 2 to multiple sub-pixels 1, the voltage drop of the common voltage during transmission can be reduced, the brightness consistency of multiple sub-pixels 1 located at different positions in the display area AA can be improved, thereby enhancing the display uniformity of the display panel.

[0070] Furthermore, along the thickness direction h3 of the display panel, by staggering the common branch 2 and the pixel driving circuit 10, the common voltage transmitted by the common branch 2 can avoid mutual interference between the common voltage transmitted by the common branch 2 and other structures in the pixel driving circuit 10 that transmit different signals, thereby reducing the coupling capacitance between the common branch 2 and the pixel driving circuit 10 and improving the accuracy of the signal.

[0071] It should be understood that Figure 2 The equivalent circuit diagram of sub-pixel 1 shown, and Figure 3 The wiring diagrams of the pixel driving circuit 10 shown are all schematic diagrams. In this embodiment of the invention, the equivalent circuit diagram of the sub-pixel 1 and the wiring of the pixel driving circuit 10 can be designed in other ways according to different needs. This embodiment of the invention does not limit this.

[0072] For example, in an embodiment of the invention, the common branch 2 includes a first power line and / or a reference voltage line. Optionally, as... Figure 5 As shown, Figure 5 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. The display area AA includes a first electrode 111 and a common branch line 2. The first electrode 111 is used to transmit the aforementioned first power supply voltage PVEE. For example, as shown... Figure 5 As shown, in this embodiment of the invention, the first electrode 111 can be configured as a planar structure covering the display area AA, with different light-emitting elements ( Figure 5 The first electrodes 111 (not shown) can be electrically connected to each other.

[0073] like Figure 5 As shown, the common branch 2 includes a first power line 21. The first power line 21 is electrically connected to the light-emitting element in the sub-pixel to provide the light-emitting element with the aforementioned first power supply voltage PVEE. Figure 5 As shown, the non-display area NA includes a first power bus 51. Exemplarily, in this embodiment of the invention, both the first power line 21 and the first electrode 111 can be electrically connected to the first power bus 51 in the non-display area NA.

[0074] If the load on the first power bus 51 is large, it will generate significant heat during display panel operation. In particular, overheating will occur in narrower areas of the first power bus 51, leading to a higher risk of burn-in. This embodiment of the invention addresses this by incorporating a first power line 21 within the display area AA in the array film layer 42. This reduces the voltage drop of the first power supply voltage PVEE during transmission, thereby compressing the width of the first power bus 51 without increasing its load. This achieves a narrow bezel design for the display panel while reducing the risk of burn-in and improving the reliability of the display panel. Furthermore, by integrating the first power line 21 into the array film layer 42, this embodiment integrates it into the manufacturing process of other existing structures within the array film layer 42, avoiding increased manufacturing complexity for the display panel.

[0075] Optional, such as Figure 5 As shown, the first power line 21 includes a first sub-power line 2101 and / or a second sub-power line 2102, the first sub-power line 2101 extending along a first direction h1, and the second sub-power line 2102 extending along a second direction h2. (Combined with...) Figure 5 and Figure 6 As shown, Figure 6 This is a partially enlarged schematic diagram of the display area of ​​a display panel provided in an embodiment of the present invention. It illustrates two rows of pixel driving circuits arranged along the second direction h2, with each row including seven pixel driving circuits arranged along the first direction h1. Each pixel driving circuit can be configured according to... Figure 3 Configure it as shown in the diagram. Figure 6 In the first power line 21, there are first sub-power lines 2101 and second sub-power lines 2102 that are electrically connected, so as to further increase the conduction path of the first power supply voltage PVEE in the array film layer, reduce the voltage drop of the first power supply voltage PVEE during transmission, avoid the situation of excessive load on the first power bus 51, and help to further reduce the width of the first power bus 51, so as to realize the narrow bezel design of the display panel.

[0076] For example, such as Figure 6 As shown, a portion of the first sub-power line 2101 is located between two adjacent pixel driving circuits 10 in the second direction h2, and a portion of the second sub-power line 2102 is located between two adjacent pixel driving circuits 10 in the first direction h1. Both the first sub-power line 2101 and the second sub-power line 2102 are offset from the pixel driving circuits 10.

[0077] Optional, such as Figure 5 and Figure 6As shown, in this embodiment of the invention, a second sub-power line 2102 can be electrically connected to at least two first sub-power lines 2101, and / or a first sub-power line 2101 can be electrically connected to at least two second sub-power lines 2102. That is, within the display area AA, the first power line 21 is wired in a grid pattern in the array film layer to further increase the conduction path of the first power supply voltage PVEE and reduce the voltage drop of the first power supply voltage PVEE during propagation.

[0078] Combination Figure 4 , Figure 6 and Figure 7 As shown, Figure 7 for Figure 6 This is a top view schematic diagram of a semiconductor layer S, which includes the active layer of a thin-film transistor. The active layer includes the channel region, source region, and drain region of each thin-film transistor. Optionally, such as... Figure 7 As shown, the semiconductor layer S includes a first channel region S10, a first doped region S11 and a second doped region S12 located on both sides of the first channel region S10, a second channel region S20, a third doped region S21 and a fourth doped region S22 located on both sides of the second channel region S20, a third channel region S30, a fifth doped region S31 and a sixth doped region S32 located on both sides of the third channel region S30, a fourth channel region S40, a seventh doped region S41 and an eighth doped region S42 located on both sides of the fourth channel region S40, a fifth channel region S50, a ninth doped region S51 and a tenth doped region S52 located on both sides of the fifth channel region S50, a sixth channel region S60, an eleventh doped region S61 and a twelfth doped region S62 located on both sides of the sixth channel region S60, a seventh channel region S70, and a thirteenth doped region S71 and a fourteenth doped region S72 located on both sides of the seventh channel region S70. One of the two doped regions located on either side of each channel region is the source region, and the other is the drain region. Both the source and drain regions are doped with impurities. These impurities include P-type or N-type impurities. For example, the semiconductor layer S includes any one or more of low-temperature polycrystalline silicon, amorphous silicon, and oxide semiconductor layers.

[0079] Combination Figure 6 and Figure 8 As shown, Figure 8 for Figure 6 A top view schematic diagram of the first metal layer M1, which includes the aforementioned light-emitting control signal line 33, the first electrode C1 of the storage capacitor C, the gate G2 of the second transistor T2, the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, and the gate G7 of the seventh transistor T7. The gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4 are connected.

[0080] Combination Figure 6 , Figure 7and Figure 8 As shown, along the thickness direction h3 of the display panel, the gate G2 of the second transistor T2 overlaps with the second channel region S20. The gate G4 of the fourth transistor T4 overlaps with the fourth channel region S40. The gate G5 of the fifth transistor T5 overlaps with the fifth channel region S50. The gate G7 of the seventh transistor T7 overlaps with the seventh channel region S70. The portions of the light-emitting control signal line 33 that overlap with the first channel region S10 and the sixth channel region S60 respectively form the gate G1 of the first transistor T1 and the gate G6 of the sixth transistor T6. The portion of the first plate C1 of the storage capacitor C that overlaps with the third channel region S30 forms the gate G3 of the third transistor T3.

[0081] Combination Figure 6 and Figure 9 As shown, Figure 9 for Figure 6 A top view schematic diagram of the second metal layer M2, which includes a reference voltage line 22 and a second electrode C2 of a storage capacitor C. Exemplarily, the second electrode C2 of the storage capacitor C of different pixel driving circuits is electrically connected.

[0082] Combining 6 and Figure 10 As shown, Figure 10 for Figure 6 A top view of the third metal layer M3 is shown. The third metal layer M3 includes a first scan line 31, a second scan line 32, and a second power line 35 extending along a first direction h1. The second power line 35 is used to transmit the aforementioned second power supply voltage PVDD.

[0083] Combination Figure 6 and Figure 11 As shown, Figure 11 for Figure 6 A top view of the fourth metal layer M4 is shown. The fourth metal layer M4 includes a data line 34 and a second power line 35 extending along a second direction h2. The second power line 35 is used to transmit the aforementioned second power supply voltage PVDD. The second power supply voltage line 35 extending along the second direction h2 is electrically connected to a second power supply voltage line 35 located in the third metal layer M3 that extends along a first direction h1.

[0084] For example, in embodiments of the present invention, the first sub-power line 2101 and the second sub-power line 2102 can be arranged on different layers. For example... Figure 6 , Figure 11 and Figure 12 As shown, Figure 12 for Figure 6A top view of the fifth metal layer in the present invention embodiment allows the first sub-power line 2101 to be located in the fifth metal layer M5, and the second sub-power line 2102 to be located in the fourth metal layer M4, that is, the second sub-power line 2102 is arranged in the same layer as the data line 34 and the second power line 35 extending along the second direction h2.

[0085] For example, in combination Figure 6 and Figure 13 As shown, Figure 13 for Figure 6 A cross-sectional schematic diagram along BB' shows that the first sub-power line 2101 and the second sub-power line 2102 are electrically connected through a connection hole K21 that penetrates the sixth insulating layer IS6.

[0086] Optional, combined Figure 3 and Figure 10 As shown, the third metal layer M3 also includes a first connection portion X1. The first connection portion X1 is electrically connected to a second power supply voltage line 35 extending along the first direction h1, and one end of the first connection portion X1 is electrically connected to the second electrode C2 of the capacitor C located in the second metal layer M2 through a first via H11 penetrating the third insulating layer (not shown). The other end of the first connection portion X1 is electrically connected to the first doped region S11 located in the semiconductor layer S through a second via H12 to transmit the second power supply voltage PVDD to the source or drain of the first transistor T1. The second via H12 penetrates the fourth insulating layer (not shown), the third insulating layer (not shown), and the second insulating layer (not shown).

[0087] Combination Figure 3 and Figure 10 As shown, the third metal layer M3 also includes a second connection portion X2. One end of the second connection portion X2 is electrically connected to the data line 34 located in the fourth metal layer M4 through a third via H21 penetrating the fifth insulating layer (not shown). The other end of the second connection portion X2 is electrically connected to the third doped region S21 in the semiconductor layer S through a fourth via H22 penetrating the fourth insulating layer (not shown), the third insulating layer (not shown), and the second insulating layer (not shown) to transmit data voltage to the source or drain of the second transistor T2.

[0088] Combination Figure 3 and Figure 10As shown, the third metal layer M3 also includes a third connection portion X3. One end of the third connection portion X3 is electrically connected to the seventh doped region S41 and the tenth doped region S52 located in the semiconductor layer S through a fifth via H31 that penetrates the fourth insulating layer (not shown), the third insulating layer (not shown), and the second insulating layer (not shown). The other end of the third connection portion X3 is electrically connected to the first electrode C1 of the capacitor C located in the first metal layer M1 through a sixth via H32 that penetrates the fourth insulating layer, the second metal layer, and the third insulating layer. The portion of the first electrode C1 that overlaps with the third channel region S30 is multiplexed as the gate G3 of the third transistor T3.

[0089] Combination Figure 9 As shown, the second plate C2 of the capacitor C located in the second metal layer M2 includes an opening O. Along the thickness direction h3 of the display panel, the sixth via H32 and the opening O overlap.

[0090] For example, the area of ​​opening O is greater than or equal to the area of ​​the sixth through hole H32. Figure 9 The diagram illustrates the case where the area of ​​opening O is larger than the area of ​​the sixth via H32. The orthographic projection of the sixth via H32 onto the plane of the substrate lies within opening O.

[0091] like Figure 3 As shown, the second power supply voltage line 35 extending along the first direction h1 in the third metal layer M3 is electrically connected to the second power supply voltage line 35 extending along the second direction h2 in the fourth metal layer M4 through the seventh via H4. The seventh via H4 penetrates the fifth insulating layer (not shown).

[0092] Alternatively, in embodiments of the present invention, the first sub-power line 2101 and the second sub-power line 2102 may be arranged on the same layer. For example, as shown... Figure 14 , Figure 15 , Figure 16 and Figure 17 As shown, Figure 14 This is a partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention. Figure 15 for Figure 14 A top view of the fourth metal layer in the structure. Figure 16 for Figure 14 A top view of the fifth metal layer. Figure 17 for Figure 14 A cross-sectional view along CC' shows that, in this embodiment of the invention, both the first sub-power line 2101 and the second sub-power line 2102 are located in the fifth metal layer M5. With this configuration, when manufacturing the display panel, the same material can be used to simultaneously fabricate the first sub-power line 2101 and the second sub-power line 2102 in the same process flow, thereby improving process efficiency.

[0093] For example, Figure 14 The arrangement of the semiconductor layer, the first metal layer, the second metal layer, and the third metal layer can be referred to respectively. Figure 7 , Figure 8 , Figure 9 and Figure 10 The settings will be explained in detail here.

[0094] It should be noted that, Figure 3 , Figure 6 and Figure 14 The arrangement of the first scan line 31, the second scan line 32, and the light emission control signal line 33 shown is merely an illustration. Embodiments of the present invention can adjust the film positions or structures of the first scan line 31, the second scan line 32, and the light emission control signal line 33 according to different design requirements; the present invention does not limit this. For example, besides… Figure 3 , Figure 6 and Figure 14 In addition to setting the first scan line 31, the second scan line 32, and the light emission control signal line 33 as a single-layer structure, embodiments of the present invention may also set at least one of the first scan line 31, the second scan line 32, and the light emission control signal line 33 as a double-layer or multi-layer structure including at least two metal layers, in order to reduce the resistance of the corresponding signal line.

[0095] For example, such as Figure 18 As shown, Figure 18 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. The display area AA includes a common branch line 2, the common branch line 2 includes a reference voltage line 22, and the reference voltage line 22 leads to the pixel driving circuit ( Figure 18 (Not shown) provides the aforementioned reference voltage Vref. Figure 2 Taking the pixel driving circuit 10 shown as an example, the reference voltage line 22 is electrically connected to the fifth transistor T5 and / or the seventh transistor T7 in the pixel driving circuit 10.

[0096] Optional, such as Figure 18 As shown, the reference voltage line 22 includes a first sub-reference voltage line 2201 and / or a second sub-reference voltage line 2202. The first sub-reference voltage line 2201 extends along a first direction h1, and the second sub-reference voltage line 2202 extends along a second direction h2. The first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are electrically connected. For example, as shown... Figure 18As shown, a second sub-reference voltage signal line 2202 can be electrically connected to at least two first sub-reference voltage signal lines 2201, and a first sub-reference voltage signal line 2201 can be electrically connected to at least two second sub-reference voltage signal lines 2202, so that the reference voltage line 22 has a grid-like shape, which is beneficial to further increase the conduction path of the reference voltage Vref, reduce the voltage drop of the reference voltage Vref during transmission, and improve the brightness consistency of sub-pixels located at different positions in the display area AA.

[0097] For example, such as Figure 18 As shown, the non-display area NA also includes a reference voltage bus 52, and the reference voltage line 22 is electrically connected to the reference voltage bus 52 and the pixel driving circuit.

[0098] like Figure 18 As shown, the non-display area NA includes a first sub-non-display area NA1, and the first sub-non-display area NA1 includes a scan driving circuit 6. The scan driving circuit 6 is connected to the scan lines in the display area AA. Figure 18 Electrical connections (not shown). For example, the scan lines include the first scan signal line and / or the second scan signal line described above.

[0099] In related technologies, the reference voltage bus 52 is usually integrated into the scan driving circuit 6, resulting in a larger width of the first sub-non-display area NA1, which is not conducive to the narrow bezel design of the display panel. This embodiment of the invention reduces the voltage drop of the reference voltage Vref during transmission by setting a grid-like reference voltage line 22 in the display area AA. Based on this, this embodiment of the invention can reduce the width of the reference voltage bus 52 integrated in the scan driving circuit 6, or, as... Figure 18 As shown, in this embodiment of the invention, a reference voltage bus may not be required in the scan drive circuit 6. Figure 18 As shown, the non-display area NA also includes a second sub-non-display area NA2. The second sub-non-display area NA2 does not include the aforementioned scan drive circuit 6, and the reference voltage bus 52 is located in the second sub-non-display area NA2. This configuration helps to reduce the width of the first sub-non-display area NA1 occupied by the scan drive circuit 6, which is beneficial to increasing the area ratio of the display area AA in the display panel, that is, increasing the screen ratio of the display panel.

[0100] For example, Figure 19 As shown, Figure 19 This is a partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention, wherein two rows of pixel driving circuits are arranged along the second direction h2, and each row of pixel driving circuits includes seven pixel driving circuits arranged along the first direction h1, as illustrated. Each pixel driving circuit can be arranged according to... Figure 3 Configure it as shown in the diagram. Figure 19In the diagram, the reference voltage line 22 is illustrated by including a first sub-reference voltage line 2201 and a second sub-reference voltage line 2202. A portion of the first sub-reference voltage line 2201 is located between two adjacent pixel driving circuits 10 in the second direction h2; a portion of the second sub-reference voltage line 2202 is located between two adjacent pixel driving circuits 10 in the first direction h1. Along the thickness direction h3 of the display panel, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are offset from the pixel driving circuits 10.

[0101] For example, such as Figure 18 and Figure 19 As shown, in this embodiment of the invention, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 can be located in different film layers, and the two are electrically connected through the connection part K22.

[0102] Combination Figure 19 and Figure 20 As shown, Figure 20 for Figure 19 This is a top view of a semiconductor layer. In this embodiment of the invention, the first sub-reference voltage line 2201 can be disposed on the semiconductor layer S, that is, the first sub-reference voltage line 2201 is disposed on the same layer as the active layer of each of the thin-film transistors. The active layer includes the channel region, source region, and drain region of each of the thin-film transistors.

[0103] Optional, such as Figure 20 As shown, the first sub-reference voltage line 2201 is electrically connected to the ninth doped region S51 and the thirteenth doped region S71, respectively. This configuration, compared to using a metal layer to form the first sub-reference voltage line 2201, avoids the need for vias to connect the first sub-reference voltage line 2201 to the ninth doped region S51 and the thirteenth doped region S71, simplifying the display panel manufacturing process and reducing wiring complexity. Furthermore, to ensure process yield, a minimum spacing exists between different traces located on the same film layer. In this embodiment, by placing the first sub-reference voltage line 2201 in the semiconductor layer S, compared to placing it in the second metal layer M2, the distance between two adjacent pixel driving circuits 10 in the second direction h2 can be compressed. Figure 9 and Figure 21 ,like Figure 21 As shown, Figure 21 for Figure 19A top view of the second metal layer in the diagram shows that when the reference voltage line 22 is disposed in the second metal layer M2, the distance between the storage capacitors C of two adjacent pixel driving circuits 10 on the second direction h2 is d1. When the reference voltage line is disposed in the semiconductor layer S, that is, after removing the reference voltage line in the second metal layer M2, the distance between the storage capacitors C of two adjacent pixel driving circuits 10 on the second direction h2 is d2, where d2 < d1. This allows the pixel driving circuits 10 in the display area AA to be disposed more compactly on the second direction h2, which is beneficial for increasing the number of pixels per inch (PPI) of the display panel. For example, the portion of the semiconductor layer S used to form the first sub-reference voltage line 2201 can be produced using a heavily doped process.

[0104] When the first sub-reference voltage line 2201 is disposed on the same layer as the active layer of the thin-film transistor, embodiments of the present invention can make the first sub-reference voltage line 2201 electrically connected to the active layers of the thin-film transistors of two adjacent pixel driving circuits. The two adjacent pixel driving circuits are arranged along the extending direction of the first sub-reference voltage line 2201. For example, as shown... Figure 19 and Figure 20 As shown, the first sub-reference voltage line 2201 extends along the first direction h1. The ninth doped region S51 in the active layer of the pixel driving circuit adjacent to it on the first direction h1 is electrically connected through the first sub-reference voltage line 2201. The ninth doped region S51 is used to form the fifth transistor T5 in the pixel driving circuit. Optionally, as... Figure 19 and Figure 20 As shown, in this embodiment of the invention, multiple active layers arranged along the first direction h1 can be electrically connected to the same first sub-reference voltage line 2201.

[0105] Optional, such as Figure 22 As shown, Figure 22 for Figure 19 A top view of the fourth metal layer. In this embodiment of the invention, the second sub-reference voltage line 2202, the data line 34, and the second power line 35 extending along the second direction h2 can be disposed in the same layer of the fourth metal layer M4, so as to avoid the need to set an additional film layer in the display panel. On the one hand, the second sub-reference voltage line 2202, the data line 34, and the second power line 35 can be formed in the same process using the same material. On the other hand, it is also beneficial to reduce the thickness of the display panel.

[0106] For example, Figure 19 The first scan line 31, the second scan line 32, and the light emission control signal line 33 can be referenced. Figure 6 and Figure 14 The settings are as shown, and will not be repeated here.

[0107] Optional, such as Figure 23 and Figure 24 As shown, Figure 23 for Figure 19 A top view of the third metal layer in the structure. Figure 24 for Figure 19 A schematic cross-sectional view along DD' shows that the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are electrically connected via a connector K22. For example, as shown... Figure 24 As shown, the connecting part K22 includes a first sub-connecting hole K221 for electrical connection, a connecting wire 220, and a second sub-connecting hole K222. The first sub-connecting hole K221 penetrates the second insulating layer IS2, the third insulating layer IS3, and the fourth insulating layer IS4, and the second sub-connecting hole K222 penetrates the fifth insulating layer IS5. Figure 23 and Figure 24 As shown, the connecting line 220 is located in the third metal layer M3.

[0108] For example, such as Figure 25 and Figure 26 As shown, Figure 25 This is a partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention, wherein two rows of pixel driving circuits are arranged along the second direction h2, and each row of pixel driving circuits includes seven pixel driving circuits arranged along the first direction h1, as illustrated. Each pixel driving circuit can be arranged according to... Figure 3 Configure it as shown. Figure 26 for Figure 25 A schematic diagram of a cross-section along EE', in Figure 25 In the common branch line 2, there are a first power line 21 and a reference voltage line 22 along the thickness direction h3 of the display panel. In this embodiment of the invention, the first power line 21 and the reference voltage line 22 can partially overlap to avoid increasing the planar space occupied by the first power line 21 and the reference voltage line 22, which is beneficial to increasing the PPI of the display panel.

[0109] For example, when the first power line 21 includes a first sub-power line 2101 and a second sub-power line 2102, and the reference voltage line 22 includes a first sub-reference voltage line 2201 and a second sub-reference voltage line 2202, as follows: Figure 25 and Figure 26 As shown, along the thickness direction h3 of the display panel, in this embodiment of the invention, the first sub-power line 2101 and the first sub-reference voltage line 2201 can partially overlap, and the second sub-power line 2102 and the second sub-reference voltage line 2202 can partially overlap.

[0110] For example, in Figure 25 In this embodiment of the invention, the first sub-reference voltage line 2201 can be located in the semiconductor layer S, and the second sub-reference voltage line 2202 can be located in the fourth metal layer M4. Optionally, Figure 25 The arrangement of the structures in the semiconductor layer S can be according to Figure 20 Configure it as shown. Figure 25 The arrangement of the structures in the fourth metal layer M4 can be according to Figure 22 Configure it as shown. Figure 24 As shown, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 are electrically connected through the connecting line 220, the first sub-connecting hole K221 and the second sub-connecting hole K222.

[0111] Optional, in Figure 25 In this embodiment of the invention, the first sub-power line 2101 and the second sub-power line 2102 can be disposed on the same layer of the fifth metal layer M5. For example, Figure 25 The arrangement of the structures in the fifth metal layer M5 can be according to Figure 16 Configure it as shown.

[0112] It should be noted that, Figure 6 , Figure 14 , Figure 19 and Figure 25 This description of the embodiment of the invention only takes the example of the first node N1 and the fourth node N4 requiring the same reference voltage for reset. When the reference voltages required for reset of the first node N1 and the fourth node N4 are different, for example, when the first reference voltage Vref1 required for reset of the first node N1 and the second reference voltage Vref2 required for reset of the fourth node N4 are different, combined with... Figure 27 and Figure 28 As shown, Figure 27 This is a partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention, wherein two rows of pixel driving circuits are arranged along the second direction h2, and each row of pixel driving circuits includes seven pixel driving circuits arranged along the first direction h1 as an illustration. Figure 28 for Figure 27 A top view of a semiconductor layer in [the image / structure]. Figure 27 In the above, the reference voltage line 22 includes a first reference voltage line 221 and a second reference voltage line 222. The first reference voltage line 221 is used to transmit the first reference voltage Vref1, and the second reference voltage line 222 is used to transmit the second reference voltage Vref2.

[0113] Optionally, the first reference voltage line 221 includes a first sub-reference voltage line 2201 extending along a first direction h1 and a second sub-reference voltage line 2202 extending along a second direction h2, which are electrically connected and both transmit the first reference voltage Vref1. The second reference voltage line 222 includes a first sub-reference voltage line 2201 extending along the first direction h1 and a second sub-reference voltage line 2202 extending along the second direction h2, which are electrically connected and both transmit the second reference voltage Vref2.

[0114] For example, such as Figure 27 and Figure 28 As shown, the first sub-reference voltage line 2201 of the first reference voltage line 221 and the first sub-reference voltage line 2201 of the second reference voltage line 222 can be simultaneously set between two adjacent pixel driving circuits on the second direction h2. The first sub-reference voltage line 2201 of the first reference voltage line 221 is electrically connected to the ninth doped region S51 of the fifth transistor T5 of the pixel driving circuit located below it, and the first sub-reference voltage line 2201 of the second reference voltage line 222 is electrically connected to the thirteenth doped region S71 of the seventh transistor T7 of the pixel driving circuit located above it.

[0115] Optional, such as Figure 27 and Figure 29 As shown, Figure 29 for Figure 27 A top view of the fourth metal layer in the first reference voltage line 221, the second sub-reference voltage line 2202 of the first reference voltage line 221 and the second sub-reference voltage line 2202 of the second reference voltage line 222 can be alternately arranged between different pixel driving circuits arranged adjacently on the first direction h1.

[0116] Optional, such as Figure 27 As shown, the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 included in the first reference voltage line 221 are electrically connected through the connecting part K31, and the first sub-reference voltage line 2201 and the second sub-reference voltage line 2202 included in the second reference voltage line 222 are electrically connected through the connecting part K32. Both the connecting part K31 and the connecting part K32 may include... Figure 24 The connection part K22 shown is configured in this manner.

[0117] Optional, such as Figure 6 , Figure 14 , Figure 19 , Figure 25 and Figure 27 As shown, the multiple pixel driving circuits 10 include a first pixel driving circuit 101, a second pixel driving circuit 102, and a third pixel driving circuit 103. Figure 6 , Figure 14 , Figure 19 , Figure 25 and Figure 27 The diagram illustrates a first pixel driving circuit 101, a second pixel driving circuit 102, and a third pixel driving circuit 103 arranged along a first direction h1. Along the first direction h1, the distance d12 between the first pixel driving circuit 1011 and the second pixel driving circuit 102 is greater than or equal to the distance d23 between the second pixel driving circuit 102 and the third pixel driving circuit 103. (Combined...) Figure 7 As shown, in this embodiment of the invention, the distance between two adjacent pixel driving circuits in the first direction h1 is the distance between the first channel region S10 of one pixel driving circuit and the sixth channel region S60 of another pixel driving circuit in the semiconductor layer S. The distance between two adjacent pixel driving circuits in the second direction h2 is the distance between the ninth doped region S51 of one pixel driving circuit and the thirteenth doped region S71 of another pixel driving circuit. In this embodiment of the invention, a portion of the common branch 2 is located between the first pixel driving circuit 101 and the second pixel driving circuit 102. That is, a portion of the common branch 2 is located between two adjacent pixel driving circuits with a larger spacing. In this embodiment of the invention, by adjusting the spacing of some pixel driving circuits, the distance d12 between the first pixel driving circuit 101 and the second pixel driving circuit 102 is greater than or equal to the distance d23 between the second pixel driving circuit 102 and the third pixel driving circuit 103. This allows space to be provided for the setting of the common branch line 2, reducing the wiring difficulty of the common branch line 2. Moreover, by setting the common branch line 2 between the first pixel driving circuit 101 and the second pixel driving circuit 102, this embodiment of the invention also helps to reduce the impact of the common branch line 2 on the pixel driving circuit 10.

[0118] For example, in this embodiment of the invention, N pixel driving circuits 10 are included between two adjacent common branches 2, where N is an integer greater than or equal to 1. For instance, in this embodiment of the invention, N can be an integer greater than or equal to 2, so that while utilizing the common branch 2 to reduce the voltage drop of the corresponding common voltage during transmission, it is also possible to avoid adjusting the spacing of too many pixel driving circuits 10, allowing the distance between two adjacent pixel driving circuits 10 to be set smaller, thereby improving the PPI of the display panel.

[0119] For example, such as Figure 6 , Figure 14 , Figure 19 , Figure 25 and Figure 27As shown, the common branch 2 includes a first sub-common branch 201 and a second sub-common branch 202 electrically connected. The first sub-common branch 201 extends along a first direction h1, and the second sub-common branch 202 extends along a second direction h2. The statement that N pixel driving circuits 10 are included between two adjacent common branches 2 means that N pixel driving circuits 10 are included between two adjacent first sub-common branches 201, or N pixel driving circuits 10 are included between two adjacent second sub-common branches 202. When the common branch 2 includes a first power line 21, as... Figure 6 , Figure 14 and Figure 25 As shown, the first sub-common branch 201 includes the aforementioned first sub-power line 2101, and the second sub-common branch 202 includes the aforementioned second sub-power line 2102. When the common branch 2 includes the reference voltage line 22, as... Figure 6 , Figure 14 , Figure 19 and Figure 25 As shown, the first sub-common branch 201 includes the aforementioned first sub-reference voltage line 2201, and the second sub-common branch 202 includes the aforementioned second sub-reference voltage line 2202. Figure 6 , Figure 14 , Figure 19 and Figure 25 The diagram illustrates a scenario where three pixel driving circuits 10 are spaced between two adjacent second sub-common branches 202, i.e., N=3.

[0120] For example, such as Figure 30 As shown, Figure 30 This is a partially enlarged schematic diagram of the display area of ​​another display panel provided in an embodiment of the present invention, wherein two rows of pixel driving circuits are arranged along the second direction h2, and each row of pixel driving circuits includes seven pixel driving circuits arranged along the first direction h1, as illustrated. Each pixel driving circuit can be arranged according to... Figure 3 The display panel is configured as shown, including a gap region GA located between two adjacent pixel driving circuits 10; the common branch line 2 includes a first power line 21 and a reference voltage line 22, which are located in different gap regions GA.

[0121] For example, when the first power line 21 includes a first sub-power line 2101 and / or a second sub-power line 2102, and the reference voltage line 22 includes a first sub-reference voltage line 2201 and / or a second sub-reference voltage line 2202, the first power line 21 and the reference voltage line 22 are located in different gap regions GA, including the first sub-power line 2101 and the first sub-reference voltage line 2201 being located in different gap regions GA, or the second sub-power line 2102 and the second sub-reference voltage line 2202 being located in different gap regions GA. This configuration allows the first sub-power line 2101 and the first sub-reference voltage line 2201 to be distributed at different locations within the display area AA, or the second sub-power line 2102 and the second sub-reference voltage line 2202 to be distributed at different locations within the display area AA, thereby reducing the coupling between the first power supply voltage PVEE and the reference voltage Vref.

[0122] It should be noted that, Figure 30 The illustration shows a first sub-reference voltage line 2201 electrically connected to each pixel driving circuit row, and a second sub-reference voltage line 2202 every three pixel driving circuit columns. This is merely one example. The pixel driving circuit column includes multiple pixel driving circuits arranged along the second direction h2. While ensuring that the reference voltage line 22 provides a reference voltage Vref to the multiple pixel driving circuits in the display area, this embodiment of the invention does not limit the number and positional distribution of the first sub-reference voltage lines 2201 and second sub-reference voltage lines 2202 in the reference voltage line 22. For example, this embodiment of the invention may also provide a second sub-reference voltage line electrically connected to each pixel driving circuit column, and a first sub-reference voltage line every at least two pixel driving circuit rows.

[0123] When a first sub-reference voltage line 2201 electrically connected to each pixel driving circuit row is provided, and a second sub-reference voltage line 2202 is provided every two pixel driving circuit columns, for example, as shown below. Figure 30 As shown, in this embodiment of the invention, the first sub-power line can be omitted from the display area, and the first power line 21 can include the second sub-power line 2102, with the second sub-power line 2102 and the second sub-reference voltage line 2202 located in different gap areas GA.

[0124] When a second sub-reference voltage line is provided for each pixel driving circuit column and a first sub-reference voltage line is provided every two pixel driving circuit rows, optionally, in this embodiment of the invention, the second sub-power line is not provided in the display area, the first power line includes the first sub-power line, and the first sub-power line and the first sub-reference voltage line are located in different gap areas.

[0125] For example, in embodiments of the present invention, the first power line 21 and the reference voltage line 22 located in different gap regions GA can be arranged on the same layer. Figure 30 and Figure 31 As shown, Figure 31 for Figure 30 A top view of the fourth metal layer in the present invention shows that, in this embodiment, the second sub-reference voltage line 2202 and the second sub-power line 2102 can be disposed in the same layer on the fourth metal layer M4. This arrangement allows the second sub-reference voltage line 2202 and the second sub-power line 2102 to be formed simultaneously using the same material in the same process, which simplifies the manufacturing process of the display panel and reduces the thickness of the display panel.

[0126] For example, such as Figure 32 As shown, Figure 32 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The plurality of data lines 34 include at least an inner data line 341 and at least one edge data line 342, with the edge data line 342 located on the side of the inner data line 341 near the edge E of the display panel. The display area AA also includes a connecting line 3 electrically connected to the edge data line 342. Figure 32 As shown, the end D1 of the connecting line 3 near the non-display area AA is located on the side of the edge data line 342 near the inner data line 341. The connecting line 3 electrically connects the pad 53 and the corresponding edge data line 342. The arrangement of the connecting line 3 avoids the need for fan-out lines electrically connected to the edge data line 342 in the non-display area NA, thereby reducing the number of fan-out lines in the non-display area NA and consequently reducing the width of the non-display area NA. Specifically, when the display panel is configured to have... Figure 32 When the rounded corner shape is shown, the setting of connecting line 3 can reduce the width of the non-display area NA located at the rounded corner.

[0127] For example, such as Figure 32 As shown, in this embodiment of the invention, at least a portion of the connecting line 3 can be located between two adjacent pixel driving circuits 10.

[0128] For example, such as Figure 32 As shown, the connecting line 3 includes a first sub-connecting line 301 and a second sub-connecting line 302 that are electrically connected; the first sub-connecting line 301 extends along a first direction h1, and the second sub-connecting line 302 extends along a second direction h2.

[0129] Optionally, when setting the first sub-connecting line 301, in this embodiment of the invention, the first sub-connecting line 301 and the first sub-power line 2101 can be disposed on the same layer in different gap areas GA to simplify the manufacturing process of the display panel and reduce the thickness of the display panel. For example, the first sub-connecting line 301 and the first sub-power line 2101 can be disposed on the same layer in the fifth metal layer M5.

[0130] When configuring the second sub-connecting line 302, optionally, in this embodiment of the invention, the second sub-connecting line 302 can be configured on the same layer as the second sub-common branch line 202 to simplify the manufacturing process of the display panel and reduce the thickness of the display panel. The second sub-common branch line 202 includes the second sub-power line 2102 and / or the second sub-reference voltage line 2202. Optionally, such as... Figure 33 As shown, Figure 33 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention, wherein the second sub-common branch 202 includes the second sub-power line 2102, the second sub-connecting line 302 and the second sub-power line 2102 are disposed on the same layer of the fourth metal layer M4, and the second sub-connecting line 302 and the second sub-power line 2102 are respectively located in different gap areas GA as an illustration.

[0131] Alternatively, in embodiments of the present invention, the first sub-connecting line 301 may be disposed on a different layer from the first sub-common branch line 201, and the first sub-connecting line 301 and the first sub-common branch line 201 may at least partially overlap along the thickness direction h3 of the display panel; and / or, the second sub-connecting line 302 may be disposed on a different layer from the second sub-common branch line 202, and the second sub-connecting line 302 and the second sub-common branch line 202 may at least partially overlap along the thickness direction h3 of the display panel. Figure 34 As shown, Figure 34 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention, wherein the first sub-common branch 201 includes a first sub-reference voltage line 2201, the second sub-common branch 202 includes a second sub-power line 2102, the first sub-connection line 301 is located in the fifth metal layer M5, the first sub-reference voltage line 2201 is located in the semiconductor layer S, and the first sub-connection line 301 and the first sub-reference voltage line 2201 at least partially overlap along the thickness direction h3 of the display panel. The second sub-connection line 302 is located in the sixth metal layer M6, the second sub-power line 2102 is located in the fourth metal layer M4, and the second sub-connection line 302 and the second sub-power line 2102 at least partially overlap along the thickness direction h3 of the display panel. Figure 34 As shown, the first sub-connecting line 301 and the second sub-connecting line 302 are electrically connected through the connecting hole K3.

[0132] Optional, such as Figure 35 and Figure 36 As shown, Figure 35 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. Figure 36 for Figure 35 An enlarged schematic diagram of the central region R, showing that the display area AA also includes touch electrodes 6. For example, in conjunction with... Figure 37 As shown, Figure 37 This is a cross-sectional schematic diagram of another display panel provided in an embodiment of the present invention, wherein the touch electrode 6 is located on the side of the light-emitting element 11 away from the substrate 41. Figure 35 As shown, the touch electrode 6 includes a driving electrode 601 and a sensing electrode 602. Along the thickness direction h3 of the display panel, the touch electrode 6 and the common branch line 2 at least partially overlap. This arrangement helps to increase the light-transmitting area within the display area AA. When this display panel is used for fingerprint recognition, based on the arrangement provided in this embodiment of the invention, the influence of the common branch line 2 on the light transmittance of the display panel can be avoided, ensuring the fingerprint recognition sensitivity of the display panel. For example, as... Figure 35 As shown, the common branch 2 extends along the edge of the touch electrode 6 at least in some locations to increase the overlap area between the common branch 2 and the touch electrode 6, thereby ensuring the light-transmitting area within the display area AA.

[0133] Optional, such as Figure 36 and Figure 40 As shown, the touch electrode 6 has an opening 60 and intersecting touch grid lines 61. The opening 60 exposes at least a portion of the second electrode 112 of the light-emitting element 11 to prevent the arrangement of the touch electrode 6 from affecting the light emission of the sub-pixel. Figure 35 , Figure 36 and Figure 37 As shown, along the thickness direction h3 of the display panel, the touch grid lines 61 and the common branch lines 2 in the touch electrode 6 at least partially overlap to increase the light transmission area in the display area AA.

[0134] Combination Figure 37 As shown, the display panel also includes an encapsulation layer 44 and a touch layer 45, with the touch layer 45 located on the side of the encapsulation layer 44 away from the display film layer 43. The touch layer 44 includes the aforementioned touch electrode 6. The touch electrode 6 and the common branch line 2 are separated by the encapsulation layer 44. For example, as... Figure 37 As shown, the encapsulation layer 44 includes a first inorganic encapsulation layer 441, an organic encapsulation layer 440, and a second inorganic encapsulation layer 442 stacked together. Based on this arrangement, a larger distance can be maintained between the touch electrode 6 and the common branch line 2, which helps to reduce coupling interference between them.

[0135] It should be noted that, in order to more clearly illustrate the relative positions of the second electrode 112, the touch electrode 6, and the common branch 2, in Figure 36 The pixel driving circuit is not shown in the diagram. Also, Figure 6 , Figure 14 , Figure 19 , Figure 25 and Figure 27The shape of the common branch 2 shown is a straight line only. In the design process of the display panel, the shape of the common branch 2 can be designed accordingly based on the shape of the touch electrode and the shape of the gap of the pixel driving circuit 10.

[0136] For example, such as Figure 5 and Figure 18 As shown, the non-display area NA includes a common bus 5 and pads 53; the common bus 5 is electrically connected to the corresponding common branch 2. Specifically, the common bus 5 includes the aforementioned first power bus 51 and / or reference voltage bus 52. When setting the common bus 5, along the second direction h2, the common bus 5 and pads 53 are located on opposite sides of the display area AA. This arrangement, compared to setting the common bus 5 and pads 53 on the same side of the display area AA, avoids the non-display area NA from being too wide on only one side of the display area AA. Figure 5 As shown, along the second direction h2, the first power bus 51 and the pad 53 are located on both sides of the display area AA. Figure 18 As shown, along the second direction h2, the reference voltage bus 52 and the pad 53 are located on both sides of the display area AA.

[0137] For example, such as Figure 5 and Figure 18 As shown, the width W5 of the common bus 5 is greater than or equal to the width W2 of the common branch line 2. This arrangement helps to reduce the voltage drop of the signal transmitted by the common bus 5 during propagation. Optionally, in this embodiment of the invention, the common branch line 2 and the common bus 5 can be arranged on the same layer, or they can be arranged on different layers. This embodiment of the invention does not limit this.

[0138] For example, such as Figure 5 and 18 As shown, the non-display area NA includes a first sub-non-display area NA1 and a second sub-non-display area NA2. The first sub-non-display area NA1 includes a scan driving circuit 6. The second sub-non-display area NA2 includes a common connection line 7, which is electrically connected to a corresponding common bus 5 and a common branch line 2. For example, the common connection line 7 includes a power connection line 71 or a reference voltage connection line 72. The power connection line 71 is electrically connected to the first power bus 51 and the aforementioned first power line 21, and the reference voltage connection line 72 is electrically connected to the reference voltage bus 52 and the aforementioned reference voltage line 22. Figure 5 The diagram illustrates the connection of power cable 71 to the first power bus 51 and the first power line 21. Figure 18The reference voltage connection line 72 is used to electrically connect the reference voltage bus 52 and the aforementioned reference voltage line 22 as an example. Based on the configuration provided in this embodiment of the invention, it is possible to avoid drawing the common connection line 7, which electrically connects the common bus 5 and the common branch line 2, from the first sub-non-display area NA1 where the scan drive circuit 6 is located. That is, by setting the common connection line 7 away from the scan drive circuit 6, it is beneficial to reduce the width of the first sub-non-display area NA1 where the scan drive circuit 6 is located.

[0139] For example, such as Figure 38 As shown, Figure 38 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The non-display area NA includes an irregularly shaped non-display area NA31 and a regular non-display area NA32. The line width W31 of the common bus 5 in the irregularly shaped non-display area NA31 is greater than or equal to the line width W32 of the common bus 5 in the regular non-display area NA3. The edge shape of the irregularly shaped non-display area NA2 includes a curve, while the edge of the regular non-display area NA3 includes a straight line. For example, for a display panel having... Figure 38 For the rounded rectangular display panel shown, the irregular non-display area NA2 corresponds to the rounded corner area of ​​the display panel, and the regular non-display area NA3 corresponds to the area where the long or short side of the display panel is located. Generally speaking, the space in the irregular non-display area NA2 is more abundant than the space in the regular non-display area NA3. In this embodiment of the invention, by setting the line width W31 of the common bus 5 in the irregular non-display area NA2 to be greater than or equal to the line width W32 of the common bus 5 in the regular non-display area NA3, the line width of the common bus 5 can be set as large as possible within the existing wiring space, which is beneficial to reduce the resistance of the common bus 5 and the voltage drop of the signal transmitted by the common bus 5 during transmission.

[0140] For example, such as Figure 39 As shown, Figure 39 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The common bus 5 includes a first sub-common bus 501 and a second sub-common bus 502 electrically connected. The width of the first sub-common bus 501 is less than or equal to the width of the second sub-common bus 502. This arrangement helps to reduce the space occupied by the first sub-common bus 501 in the non-display area NA, leaving space for the arrangement of other traces. Optionally, such as... Figure 39 As shown, in this embodiment of the invention, the common branch 2 is electrically connected to at least the first sub-common bus 501. This arrangement helps to reduce the load on the first sub-common bus 501, which has a smaller width, thereby reducing the heat generation of the first sub-common bus 501 during the operation of the display panel and improving the reliability of the first sub-common bus 501.

[0141] For example, such as Figure 40 As shown, Figure 40 for Figure 38 An enlarged schematic diagram of the central region Q shows that the common bus 5 includes an opening 50. The opening 50 serves two purposes: firstly, it allows gas released from the organic layer located below the common bus 5 to escape, preventing bulging caused by gas overflow in the common bus 5 and improving the reliability of the display panel; secondly, it reduces the overlap area between the common bus 5 and other traces, thereby reducing the coupling between the common bus 5 and other traces.

[0142] This invention also provides a display device, such as... Figure 41 As shown, Figure 41 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Figure 41 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0143] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that, Includes display area and non-display area; The display area includes: Multiple sub-pixels, each sub-pixel including an electrically connected pixel driving circuit and a light-emitting element; each light-emitting element including a first electrode, the first electrodes of different light-emitting elements being electrically connected; A common branch line is electrically connected to multiple of the said sub-pixels; Along the thickness direction of the display panel, the common branch line is offset from the pixel driving circuit; The non-display area includes a common bus; the common bus is electrically connected to the common branch line. The width of the common bus is greater than or equal to the width of the common branch line; The common bus includes a first sub-common bus and a second sub-common bus that are electrically connected. The width of the first sub-common bus is less than or equal to the width of the second sub-common bus, and the common branch is at least electrically connected to the first sub-common bus; The common branch line includes a first power line and a reference voltage line; the first power line is electrically connected to the first electrode of the light-emitting element; the reference voltage line is electrically connected to the pixel driving circuit. The display panel includes a gap region located between two adjacent pixel driving circuits; the first power line and the reference voltage line are located in different gap regions.

2. The display panel according to claim 1, characterized in that, The plurality of pixel driving circuits includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit; the distance between the first pixel driving circuit and the second pixel driving circuit is greater than or equal to the distance between the second pixel driving circuit and the third pixel driving circuit. The portion of the common branch is located between the first pixel driving circuit and the second pixel driving circuit.

3. The display panel according to claim 1, characterized in that, Between two adjacent common branches, there are N pixel driving circuits, where N is an integer greater than or equal to 1.

4. The display panel according to claim 1, characterized in that, The first power line includes a first sub-power line and a second sub-power line that are electrically connected. The first sub-power line extends along a first direction, and the second sub-power line extends along a second direction. The first direction and the second direction intersect. A portion of the first sub-power line is located between two adjacent pixel driving circuits in the second direction, and a portion of the second sub-power line is located between two adjacent pixel driving circuits in the first direction.

5. The display panel according to claim 4, characterized in that, The first sub-power line and the second sub-power line are arranged on the same layer.

6. The display panel according to claim 1, characterized in that, The reference voltage line includes a first sub-reference voltage line and a second sub-reference voltage line that are electrically connected. The first sub-reference voltage line extends along a first direction, and the second sub-reference voltage line extends along a second direction. The first direction and the second direction intersect. A portion of the first sub-reference voltage line is located between two adjacent pixel driving circuits in the second direction; a portion of the second sub-reference voltage line is located between two adjacent pixel driving circuits in the first direction.

7. The display panel according to claim 6, characterized in that, The pixel driving circuit includes multiple thin-film transistors, and the first sub-reference voltage line is disposed on the same layer as the active layer of the thin-film transistors.

8. The display panel according to claim 7, characterized in that, The first sub-reference voltage line is electrically connected to the active layer of the thin-film transistor of two adjacent pixel driving circuits, wherein the two adjacent pixel driving circuits are arranged along the extension direction of the first sub-reference voltage line.

9. The display panel according to claim 6, characterized in that, It also includes a data line electrically connected to the pixel driving circuit; The second sub-reference voltage line is arranged on the same layer as the data line.

10. The display panel according to claim 1, characterized in that, The non-display area includes a first power bus and pads; the first power bus is electrically connected to the first power line. The first power bus and the pads are located on both sides of the display area.

11. The display panel according to claim 1, characterized in that, The first power line includes a first sub-power line and a second sub-power line that are electrically connected; the reference voltage line includes a first sub-reference voltage line and a second sub-reference voltage line that are electrically connected; the first sub-power line and the first sub-reference voltage line extend along a first direction, and the second sub-power line and the second sub-reference voltage line extend along a second direction; the first direction and the second direction intersect. The second sub-reference voltage line and the second sub-power line are arranged on the same layer.

12. The display panel according to claim 1, characterized in that, The display area also includes: Multiple data lines are arranged along a first direction, and the data lines are electrically connected to the pixel driving circuit; the multiple data lines include an inner data line and at least one edge data line, and the edge data line is located on the side of the inner data line close to the edge of the display panel; A connecting line is electrically connected to the edge data line; the end of the connecting line near the non-display area is located on the side of the edge data line near the inner data line.

13. The display panel according to claim 12, characterized in that, The connecting line includes a first sub-connecting line and a second sub-connecting line that are electrically connected; the common branch line includes a first sub-common branch line and a second common branch line that are electrically connected. The first sub-connecting line and the first sub-common branch line extend along a first direction, and the second sub-connecting line and the second sub-common branch line extend along a second direction; the first direction and the second direction intersect. The second sub-connecting line is installed on the same layer as the second sub-common branch line.

14. The display panel according to claim 1, characterized in that, The display area also includes touch electrodes, and the touch electrodes and the common branch line at least partially overlap along the thickness direction of the display panel.

15. The display panel according to claim 1, characterized in that, The non-display area includes irregularly shaped non-display areas and regular non-display areas; The line width of the common bus in the irregular non-display area is greater than or equal to the line width of the common bus in the regular non-display area.

16. The display panel according to claim 1, characterized in that, The display area includes scan lines; The non-display area includes a first sub-non-display area and a second sub-non-display area. The first sub-non-display area includes a scan driving circuit, which is electrically connected to the scan line. The second sub-display area includes a common connection line, which electrically connects the common bus and the common branch line.

17. The display panel according to claim 1, characterized in that, The common bus includes an opening.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1-17.

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