Transparent display device

Abstract

A transparent display device is provided that improves reflection visibility between a display area and a non-display area. The transparent display device includes a substrate provided with a display area and a non-display area adjacent to the display area, in which a plurality of pixels having a first transmissive portion and a plurality of sub-pixels are provided; and a plurality of GIP portions provided over the substrate in the non-display area, each including a second transmissive portion and a plurality of block portions, wherein the plurality of sub-pixels include a first sub-pixel provided to emit white light, the plurality of block portions include a first block portion provided at a position corresponding to the first sub-pixel, and the first block portion includes a dummy pattern provided to be the same as or similar to the first sub-pixel.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a transparent display apparatus. BACKGROUND

[0002] As the information age has developed, the demand for display apparatuses for displaying images has increased in various forms. Accordingly, various types of display apparatuses, such as liquid crystal display (LCD) apparatuses, plasma display panel (PDP) apparatuses, organic light emitting display (OLED) apparatuses, and quantum dot light emitting display (QLED) apparatuses, have recently been used.

[0003] Recently, research into a transparent display apparatus in which a user can view an object or an image located at an opposite side through a display apparatus is actively being conducted.

[0004] A transparent display apparatus includes a display area on which an image is displayed and a non-display area including a bezel area, wherein the display area can include a transmissive area capable of transmitting external light and a non-transmissive area such as a pixel. SUMMARY

[0005] A plurality of signal lines for driving pixels of the display area and a plurality of circuits are disposed in the non-display area, and a plurality of pixels are disposed in the display area to display an image. Accordingly, since the structures of the display area and the non-display area are different from each other, a problem of a difference in reflection visibility with respect to external light occurs.

[0006] The disclosure has been made in view of the above-mentioned problems, and it is an object of the disclosure to provide a transparent display apparatus that improves reflection visibility between a display area and a non-display area.

[0007] In addition to the object of the disclosure as described above, further objects and features of the disclosure will be clearly understood by those skilled in the art from the following description of the disclosure.

[0008] According to an aspect of the disclosure, the above and other objects can be achieved by providing a transparent display apparatus including a substrate provided with a display area in which a plurality of pixels having a first transmissive portion and a plurality of sub-pixels are disposed, and a non-display area adjacent to the display area, and a plurality of GIP portions disposed in the non-display area above the substrate, the plurality of GIP portions each including a second transmissive portion and a plurality of block portions, wherein the plurality of sub-pixels include a first sub-pixel disposed to emit white light, the plurality of block portions include a first block portion disposed at a position corresponding to the first sub-pixel, and the first block portion includes a dummy pattern disposed to be the same as or similar to the first sub-pixel.

[0009] According to another aspect of the present disclosure, the above and other objects can be achieved by providing a transparent display apparatus including a substrate provided with a display area and a non-display area adjacent to the display area, in which a plurality of pixels having a first transmissive portion and a plurality of sub-pixels are provided, and a plurality of GIP portions provided over the substrate in the non-display area, the plurality of GIP portions each including a second transmissive portion and a plurality of block portions, wherein the plurality of sub-pixels include a first sub-pixel in which at least three pixel metal layers are disposed to overlap each other, the plurality of block portions include a first block portion disposed at a position corresponding to the first sub-pixel, and the first block portion includes at least three non-pixel metal layers disposed on the same layer as the at least three pixel metal layers and to overlap each other. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view illustrating a transparent display apparatus according to an embodiment of the present disclosure;

[0012] Figure 2 is a schematic enlarged view illustrating a portion A in Figure 1 ;

[0013] Figure 3 is a schematic cross-sectional view taken along a line I-I' shown in Figure 2 ;

[0014] Figure 4 is a schematic enlarged view illustrating a portion B in Figure 1 ;

[0015] Figure 5 is a schematic cross-sectional view taken along a line II-II' shown in Figure 4 ;

[0016] Figure 6 is a plan view illustrating a transparent display apparatus according to another embodiment of the present disclosure;

[0017] Figure 7 is a plan view illustrating another example of a portion C in Figure 1 included in a transparent display apparatus according to another embodiment of the present disclosure;

[0018] Figure 8 is a schematic enlarged view illustrating another example of a portion A in Figure 1 included in a transparent display apparatus according to another variant embodiment of the present disclosure; and

[0019] Figure 9 is an example of a portion B in FIGS. 1A and 1B. Figure 1 is an example of a portion B of another example. DETAILED DESCRIPTION

[0020] Reference will now be made in detail embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. The following embodiments will be described in sufficient detail to enable those skilled in the art to make and use the disclosure, and the embodiments will be described with the recognition that the disclosure can be practiced with different forms of implementation and thus can not be limited to the embodiments set forth in the description. Rather, the following embodiments are provided so as to enable a thorough and complete disclosure of the present disclosure, and to convey the full scope of the present disclosure to those skilled in the art.

[0021] The shapes, sizes, ratios, angles, and numbers disclosed in the drawings for describing the embodiments of the present disclosure are merely examples, and thus the present disclosure is not limited to the illustrated details. The same reference numbers are used throughout the specification to refer to the same elements. In the following description, detailed descriptions of functions or configurations that are determined to unnecessarily obscure the gist of the present disclosure will be omitted.

[0022] In the case of using "include", "have", and "comprise" in the present specification, another part can be added unless "only" is used. Unless mentioned to the contrary, the singular form can include the plural form.

[0023] In interpreting elements, the elements are interpreted to include an error range even if not explicitly described.

[0024] In describing positional relationships, for example, when the positional relationship between two components is described as "on", "above", "below", and "near", one or more other components can be disposed between the two components unless "only" or "directly" is used.

[0025] In describing temporal relationships, for example, when the temporal order is described as "after", "subsequently", "then", and "before", a discontinuous case can be included unless "only" or "directly" is used.

[0026] It should be understood that, although the terms “first,” “second,” etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the present disclosure.

[0027] The “X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be interpreted only by geometric relations of mutual perpendicularity, but can have a wider directionality within a range in which elements of the present disclosure can functionally act.

[0028] The term “at least one of’ should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of “at least one of a first item, a second item, and a third item” indicates all of the possible combinations of the items from among the two or more items, as well as the first item only, the second item only, the third item only, the first item and the second item only, the first item and the third item only, the second item and the third item only, any one of the first item, the second item, and the third item, and the like.

[0029] The term “metal” used herein should be understood to include electrically conductive metal compounds such as TiN, other electrically conductive compounds, or other electrically conductive materials.

[0030] Features of various embodiments of the present disclosure can be partially or wholly coupled or combined with each other, and can interoperate and be technically driven in various ways as can be fully understood by those skilled in the art. Embodiments of the present disclosure can be executed independently of each other, or can be executed together in a dependent relationship.

[0031] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a plan view illustrating a transparent display apparatus according to one embodiment of the present disclosure, Figure 2 is a schematic enlarged view illustrating a portion A in Figure 1 Figure 3 is a schematic cross-sectional view taken along a line I-I’ shown in Figure 2 Figure 4 is a schematic enlarged view illustrating a portion B in Figure 1 Figure 5 is a schematic cross-sectional view taken along a line II-II’ shown in Figure 4

[0033] ​​​​In the following description, the transparent display device 100 according to one embodiment of the present disclosure is an organic light-emitting display device, but is not limited thereto. That is, the transparent display device according to one embodiment of the present disclosure can be implemented as any one of a liquid crystal display device, a field emission display device, a quantum dot light-emitting diode device, an electrophoretic display device, and an organic light-emitting display device.

[0034] Reference Figures 1 to 5 A transparent display device 100 according to one embodiment of the present disclosure may include: a display panel having a gating driver GD, the gating driver GD including a dummy pattern DMP; a source driver integrated circuit (hereinafter referred to as "IC") 130; a flexible film 140; a circuit board 150; and a timing controller 160.

[0035] The display panel may include a substrate 110 and a opposing substrate 120 bonded to each other. Figure 3 (as shown in the image).

[0036] Substrate 110 may include thin-film transistors and may be a transistor array substrate, a lower substrate, a base substrate, or a first substrate. Substrate 110 may be a transparent glass substrate or a transparent plastic substrate. For example, substrate 110 may be a transparent glass substrate. Hereinafter, substrate 110 will be defined as or referred to as the first substrate.

[0037] The opposing substrate 120 can be bonded to the first substrate 110 via a transparent connecting member (not shown). For example, the opposing substrate 120 may be smaller than the first substrate 110 and can be bonded to the remainder of the first substrate 110 except for the pad area. The transparent connecting member can be an adhesive member (or a transparent adhesive). The opposing substrate 120 can be an upper substrate, a second substrate, or a package substrate. The opposing substrate 120 can be bonded to a first surface of the first substrate 110 using an adhesive member via a substrate bonding process. Hereinafter, the opposing substrate 120 will be defined as or referred to as the second substrate.

[0038] According to the example, the first substrate 110 may include a display area DA and a non-display area NDA.

[0039] The display area DA is the area where an image is displayed, and it can be a pixel array area, an active area, a pixel array unit, a display unit, or a screen. For example, the display area DA can be located in the central part of the display panel.

[0040] The display area DA according to an example can include a gate line, a data line, a pixel driving power line, and a plurality of pixels P. Each of the plurality of pixels P can include a plurality of sub-pixels SP which can be defined by the gate line and the data line, and a first transmissive portion TR1 disposed adjacent to some or all of the plurality of sub-pixels SP. The first transmissive portion TR1 is a region disposed to allow light to be transmitted through a front surface and a rear surface of the display panel. Accordingly, a user located in a front surface direction of the display panel can view an image or a background located in a rear surface direction of the display panel through the first transmissive portion TR1.

[0041] Each of the plurality of sub-pixels SP can be defined as or referred to as a minimum unit region in which light is actually emitted.

[0042] According to an example, at least four sub-pixels and one first transmissive portion TR1 disposed adjacent to each other among the plurality of sub-pixels SP constitute one unit pixel P. One unit pixel can include, but is not limited to, a red sub-pixel, a green sub-pixel, a blue sub-pixel, a white sub-pixel, and the first transmissive portion TR1. As an example, one unit pixel can include at least one red sub-pixel, at least one green sub-pixel, at least one blue sub-pixel, at least one white sub-pixel, and at least one first transmissive portion TR1.

[0043] According to another example, three sub-pixels and one first transmissive portion TR1 disposed adjacent to each other among the plurality of sub-pixels SP constitute one unit pixel. One unit pixel can include, but is not limited to, at least one red sub-pixel, at least one green sub-pixel, at least one blue sub-pixel, and at least one first transmissive portion TR1.

[0044] Each of the plurality of sub-pixels SP includes a thin film transistor and a light emitting portion connected to the thin film transistor. The light emitting portion can include a light emitting element layer (or an organic light emitting layer) interposed between a first electrode and a second electrode.

[0045] The light emitting element layers respectively disposed in the plurality of sub-pixels SP can individually emit light of their respective different colors from each other or collectively emit white light. According to an example, when the light emitting element layers of the plurality of sub-pixels SP collectively emit white light, each of the red sub-pixel, the green sub-pixel, and the blue sub-pixel can include a color filter (or a wavelength conversion member) for converting the white light into light of their respective different colors. In this case, the white sub-pixel according to an example can not include the color filter. In the transparent display apparatus 100 according to an embodiment of the disclosure, the white sub-pixel can be a first sub-pixel SP1, the red sub-pixel can be a second sub-pixel SP2, the green sub-pixel can be a third sub-pixel SP3, and the blue sub-pixel can be a fourth sub-pixel SP4.

[0046] When a gate-on signal is input from a gate line by using a thin film transistor, each of the sub-pixels SP provides a predetermined or selected current to the organic light emitting element according to a data voltage of a data line. For this, the light emitting part of each of the sub-pixels can emit light at a predetermined or selected brightness according to the predetermined or selected current. The structure of each of the sub-pixels SP will be described later with reference to FIGS. 1A and 1B. Figure 2 and Figure 3 The structure of each of the sub-pixels SP will be described later with reference to FIGS. 1A and 1B.

[0047] The non-display area NDA can be an area in which an image is not displayed, and can be a peripheral circuit area, a signal providing area, a non-active area, or a bezel area. The non-display area NDA can be configured to surround the display area DA. That is, the non-display area NDA can be disposed adjacent to or surrounding the display area DA in some cases.

[0048] The transparent display apparatus 100 according to one embodiment of the disclosure can include a gate driver GD disposed in the non-display area NDA.

[0049] The gate driver GD provides a gate-on signal to a gate line according to a gate control signal input from the timing controller 160. The gate driver GD can be formed on one side of the display area DA of the display panel, or above the non-display area NDA outside both sides of the display area DA, in a gate-in-panel (GIP) method as shown in FIG. 1C. Alternatively, the gate driver GD can be manufactured as a driving chip, packaged in a flexible film, and attached to one side of the display area DA of the display panel or the non-display area NDA outside both sides of the display area DA by a tape automated bonding (TAB) method. The gate driver GD according to one example can include a plurality of gate driving circuits (or GIP circuits) and a plurality of GIP lines. The GIP line according to one example can include a plurality of signal lines and a plurality of power lines. Figure 1 A plurality of gate drivers GD can be disposed on the left side of the display area DA (that is, a first non-display area) and the right side of the display area DA (that is, a second non-display area). According to one example, the plurality of gate drivers GD can be connected to a plurality of pixels P and a plurality of first signal lines SL1 for providing signals to the plurality of pixels P, respectively. As shown in FIG. 1D, the transparent display apparatus 100 according to one embodiment of the disclosure can further include second signal lines SL2 crossing the plurality of first signal lines SL1.

[0050] Figure 1 The plurality of first signal lines SL1 can extend in a first direction (X-axis direction). Each of the plurality of first signal lines SL1 can include at least one scan line. The first direction (X-axis direction) can refer to a direction parallel to the scan line.

[0051] The plurality of first signal lines SL1 can extend in a first direction (X-axis direction). Each of the plurality of first signal lines SL1 can include at least one scan line. The first direction (X-axis direction) can refer to a direction parallel to the scan line. ​

[0052] Hereinafter, when the first signal line SL1 includes a plurality of lines, one first signal line SL1 can refer to a signal line group including the plurality of lines. For example, when the first signal line SL1 includes two scan lines, one first signal line SL1 can refer to a signal line group including the two scan lines.

[0053] The plurality of second signal lines SL2 can extend in a second direction (Y-axis direction). The plurality of second signal lines SL2 can cross the plurality of first signal lines SL1. Each of the second signal lines SL2 can be connected to at least one pad of the plurality of pads provided in the pad area PA, a pixel power shorting bar VDD, or a common power shorting bar VSS. The pixel power shorting bar VDD and the common power shorting bar VSS can be provided in a third non-display area disposed to face the pad area PA based on the display area DA. The second direction (Y-axis direction) can be a direction parallel to the data line.

[0054] The plurality of second signal lines SL2 can include a pixel power line connected to the pixel power shorting bar VDD and a common power line connected to the common power shorting bar VSS. In an embodiment, each of the plurality of second signal lines SL2 can further include a first data line, a reference line, and a second data line.

[0055] Hereinafter, when the second signal line SL2 includes a plurality of lines, one second signal line SL2 can refer to a signal line group including the plurality of lines. For example, when the second signal line SL2 includes two data lines, a pixel power line, a common power line, and a reference line, one second signal line SL2 can refer to a signal line group including the two data lines, the pixel power line, the common power line, and the reference line.

[0056] As shown in FIG. 1A, the first signal line SL1 can be disposed to cross the second signal line SL2. For example, the first signal line SL1 can be disposed to cross the second signal line SL2 in the display area DA. The first signal line SL1 can be disposed to cross the second signal line SL2 in the pad area PA. The first signal line SL1 can be disposed to cross the second signal line SL2 in the third non-display area. Figure 2 As shown in FIG. 1A, the first transmission portion TR1 can be disposed between the first signal lines SL1 adjacent to each other. In addition, the first transmission portion TR1 can be disposed between the second signal lines SL2 adjacent to each other. That is, the first transmission portion TR1 can be surrounded by two first signal lines SL1 and two second signal lines SL2.

[0057] The pixel P can be disposed to overlap at least one of the first signal line SL1 and the second signal line SL2 to emit predetermined or selected light, thereby displaying an image. The emission area EA can correspond to an area in which light is emitted in the pixel P.

[0058] Each of the pixels P can include at least one of a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, or a fourth sub-pixel SP4. The first sub-pixel SP1 can be provided to include a first emission area EA1 for emitting white light, the second sub-pixel SP2 can be provided to include a second emission area EA2 for emitting red light, the third sub-pixel SP3 can be provided to include a third emission area EA3 for emitting green light, and the fourth sub-pixel SP4 can be provided to include a fourth emission area EA4 for emitting blue light, but they are not limited thereto. Each of the pixels P can include a sub-pixel that emits light of a color other than red, green, blue, and white. In addition, various modifications can be made to the arrangement order of the sub-pixels SP1, SP2, SP3, and SP4.

[0059] Hereinafter, for convenience of description, the first sub-pixel SP1 is a white sub-pixel for emitting white light, the second sub-pixel SP2 is a red sub-pixel for emitting red light, the third sub-pixel SP3 is a green sub-pixel for emitting green light, and the fourth sub-pixel SP4 is a blue sub-pixel for emitting blue light.

[0060] In the transparent display device 100 according to one embodiment of the disclosure, since the organic light emitting element is provided to emit white light, the first sub-pixel SP1 as a white sub-pixel can not include a color filter as shown in Figure 2 and Figure 3 On the other hand, the second sub-pixel SP2 can include a red color filter (or a first color filter) CF1 to emit red light, the third sub-pixel SP3 can include a green color filter (or a second color filter) CF2 to emit green light, and the fourth sub-pixel SP4 can include a blue color filter (or a third color filter) CF3 to emit blue light.

[0061] As shown in Figure 2As illustrated, the first sub-pixel SP1 can be disposed along a first direction (X-axis direction). At least a portion of the first sub-pixel SP1 can be disposed to overlap the first signal line SL1. The second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 can be adjacent to the first sub-pixel SP1 and can be arranged along a second direction (Y-axis direction). The second sub-pixel SP2 according to one example can be disposed to face the third sub-pixel SP3 and the fourth sub-pixel SP4, with the first signal line SL1 interposed between the second sub-pixel SP2 and the third sub-pixel SP3 and the fourth sub-pixel SP4. Each of the plurality of pixels P can include a first transmissive portion TR1 disposed adjacent to the first sub-pixel SP1 and the second sub-pixel SP2, and another first transmissive portion TR1 disposed adjacent to the first sub-pixel SP1 and the third sub-pixel SP3. That is, each of the plurality of pixels P can include four sub-pixels SP1, SP2, SP3, and SP4 and two first transmissive portions TR1, as illustrated in FIG. 1B. Figure 2 The plurality of pixels P can be divided in the first direction (X-axis direction) based on the second signal line SL2.

[0062] The first sub-pixel SP1 is disposed between the first transmissive portions TR1 while being adjacent to the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4, such that at least a portion of the first sub-pixel SP1 can overlap the first signal line SL1. As described above, since the first sub-pixel SP1 is a white sub-pixel disposed to emit white light, the first sub-pixel SP1 does not include a color filter unlike other sub-pixels. Thus, when external light is reflected toward the first signal line SL1, the first sub-pixel SP1 can have greater reflection visibility unlike other sub-pixels disposed with a color filter.

[0063] In the transparent display apparatus 100 according to one embodiment of the disclosure, the non-display area NDA can have a structure similar to that of the display area DA in order to reduce a visibility difference between the display area DA and the non-display area NDA. For example, as illustrated in FIG. 1C, the non-display area NDA can include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 can be disposed adjacent to the display area DA, and the second non-display area NDA2 can be disposed adjacent to the first non-display area NDA1. Figure 4As shown, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be disposed to overlap at least a portion of the GIP signal line GL (or the plurality of clock signal lines) disposed in the second direction (Y-axis direction) in the non-display area NDA. However, no color filter is disposed at a position corresponding to the first sub-pixel SP1 in the non-display area NDA, so as to reduce the visibility difference with the display area DA. Thus, since there is no color filter at the position corresponding to the first sub-pixel SP1 in the non-display area NDA, reflection visibility due to external light can greatly occur. When the first sub-pixel SP1 of the non-display area NDA has a structure different from that of the first sub-pixel SP1 of the display area DA, the difference in reflection visibility between the display area DA and the non-display area NDA can be great. In the transparent display device 100 according to one embodiment of the disclosure, the structure of the position corresponding to the first sub-pixel SP1 in the non-display area NDA is the same as or similar to that of the first sub-pixel SP1 in the display area DA, so that the difference in reflection visibility due to external light between the display area DA and the non-display area NDA can be reduced. In this case, the corresponding position can refer to a position in the non-display area NDA parallel to a position in the display area DA in which the first sub-pixel SP1 is disposed in the first direction (X-axis direction) or the second direction (Y-axis direction).

[0064] Hereinafter, a pixel P of the transparent display device 100 according to one embodiment of the disclosure will be described with reference to Figure 2 and Figure 3

[0065] Referring to Figure 2 and Figure 3 , the pixel P disposed in the display area DA can include a plurality of sub-pixels SP and a first transmissive portion TR1. As shown, Figure 2 the first transmissive portion TR1 can be disposed adjacent to at least a portion of the plurality of sub-pixels SP. Each of the plurality of sub-pixels SP can include a buffer layer BL disposed above the first substrate 110, to prevent or reduce moisture from penetrating into the thin film transistor 112.

[0066] In addition, each of the sub-pixels SP according to one embodiment of the disclosure can include an inorganic layer 111 disposed above an upper surface of the buffer layer BL, the inorganic layer including a gate insulating layer 111a, an interlayer insulating layer 111b, and a protective layer 111c; a planarization layer 113 disposed above the inorganic layer 111; a first electrode 114 disposed on the planarization layer 113; a bank 115; an organic light emitting layer 116; a second electrode 117; a capping layer 118; and an encapsulation layer 119.

[0067] ​The thin film transistor 112 for driving the sub-pixel SP can be disposed in the inorganic layer 111. The inorganic layer 111 can be denoted as the term circuit element layer. The buffer layer BL can be included in the inorganic layer 111 together with the gate insulating layer 111a, the interlayer insulating layer 111b, and the protective layer 111c. The first electrode 114, the organic light emitting layer 116, and the second electrode 117 can be included in the light emitting element.

[0068] The buffer layer BL can be formed between the first substrate 110 and the gate insulating layer 111a to protect the thin film transistor 112. The buffer layer BL can be disposed over the entire surface (or front surface) of the first substrate 110. The buffer layer BL can be used to prevent or reduce diffusion of materials contained in the first substrate 110 into the transistor layer during a high-temperature process of a manufacturing process of the thin film transistor. Alternatively, the buffer layer BL can be omitted as appropriate.

[0069] The thin film transistor 112 according to an example can include an active layer 112a, a gate 112b, a source 112c, and a drain 112d.

[0070] The active layer 112a can include a channel region, a drain region, and a source region formed in a thin film transistor region of a circuit region of the pixel P. The drain region and the source region can be spaced apart from each other with the channel region interposed therebetween.

[0071] The active layer 112a can include a semiconductor material based on any one of amorphous silicon, polycrystalline silicon, oxide, and organic material.

[0072] The gate insulating layer 111a can be formed over the channel region of the active layer 112a. As an example, the gate insulating layer 111a can be formed in an island shape only over the channel region of the active layer 112a, or can be formed over the entire front surface of the first substrate 110 or the buffer layer BL including the active layer 112a.

[0073] The gate 112b can be formed on the gate insulating layer 111a to overlap at least a portion of the channel region of the active layer 112a.

[0074] The interlayer insulating layer 111b can be formed over the gate 112b and the drain region and the source region of the active layer 112a. The interlayer insulating layer 111b can be formed in the circuit region and the entire light emitting region in which light is emitted to the pixel P. For example, the interlayer insulating layer 111b can be made of an inorganic material, but is not necessarily limited thereto.

[0075] The source 112c can be electrically connected to the source region of the active layer 112a through a source contact hole disposed in the interlayer insulating layer 111b overlapping at least a portion of the source region of the active layer 112a.

[0076] The drain 112d can be electrically connected to the drain region of the active layer 112a through a drain contact hole provided in an interlayer insulating layer 111b that overlaps with at least a portion of the drain region of the active layer 112a.

[0077] The drain 112d and source 112c can be made of the same conductive material, such as the same metal. For example, each of the drain 112d and source 112c can be made of a single metal layer, a single alloy layer, or a multilayer of two or more layers, with or without the same construction as the gate.

[0078] Additionally, the circuit region may also include a first switching thin-film transistor and a second switching thin-film transistor disposed together with the thin-film transistor 112, as well as a capacitor. Since each of the first and second switching thin-film transistors is disposed above the circuit region of pixel P to have the same structure as the thin-film transistor 112, its description will be omitted. The capacitor may be disposed in the overlapping region between the gate 112b and the source 112c of the thin-film transistor 112, wherein the gate 112b and the source 112c of the thin-film transistor 112 overlap each other, and at least a portion of the interlayer insulating layer 111b is interposed between the gate 112b and the source 112c.

[0079] In addition, to prevent or reduce the light-induced threshold voltage shift of the thin-film transistors disposed in the pixel region, the display panel or the first substrate 110 may further include a light-shielding layer (not shown) disposed below the active layer 112a of at least one of the thin-film transistors 112, the first switching thin-film transistor, or the second switching thin-film transistor. The light-shielding layer may be disposed between the first substrate 110 and the active layer 112a to block light incident on the active layer 112a through the first substrate 110, thereby reducing and / or minimizing the change in transistor threshold voltage caused by external light.

[0080] A protective layer 111c may be disposed above the first substrate 110 to cover the pixel area. The protective layer 111c covers the drain 112d and source 112c of the thin-film transistor 112, as well as the interlayer insulating layer 111b. The protective layer 111c may be formed throughout the circuit area and the light-emitting area. For example, the protective layer 111c may be represented as a passivation layer. The protective layer 111c may be omitted.

[0081] The planarization layer 113 can be formed over the first substrate 110 to cover the protective layer 111c. When the protective layer 111c is omitted, the planarization layer 113 can be disposed over the first substrate 110 to cover the circuit region. The planarization layer 113 can be formed in the entire circuit region and the light emitting region. In addition, the planarization layer 113 can be formed over other regions except for the pad region PA and the entire display region DA in the non-display region NDA. For example, the planarization layer 113 can include an extended portion (or an enlarged portion) extending or enlarged from the display region DA to other non-display region NDA except for the pad region PA. Accordingly, the planarization layer 113 can have a relatively wide size than that of the display region DA.

[0082] The planarization layer 113 according to an example can be formed to be relatively thick, and thus can provide a flat surface over the display region DA and the non-display region NDA. For example, the planarization layer 113 can be made of an organic material such as photo acryl, benzocyclobutene, polyimide, and fluororesin.

[0083] The first electrode 114 of the sub-pixel SP can be formed on the planarization layer 113. The first electrode 114 is connected to the drain or the source of the thin film transistor 112 through a contact hole passing through the planarization layer 113 and the protective layer 111c.

[0084] The first electrode 114 can be made of at least one of a transparent conductive material such as a metal material, a semi-transmissive conductive material such as a metal material, or a conductive material having high reflectivity such as a metal material.

[0085] When the transparent display apparatus 100 is provided in a top emission mode, the first electrode 114 can include a metal material having high reflectivity or a stacked structure of a metal material having high reflectivity and a transparent metal material. For example, the first electrode 114 can include a stacked structure of a metal material having high reflectivity such as aluminum and titanium (Ti / Al / Ti), a stacked structure of ITO and aluminum (ITO / Al / ITO), an Ag alloy, and a stacked structure of an Ag alloy and ITO (ITO / Ag alloy / ITO). The Ag alloy can be an alloy such as silver (Ag), palladium (Pd), and copper (Cu).

[0086] When the transparent display apparatus 100 is provided in a bottom emission mode, the first electrode 114 can include a transparent conductive material (TCO) such as ITO and IZO, which can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0087] In addition, the material constituting the first electrode 114 can include MoTi. The first electrode 114 can be an anode or a pixel electrode.

[0088] The bank 115 is a non-light emitting area in which light is not emitted, and can be disposed adjacent to or surrounding each of the light emitting areas (or light emitting portions) of the plurality of sub-pixels SP. That is, the bank 115 can divide (or define) each of the light emitting areas (or light emitting portions).

[0089] The bank 115 can be formed over the planarization layer 113 to cover edges of the first electrodes 114, thereby dividing (or defining) the light emitting areas (or light emitting portions) of the plurality of sub-pixels SP.

[0090] The bank 115 can be formed to cover edges of the first electrodes 114 of each of the sub-pixels SP and to expose a portion of each of the first electrodes 114. Accordingly, current is not concentrated at the end portions of each of the first electrodes 114 to avoid or reduce a problem of reduced light emission efficiency. The exposed portion of the first electrodes 114, which is not covered by the bank 115, can be the light emitting area (or light emitting portion).

[0091] The bank 115 can include an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin, but is not limited thereto.

[0092] The organic light emitting layer 116 is formed on the first electrodes 114 and the bank 115. When a voltage is applied to the first electrodes 114 and the second electrodes 117, holes and electrons move to the organic light emitting layer 116, respectively, and combine with each other in the organic light emitting layer 116 to emit light.

[0093] The organic light emitting layer 116 can be formed in the plurality of sub-pixels SP and formed as a common layer disposed over the bank 115. In this case, the organic light emitting layer 116 can be disposed in a series structure in which a plurality of light emitting layers (for example, a yellow-green light emitting layer and a blue light emitting layer) are stacked, and can emit white light when an electric field is formed between the first electrodes 114 and the second electrodes 117.

[0094] Color filters suitable for colors of the corresponding sub-pixels SP can be formed on the second substrate 120. For example, a red color filter CF1 can be disposed in a red sub-pixel, a green color filter CF2 can be disposed in a green sub-pixel, and a blue color filter CF3 can be disposed in a blue sub-pixel. Since the organic light emitting layer 116 emits white light, a white sub-pixel can not include a color filter.

[0095] The second electrode 117 is formed on the organic light emitting layer 116. The second electrode 117 can be a common layer commonly formed in the sub-pixels SP. The second electrode 117 can be made of a transparent metal material, a semi-transmissive metal material, or a metal material having high reflectivity.

[0096] When the transparent display apparatus 100 is set in a top emission mode, the second electrode 117 can include a transparent conductive material (TCO) such as ITO and IZO, which can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0097] When the transparent display apparatus 100 is set in a bottom emission mode, the second electrode 117 can include a metal material having high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, and a stacked structure of an Ag alloy and ITO (ITO / Ag alloy / ITO). The Ag alloy can be an alloy of silver (Ag), palladium (Pd), copper (Cu), or the like. The second electrode 117 can be a cathode.

[0098] The cover layer 118 can be formed on the second electrode 117, but can be omitted. When the cover layer 118 is formed, the cover layer 118 can be formed in the entire display area DA. In addition, as Figure 5 indicated, the cover layer 118 can be disposed up to the non-display area NDA.

[0099] The encapsulation layer 119 is formed on the cover layer 118. The encapsulation layer 119 serves to prevent or reduce penetration of oxygen or water into the organic light emitting layer 116 and the second electrode 117. To this end, the encapsulation layer 119 can include at least one inorganic layer.

[0100] In the transparent display apparatus 100 according to one embodiment of the disclosure, the encapsulation layer 119 can be disposed in the non-display area NDA as well as the display area DA. The encapsulation layer 119 according to one example can be disposed between the cover layer 118 and the second substrate 120.

[0101] Since the encapsulation layer 119 is disposed in the display area DA and extends up to the non-display area NDA, the encapsulation layer 119 can be in contact with a dam portion (not shown) at the outside of the display panel. Accordingly, the transparent display apparatus 100 according to one embodiment of the disclosure can effectively prevent or reduce penetration of moisture into the display area DA.

[0102] Referring back to Figure 3The color filter and black matrix BM can be disposed between the encapsulation layer 119 and the second substrate 120. As described above, since the organic light-emitting layer 116 emits white light, the white sub-pixel (i.e., the first sub-pixel SP1) may not include a color filter. On the other hand, in the second sub-pixel SP2, which is a red sub-pixel, the first color filter CF1 can be disposed between the encapsulation layer 119 and the second substrate 120.

[0103] like Figure 3 As shown, a black matrix BM can be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 to prevent or reduce color mixing between the first sub-pixel SP1 and the second sub-pixel SP2. The black matrix BM can be made of a black-based material and can be disposed in the non-light-emitting area NEA. According to an example, the black matrix BM is formed on the second substrate 120 such that at least a portion of it overlaps with the embankment 115, thereby reducing the cell gap between the organic light-emitting layer 116 and the second substrate 120 to prevent or reduce color mixing between sub-pixels.

[0104] like Figure 2 As shown, since at least a portion of the first sub-pixel SP1 overlaps with the first signal line SL1, therefore... Figure 3 As shown, the first signal line SL1 can be disposed between the buffer layer BL and the first substrate 110 in the first sub-pixel SP1. Therefore, at least a portion of the first signal line SL1 in the first sub-pixel SP1 can overlap with the gate 112b, source 112c, and drain 112d of the thin-film transistor 112. That is, below the planarization layer 113 of the first sub-pixel SP1, at least a portion of each of the gate 112b, source 112c, and drain 112d can overlap with the first signal line SL1. In this case, the first signal line SL1 can be a common power line VSSL connected to a common power shorting bar VSS. The first signal line SL1, gate 112b, and source 112c and drain 112d disposed in the first sub-pixel SP1 are disposed in the display area DA, and therefore can be referred to as the pixel metal layer.

[0105] As a result, in a transparent display device 100 according to one embodiment of the present disclosure, a first sub-pixel SP1 configured to emit white light can be provided such that at least three pixel metal layers overlap each other. Figure 2As shown, since the second sub-pixel SP2 does not overlap with the first signal line SL1, the number of pixel metal layers can be less than the number of pixel metal layers in the first sub-pixel SP1. Therefore, a difference in reflective visibility between the second sub-pixel SP2 and the first sub-pixel SP1 may occur. However, since the second sub-pixel SP2 and the first sub-pixel SP1 are configured to emit light with corresponding colors different from each other, and a first color filter CF1 is provided in the second sub-pixel SP2, the difference in reflective visibility between the second sub-pixel SP2 and the first sub-pixel SP1 due to the pixel metal layers is almost negligible. Therefore, in a transparent display device 100 according to an embodiment of this disclosure, no color filter is provided in the area of ​​the non-display area NDA corresponding to the first sub-pixel SP1 without a color filter (hereinafter referred to as "the first block portion BLK1"), and the same or similar lower structures are provided below the planarization layer 113 in the first sub-pixel and the first block portion, thereby reducing the difference in reflective visibility between the first sub-pixel SP1 and the first block portion BLK1.

[0106] Reference Figure 4 In a transparent display device 100 according to one embodiment of the present disclosure, the non-display area NDA may include a GIP portion GP. The GIP portion GP may have the same or similar structure as the pixel P of the display area DA, thereby reducing the visibility difference with the display area DA. According to one example, the GIP portion GP may include a first portion BLK1, a second portion BLK2, and a second transmissive portion TR2.

[0107] The first block portion BLK1 can refer to a region in which no color filter is disposed in the non-display area NDA (or gate driver GD), and can be disposed at a position corresponding to the first sub-pixel SP1. The first block portion BLK1 does not include a color filter, and thus can be expressed as a white block portion. The second block portion BLK2 can be disposed adjacent to the first block portion BLK1 in the non-display area NDA (or gate driver GD), and can refer to a region in which a color filter is disposed. The second block portion BLK2 can include a red block portion BLK2-1, a green block portion BLK2-2, and a blue block portion BLK2-3. The red block portion BLK2-1 can include a first color filter CF1, and the first color filter CF1 can overlap at least a portion of each of the GIP signal lines GL and / or the GIP circuit. The red block portion BLK2-1 can be disposed at a position corresponding to the second sub-pixel SP2. The green block portion BLK2-2 can include a second color filter CF2, and the second color filter CF2 can overlap at least a portion of each of the GIP signal lines GL and / or the GIP circuit. The green block portion BLK2-2 can be disposed at a position corresponding to the third sub-pixel SP3. The blue block portion BLK2-3 can include a third color filter CF3, and the third color filter CF3 can overlap at least a portion of each of the GIP signal lines GL and / or the GIP circuit. The blue block portion BLK2-3 can be disposed at a position corresponding to the fourth sub-pixel SP4. A second transmission portion TR2 of the non-display area NDA can be disposed at a position corresponding to the first transmission portion TR1 of the display area DA. Thus, the second transmission portion TR2 can be disposed adjacent to the first block portion BLK1 and the red block portion BLK2-1, and the first block portion BLK1 and the green block portion BLK2-2, respectively.

[0108] As Figure 4 indicated, the GIP portion GP of the non-display area NDA can be disposed the same as or similar to the pixel P of the display area DA. Thus, in the transparent display device 100 according to one embodiment of the disclosure, a visibility difference between the display area DA and the non-display area NDA can be reduced.

[0109] Since no color filter is disposed in the first block portion BLK1 disposed in the non-display area NDA, at least three metal layers can be disposed overlapping each other like the first sub-pixel SP1. The at least three metal layers disposed in the first block portion BLK1 are disposed in the non-display area NDA, and thus can be expressed as the term non-pixel metal layer.

[0110] Referring to Figure 4, the first block portion BLK1 can be disposed between the second block portions BLK2. In more detail, the first block portion BLK1 can be disposed to be longer in a first direction (X-axis direction), and can be disposed between the second block portions BLK2 adjacent to each other. In this case, the second block portions BLK2 can refer to the second block portions BLK2 of the two adjacent GIP portions GP. The second block portions BLK2 can be disposed to be longer in a second direction (Y-axis direction) crossing the first direction (X-axis direction). Accordingly, the first block portion BLK1 can be disposed in a bridge shape between the second block portions BLK2. As a result, the first block portion BLK1 and the second block portions BLK2 of the non-display area NDA can be disposed to be the same as or similar to each of the first sub-pixel SP1 and the second, third, and fourth sub-pixels SP2, SP3, and SP4 of the display area DA, and thus a visibility difference with the display area DA can be reduced. In this case, "the same as or similar to" can mean "the same as or similar to" in at least one of a size, a shape, or a stacked structure.

[0111] Referring to Figure 5 , the first block portion BLK1 can include a dummy pattern DMP disposed to be the same as or similar to the first sub-pixel SP1. The dummy pattern DMP according to one example can be disposed by stacking a plurality of metal layers (or non-pixel metal layers). Since the first block portion BLK1 does not have a color filter disposed therein, the dummy pattern DMP is disposed to be the same as or similar to a configuration of a pixel metal layer disposed in the first sub-pixel SP1, thereby reducing a difference in reflection visibility due to external light. For example, the first block portion BLK1 can be disposed to have a step difference the same as a step difference of the pixel metal layer disposed in the first sub-pixel SP1, thereby reducing a difference in reflection visibility due to external light.

[0112] The dummy pattern DMP according to one example can include a first metal layer DMP1 disposed on the substrate 110, a second metal layer DMP2 disposed above the first metal layer DMP1, and a third metal layer DMP3 disposed above the second metal layer DMP2. In this case, the first metal layer DMP1 can be disposed such that at least a portion thereof overlaps the second metal layer DMP2 and the third metal layer DMP3. Accordingly, as shown in FIG. 13, at least a portion of the dummy pattern DMP can be disposed to be the three overlapping metal layers (that is, the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3) under the planarization layer 113, and thus can be disposed to be similar to a structure of the first sub-pixel SP1 of the pixel 100 in which at least a portion of each of the first signal line SL1 (or a line LS in the same layer as the common voltage line), the gate 112b, and the source 112c (or the drain 112d) overlaps each other. Figure 5 Figure 3 The dummy pattern DMP according to one example can include a first metal layer DMP1 disposed on the substrate 110, a second metal layer DMP2 disposed above the first metal layer DMP1, and a third metal layer DMP3 disposed above the second metal layer DMP2. In this case, the first metal layer DMP1 can be disposed such that at least a portion thereof overlaps the second metal layer DMP2 and the third metal layer DMP3. Accordingly, as shown in FIG. 13, at least a portion of the dummy pattern DMP can be disposed to be the three overlapping metal layers (that is, the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3) under the planarization layer 113, and thus can be disposed to be similar to a structure of the first sub-pixel SP1 of the pixel 100 in which at least a portion of each of the first signal line SL1 (or a line LS in the same layer as the common voltage line), the gate 112b, and the source 112c (or the drain 112d) overlaps each other.​

[0113] Referring to Figure 3 and Figure 5 The first metal layer DMP1 can be disposed on the same layer as a common voltage line (or a first signal line SL1) disposed on the substrate 110. When the common voltage line is formed in the display area DA, in the non-display area NDA (or the gate driver GD), the first metal layer DMP1 can include the same material as that of the common voltage line. Accordingly, the first metal layer DMP1 disposed in the non-display area NDA can be disposed on the same layer as the common voltage line of the display area DA. For example, the first metal layer DMP1 can be disposed between the first substrate 110 and the buffer layer BL.

[0114] The second metal layer DMP2 can be disposed on the same layer as the gate 112b of the plurality of sub-pixels SP (more specifically, the first sub-pixel SP1). When the gate 112b is formed in the display area DA, in the non-display area NDA (or the gate driver GD), the second metal layer DMP2 can include the same material as that of the gate. Accordingly, the second metal layer DMP2 disposed in the non-display area NDA can be disposed on the same layer as the gate 112b of the display area DA. For example, the second metal layer DMP2 can be disposed between the interlayer insulating layer 111b and the buffer layer BL, but is not limited thereto. When at least a portion of the second metal layer DMP2 can overlap the first metal layer DMP1 and the third metal layer DMP3, the second metal layer DMP2 can be disposed between the interlayer insulating layer 111b and the gate insulating layer 111a.

[0115] The third metal layer DMP3 can be disposed on the same layer as the source 112c disposed above the gate 112b in the first sub-pixel SP1. When the source 112c is formed in the display area DA, in the non-display area NDA (or the gate driver GD), the third metal layer DMP3 can include the same material as that of the source. Accordingly, the third metal layer DMP3 disposed in the non-display area NDA can be formed on the same layer as the source 112c of the display area DA. For example, the third metal layer DMP3 can be disposed between the protective layer 111c and the interlayer insulating layer 111b. The third metal layer DMP3 disposed in the non-display area NDA can be disposed on the same layer as the drain 112d of the display area DA.

[0116] As a result, in the transparent display device 100 according to one embodiment of the present disclosure, at least three non-pixel metal layers disposed on the same layer as at least three pixel metal layers of the first sub-pixel SP1 are configured to overlap each other in the first block portion BLK1, thereby reducing the difference in reflective visibility between the first sub-pixel SP1 and the first block portion BLK1 due to external light. The red block portion BLK2-1, the green block portion BLK2-2, and the blue block portion BLK2-3 can be configured to be the same as or similar to the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4, respectively, and specifically, include color filters having the same color as the color filters of the second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4, thereby reducing the difference in reflective visibility due to external light.

[0117] Although Figure 5 The diagram shows that the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 have the same or similar widths in a planar shape, but the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 may have different widths than those shown in the diagram. Figure 3 The first signal line SL1 (or line LS, which is on the same layer as the common voltage line), gate 112b, and source 112c (or drain 112d) have the same structure.

[0118] The first part BLK1 may also include a planarization layer 113, a dummy electrode DE, a dummy embankment DB, a cover layer 118, and an encapsulation layer 119.

[0119] The planarization layer 113 can be disposed on the protective layer 111c in the first block portion BLK1. The planarization layer 113 of the first block portion BLK1 can be formed together with the planarization layer 113 of the first sub-pixel SP1 from the same material as the planarization layer 113 of the first sub-pixel SP1, and can therefore be configured to have the same thickness as the planarization layer 113 of the first sub-pixel SP1.

[0120] like Figure 4 As shown, since the second transmission portion TR2 is disposed in the second direction (Y-axis direction) of the first block portion BLK1, the two sides of the planarization layer 113 disposed in the first block portion BLK1 can be disposed adjacent to the second transmission portion TR2.

[0121] A dummy electrode DE can be disposed above the planarization layer 113 of the first portion BLK1. The dummy electrode DE can be disposed in a structure identical or similar to that of the first sub-pixel SP1, and thus formed in the non-display area NDA (or gating driver GD) to reduce visibility differences. The dummy electrode DE can be formed together with the first electrode 114 from the same material as the first electrode 114 disposed in the sub-pixel. According to one example, the dummy electrode DE can overlap with at least a portion of each of the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3.

[0122] exist Figure 5 In this configuration, since the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 are set in a flat shape, the lower surface contour of the planarization layer 113 covering the third metal layer DMP3 can be set to be flat. However, when the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 are aligned with... Figure 3 When the first signal line SL1 (or line LS disposed in the same layer as the common voltage line), gate 112b, and source 112c are arranged in the same form, the lower surface of the planarization layer 113 covering the third metal layer DMP3 can be configured with a non-flat profile. In this case, the planarization layer 113 disposed between the dummy electrode DE and the third metal layer DMP3 covers the non-flat shape of the third metal layer DMP3, so that the upper surface of the planarization layer 113 can be configured as flat. Since the dummy electrode DE is disposed above the planarized upper surface of the planarization layer 113, the dummy electrode DE can also be configured as flat. Since the flat dummy electrode DE is configured to overlap with at least a portion of the non-flat metal layer disposed below it, diffuse reflection of external light by the non-flat metal layer can be reduced or prevented. Therefore, the dummy electrode DE disposed in the first block portion BLK1 can reduce or prevent diffuse reflection of external light relative to the dummy pattern DMP.

[0123] Furthermore, since the non-display area NDA does not emit light, power (or voltage) need not be supplied to the dummy electrode DE. Therefore, the dummy electrode DE can be provided in a floating manner without being electrically connected to the third metal layer DMP3. Similarly, the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 are used to reduce the reflected brightness relative to the display area DA. Therefore, the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 can be provided without being electrically connected to the pad portion of the pad area PA or the drive circuit of the gate driver GD. As a result, in the transparent display device 100 according to one embodiment of the present disclosure, the dummy pattern DMP can be provided in the form of islands, that is, the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3.

[0124] The dummy embankment DB can be configured to cover the edge of the dummy electrode DE on the planarization layer 113. The dummy embankment DB can be configured with the same structure as the embankment 115 provided in the display area DA, thereby reducing the visibility difference with the display area DA. According to one example, the dummy embankment DB can be formed together with the embankment 115 from the same material as the embankment 115 of the display area DA.

[0125] Return to reference Figure 5 Since the non-display area NDA does not emit light, the organic light-emitting layer 116 and the second electrode 117 are not required. Therefore, as... Figure 5 As shown, the cover layer 118 may cover the upper surface of the protective layer 111c exposed in the second transmissive portion TR2, the side surface of the planarization layer 113, the upper surface and side surface of the dummy embankment DB, and the upper surface of the dummy electrode DE exposed between the dummy embankments DB, but is not limited thereto. The organic light-emitting layer 116 and the second electrode 117 may be disposed above the dummy electrode DE to reduce the visibility difference with the display area DA. Even though the organic light-emitting layer 116 and the second electrode 117 are disposed above the dummy electrode DE, no power supply (or voltage) is provided to the dummy electrode DE, so that the organic light-emitting layer 116 may not emit light.

[0126] The encapsulation layer 119 can be configured to cover the cover layer 118 disposed in the first block portion BLK1 and the cover layer 118 disposed in the second transmissive portion TR2 adjacent to the first block portion BLK1. The encapsulation layer 119 disposed in the non-display area NDA can include at least one inorganic layer and at least one organic layer. Therefore, the encapsulation layer 119 disposed in the non-display area NDA can prevent or reduce the penetration of moisture from the outside of the substrate 110 into the display area DA.

[0127] Further, the first block portion BLK1 can not include a color filter so as to reduce a visibility difference with the first sub-pixel SP1. Accordingly, the second substrate 120 can be disposed on the encapsulation layer 119 of the first block portion BLK1 so that the second substrate 120 can be in direct contact with the encapsulation layer 119 of the first block portion BLK1.

[0128] As a result, in the transparent display apparatus 100 according to one embodiment of the present disclosure, the structure of the GIP portion GP of the non-display area NDA is similar or identical to the structure of the pixel P of the display area DA, thereby it is possible to reduce a visibility difference with respect to a user between the display area DA and the non-display area NDA, and it is possible to reduce a difference in reflection visibility due to external light.

[0129] In more detail, in the first block portion BLK1, there is no color filter, and at least a portion of the three non-pixel metal layers is disposed under the planarization layer 113 to overlap each other so that the non-pixel metal layers are disposed in the same or similar structure (or step difference) as that of the first sub-pixel SP1, by which it is possible to reduce a visibility difference due to a naked eye and a difference in reflection visibility due to external light. Since the red block portion BLK2-1 of the second block portion BLK2 includes a red color filter CF1, it is possible to reduce a visibility difference due to a naked eye and a difference in reflection visibility due to external light with respect to the second sub-pixel SP2. Since the green block portion BLK2-2 of the second block portion BLK2 includes a green color filter CF2, it is possible to reduce a visibility difference due to a naked eye and a difference in reflection visibility due to external light with respect to the third sub-pixel SP3. Since the blue block portion BLK2-3 of the second block portion BLK2 includes a blue color filter CF3, it is possible to reduce a visibility difference due to a naked eye and a difference in reflection visibility due to external light with respect to the fourth sub-pixel SP4.

[0130] Figure 6 FIG. 1 is an example of a plan view illustrating a transparent display apparatus according to another embodiment of the present disclosure.

[0131] Referring to Figure 6 , the transparent display apparatus 100 according to another embodiment of the present disclosure is the same as the transparent display apparatus according to Figures 1 to 5 , except that the dummy pattern DMP serves as a line for providing a signal or a power supply to the display area DA. Accordingly, the same reference numerals are given to the same elements, and the following description will be based on the differences.

[0132] In the transparent display apparatus 100 according to Figure 1In the case of the transparent display apparatus according to Figure 5 the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 of the dummy pattern DMP are made of the same metal material as each of the common power line VSSL, the gate 112b, and the source 112c, and are insulated from each other, and thus can be used as a signal line or a power line.

[0133] On the other hand, in the case of the transparent display apparatus according to Figure 6 the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 of the dummy pattern DMP are made of the same metal material as each of the common power line VSSL, the gate 112b, and the source 112c, and are insulated from each other, and thus can be used as a signal line or a power line.

[0134] The dummy pattern DMP according to one example can transmit a signal for causing a plurality of pixels P to emit light, because at least one of the first metal layer DMP1, the second metal layer DMP2, or the third metal layer DMP3 is connected to a pad portion provided in the pad area PA or a gate line of the display area DA through the first line LIN1.

[0135] The dummy pattern DMP according to another example can transmit a power source (or voltage) for causing a plurality of pixels P to emit light, because at least one of the first metal layer DMP1, the second metal layer DMP2, or the third metal layer DMP3 is connected to a pixel power shorting bar VDD or a common power shorting bar VSS provided in the non-display area NDA through the second line LIN2.

[0136] As shown in FIG. 6, because a plurality of first block portions BLK1 are provided in the non-display area NDA, a plurality of dummy patterns DMP including at least three non-pixel metal layers can be provided. Because the dummy patterns DMP provided at different positions are used as signal lines or power lines, the number of additional lines can be reduced compared to a case in which the dummy patterns DMP are not used electrically, and thus the width of the non-display area NDA (or the bezel) can be reduced. In addition, because the non-pixel metal layers provided in the dummy patterns DMP have a width and an area greater than those of a general signal line or power line, problems such as signal attenuation or voltage drop can be improved. Figure 6

[0137] ​As a result, in the transparent display apparatus 100 according to the other embodiment of the present disclosure, at least one of the first metal layer DMP1, the second metal layer DMP2, or the third metal layer DMP3 of the first block portion BLK1 functions as a signal line and / or a power line, so that a bezel width can be reduced and problems such as signal attenuation or voltage drop can be improved.

[0138] Figure 7 is a plan view illustrating a portion C included in the transparent display apparatus according to the other embodiment of the present disclosure. Figure 1

[0139] Referring to Figure 7 , the transparent display apparatus 100 according to the other embodiment of the present disclosure is the same as the transparent display apparatus according to Figures 1 to 5 except that the plurality of GIP circuits GS including the dummy pattern DMP electrically connected to the buffer area BA are disposed adjacent to the display area DA. Thus, the same reference numerals are given to the same elements, and the following description will be based on the difference.

[0140] In the case of the transparent display apparatus according to Figure 1 , the first block portion BLK1 can be disposed to reduce a difference in visibility due to a naked eye and a difference in reflection visibility due to external light from the display area DA. Thus, the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 are not electrically connected to the pad portion of the pad area PA or the driving circuit of the gate driver GD, and can be disposed in the form of an island as shown in Figure 5 .

[0141] On the other hand, in the case of the transparent display apparatus according to Figure 7 , the dummy pattern DMP can be electrically connected to the GIP circuit GS disposed in the buffer area BA. For example, the GIP circuit GS disposed in the buffer area BA can be a gate signal generation circuit. Each of the plurality of dummy patterns DMP can be electrically connected to each of the plurality of GIP circuits GS disposed in the buffer area BA. In this case, the dummy pattern DMP connected to each of the plurality of GIP circuits GS can function as a capacitor. Since at least three non-pixel metal layers are disposed in the dummy pattern DMP to overlap each other, the dummy pattern DMP can function as a capacitor.

[0142] ​For example, the dummy pattern DMP can receive power through multiple power lines LN connected to the power supply and maintain the voltage supplied to multiple GIP circuits GS disposed in the buffer region BA within a frame. The multiple GIP circuits GS can be connected to the first signal line SL1 (or a gating line) to provide a gating signal. When the first metal layer DMP1 is used as the first capacitor electrode, the second metal layer DMP2 or the third metal layer DMP3 can be used as the second capacitor electrode. When the second metal layer DMP2 is used as the first capacitor electrode, the first metal layer DMP1 or the third metal layer DMP3 can be used as the second capacitor electrode. When the third metal layer DMP3 is used as the first capacitor electrode, the first metal layer DMP1 or the second metal layer DMP2 can be used as the second capacitor electrode.

[0143] As a result, in the transparent display device 100 according to another embodiment of this disclosure, the dummy pattern DMP is configured as a capacitor for the buffer area BA, thereby reducing the difference in visibility between the display area DA due to the user's naked eye and the difference in reflected visibility due to external light. Since the voltage supplied to the multiple GIP circuits GS can be maintained within a frame without additional capacitors, manufacturing costs can be reduced by omitting the additional capacitors.

[0144] Figure 8 This is an example of a transparent display device included in another variant of this disclosure. Figure 1 A schematic enlarged view of another example of part A in the diagram, and Figure 9 This is an example of a transparent display device included in other variations of this disclosure. Figure 1 A schematic enlarged view of another example of part B in the diagram.

[0145] Reference Figure 8 and Figure 9 Except for modifications to the structure of the pixel P in the display area DA and the structure of the GIP portion GP of the gating driver, the transparent display device 100 according to another variant of this disclosure and according to Figures 1 to 7 The transparent display device is the same. Therefore, the same reference numerals are given to the same elements, and the following description will be based on the differences.

[0146] According to Figure 1 In the case of a transparent display device, sub-pixels SP1, SP2, SP3, and SP4, which are included in a plurality of pixels P, are arranged in a T-shape along a first direction (X-axis direction), and two first transmissive portions TR1 are arranged on both sides of the first sub-pixel SP1. Each of the plurality of GIP portions GP arranged in the non-display area NDA (or gating driver GD) is configured to be the same as or similar to the plurality of pixels P.

[0147] For example, the gate driver GD can include a plurality of circuits and a plurality of lines, and the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be disposed in at least a portion of each of the plurality of circuits and / or the plurality of lines to overlap each other. The area in which the first color filter CF1 serving as a red color filter is disposed in the gate driver GD can be the red block portion BLK2-1, and the red block portion BLK2-1 can be disposed at a position corresponding to the second sub-pixel SP2. The area in which the second color filter CF2 serving as a green color filter is disposed in the gate driver GD can be the green block portion BLK2-2, and the green block portion BLK2-2 can be disposed at a position corresponding to the third sub-pixel SP3. The area in which the third color filter CF3 serving as a blue color filter is disposed in the gate driver GD can be the blue block portion BLK2-3, and the blue block portion BLK2-3 can be disposed at a position corresponding to the fourth sub-pixel SP4. The area in which no color filter is disposed between the plurality of circuits and / or between the plurality of lines in the gate driver GD can be the first block portion BLK1 (or the white block portion), and the white block portion BLK1 can be disposed at a position corresponding to the first sub-pixel SP1. Two second transmission portions TR2 can be disposed at both sides of the white block portion BLK1. As a result, the blocks BLK1, BLK2, BLK3, and BLK4 of the GIP portion GP can be disposed in a T shape in the first direction (X-axis direction), and the two second transmission portions TR2 can be disposed at both sides of the first block portion BLK1.

[0148] Accordingly, in the transparent display apparatus according to Figure 1 the structure of the pixels P of the display area DA is disposed to be the same as or similar to the GIP portion GP of the non-display area NDA (or the gate driver GD), so that it is possible to reduce the difference in visibility due to the naked eye of a user and the difference in reflection visibility due to external light.

[0149] In contrast, in the transparent display apparatus according to Figure 8In the case of the transparent display device of FIG. 1, the sub-pixels SP1, SP2, SP3, and SP4 included in the plurality of pixels P, respectively, can be arranged in a windmill shape or a "+" shape. Each of the plurality of pixels P includes four first transmissive portions TR1, and each of the first transmissive portions TR1 can be arranged adjacent to two sub-pixels. Since the first sub-pixel SP1 is arranged to emit white light, a color filter can not be arranged in the first sub-pixel SP1. Since the second sub-pixel SP2 is arranged to emit red light, a first color filter CF1, which is a red color filter, can be arranged in the second sub-pixel SP2. Since the third sub-pixel SP3 is arranged to emit green light, a second color filter CF2, which is a green color filter, can be arranged in the third sub-pixel SP3. Since the fourth sub-pixel SP4 is arranged to emit blue light, a third color filter CF3, which is a blue color filter, can be arranged in the fourth sub-pixel SP4.

[0150] As shown in FIG. 1, when the four pixels P are arranged adjacent to each other, one first transmissive portion TR1 of each of the pixels P can be arranged adjacent to another first transmissive portion TR1. That is, as shown in FIG. 1, the four first transmissive portions TR1 of the four pixels P can be arranged adjacent to each other at portions where the four pixels P are adjacent to each other. Since the four first transmissive portions TR1 are arranged adjacent to each other, the area of the transmissive portion can be greater than in the case where the first transmissive portions TR1 are alternately or randomly arranged, and thus the visibility of the background or image behind the display panel can be further improved. Figure 8 Figure 8 As shown in FIG. 1, when the four pixels P are arranged adjacent to each other, one first transmissive portion TR1 of each of the pixels P can be arranged adjacent to another first transmissive portion TR1. That is, as shown in FIG. 1, the four first transmissive portions TR1 of the four pixels P can be arranged adjacent to each other at portions where the four pixels P are adjacent to each other. Since the four first transmissive portions TR1 are arranged adjacent to each other, the area of the transmissive portion can be greater than in the case where the first transmissive portions TR1 are alternately or randomly arranged, and thus the visibility of the background or image behind the display panel can be further improved.

[0151] Referring to FIG. 1, each of the GIP portions GP included in the plurality of GIP portions GP arranged in the non-display area NDA (or the gate driver GD) can be arranged in the same or similar configuration as the plurality of pixels P as shown in FIG. 1. Figure 9 Figure 8 As shown in FIG. 1, when the four pixels P are arranged adjacent to each other, one first transmissive portion TR1 of each of the pixels P can be arranged adjacent to another first transmissive portion TR1. That is, as shown in FIG. 1, the four first transmissive portions TR1 of the four pixels P can be arranged adjacent to each other at portions where the four pixels P are adjacent to each other. Since the four first transmissive portions TR1 are arranged adjacent to each other, the area of the transmissive portion can be greater than in the case where the first transmissive portions TR1 are alternately or randomly arranged, and thus the visibility of the background or image behind the display panel can be further improved.

[0152] ​​For example, the gate driver GD can include a plurality of circuits and a plurality of lines, and the first color filter CF1, the second color filter CF2, and the third color filter CF3 can be disposed in at least a portion of each of the plurality of circuits and / or the plurality of lines to overlap each other. An area in which the first color filter CF1 as a red color filter is disposed in the gate driver GD can be a red block portion BLK2-1, and the red block portion BLK2-1 can be disposed at a position corresponding to the second sub-pixel SP2. An area in which the second color filter CF2 as a green color filter is disposed in the gate driver GD can be a green block portion BLK2-2, and the green block portion BLK2-2 can be disposed at a position corresponding to the third sub-pixel SP3. An area in which the third color filter CF3 as a blue color filter is disposed in the gate driver GD can be a blue block portion BLK2-3, and the blue block portion BLK2-3 can be disposed at a position corresponding to the fourth sub-pixel SP4. An area in which no color filter is disposed between the plurality of circuits and / or between the plurality of lines in the gate driver GD can be a first block portion BLK1 (or a white block portion), and the white block portion BLK1 can be disposed at a position corresponding to the first sub-pixel SP1. One GIP portion GP can include four second transmission portions TR2. One of the four second transmission portions TR2 can be disposed adjacent to the white block portion BLK1 and the red block portion BLK2-1. Another of the four second transmission portions TR2 can be disposed adjacent to the red block portion BLK2-1 and the blue block portion BLK2-3. Still another of the four second transmission portions TR2 can be disposed adjacent to the blue block portion BLK2-3 and the green block portion BLK2-2. The remaining one of the four second transmission portions TR2 can be disposed adjacent to the green block portion BLK2-2 and the white block portion BLK1. As a result, the blocks BLK1, BLK2, BLK3, and BLK4 of the GIP portion GP can be disposed in a wind wheel shape or a "+" shape, and the four second transmission portions TR2 can be disposed adjacent to two block portions.

[0153] Further, in the transparent display apparatus 100 according to Figure 8 the dummy pattern DMP of the display apparatus according to Figure 1 is the same as the dummy pattern DMP of the display apparatus according to

[0154] As a result, in the transparent display device 100 according to another modified embodiment of the disclosure, the pixel P of the display area DA and the GIP portion GP of the non-display area NDA (or the gate driver GD) have the same or similar structure in which four second transmission portions TR2 and a block portion having a wind wheel shape or a "+" shape are provided, and thus it is possible to reduce a difference in reflection visibility due to a visibility difference of a naked eye of a user and a difference in reflection visibility due to external light.

[0155] According to the disclosure, the following advantageous effects can be obtained.

[0156] In the disclosure, the structure of the GIP portion of the non-display area is set to be the same as or similar to the structure of the pixel of the display area, and thus it is possible to reduce a difference in reflection visibility between the display area and the non-display area.

[0157] Further, in the disclosure, the structure of the GIP portion of the non-display area is set to be similar to the structure of the pixel of the display area, and the GIP portion of the non-display area can be used as a capacitor or a wire.

[0158] It will be apparent to those skilled in the art that the above-described disclosure is not limited by the embodiments and drawings described above, and various substitutions, modifications and variations of the disclosure can be made without departing from the spirit or scope of the disclosure. Therefore, the scope of the disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope and equivalent concepts of the claims are intended to fall within the scope of the disclosure.

[0159] Cross Reference to Related Applications

[0160] This patent application claims the benefit of Korean Patent Application No. 10-2021-0183828, filed December 21, 2021, which is incorporated by reference herein as if fully set forth in its entirety herein.

Claims

1. A transparent display device, the transparent display device comprising: A substrate having a display area and a non-display area near the display area, wherein a plurality of pixels having a first transmissive portion and a plurality of sub-pixels are provided in the display area; as well as Multiple in-panel gated driver (GIP) portions are disposed above the substrate in the non-display area. Each GIP portion includes a second transmissive portion and multiple block portions. The plurality of sub-pixels includes a first sub-pixel configured to emit white light, the first sub-pixel having a stacked structure different from that of the other sub-pixels emitting light of a different color than the white light. The plurality of block portions includes a first block portion disposed at a position corresponding to the first sub-pixel, and The first block portion includes a dummy pattern set in the stacked structure to be the same as or similar to the first sub-pixel.

2. The transparent display device according to claim 1, wherein, The first section does not include color filters.

3. The transparent display device according to claim 1, wherein, The plurality of block portions also include a plurality of second block portions arranged adjacent to the first block portion, and The first block is disposed between the second block.

4. The transparent display device according to claim 3, wherein, The first block is positioned along a first direction, and The second block is positioned along a second direction that intersects with the first direction.

5. The transparent display device according to claim 4, wherein, The plurality of sub-pixels also includes a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The plurality of second blocks also include red block blocks, green block blocks, and blue block blocks. The red block is positioned at the location corresponding to the second sub-pixel. The green block is positioned at a location corresponding to the third sub-pixel, and The blue block is positioned at the location corresponding to the fourth sub-pixel.

6. The transparent display device according to claim 1, wherein, The dummy pattern is configured as multiple stacked conductive layers.

7. The transparent display device according to claim 6, wherein, The virtual pattern includes: A first conductive layer is disposed above the substrate; A second conductive layer, wherein the second conductive layer is disposed above the first conductive layer; and A third conductive layer is disposed above the second conductive layer, and The first conductive layer overlaps at least partially with the second and third conductive layers.

8. The transparent display device according to claim 7, wherein, The first conductive layer and the common voltage line disposed above the substrate are disposed on the same layer. The second conductive layer and the gate disposed in the plurality of sub-pixels are disposed on the same layer, and The third conductive layer is formed on the same layer as the source electrode disposed above the gate.

9. The transparent display device according to claim 7, wherein, At least one of the first conductive layer, the second conductive layer, or the third conductive layer serves as a line for providing signals or power to the display area.

10. The transparent display device according to claim 1, wherein, The non-display area includes a buffer area configured adjacent to the display area and comprising multiple GIP circuits, and The dummy pattern is electrically connected to the GIP circuit.

11. The transparent display device according to claim 10, wherein, The dummy pattern is used as a capacitor.

12. A transparent display device, the transparent display device comprising: A substrate having a display area and a non-display area near the display area, wherein a plurality of pixels having a first transmissive portion and a plurality of sub-pixels are provided in the display area; as well as Multiple in-panel gated driver (GIP) portions are disposed above the substrate in the non-display area. Each GIP portion includes a second transmissive portion and multiple block portions. The plurality of sub-pixels includes a first sub-pixel, in which at least three pixel conductive layers are arranged to overlap each other. The first sub-pixel is configured to emit white light and has a stacked structure different from that of the other sub-pixels that emit light of a different color than the white light. The plurality of block portions includes a first block portion disposed at a position corresponding to the first sub-pixel, and The first block includes at least three non-pixel conductive layers, which are disposed on the same layer as the at least three pixel conductive layers and are arranged to overlap each other.

13. The transparent display device according to claim 12, wherein, The at least three non-pixel conductive layers of the first block portion include: A first conductive layer is disposed on the same layer as a common voltage line disposed above the substrate. A second conductive layer is disposed above the first conductive layer and on the same layer as the gates disposed in the plurality of sub-pixels; and A third conductive layer is disposed above the second conductive layer and is disposed on the same layer as the source electrode disposed above the gate.

14. The transparent display device according to claim 12, wherein, At least one of the non-pixel conductive layers in the first block portion is used as a line for providing signals or power to the display area.

15. The transparent display device according to claim 12, wherein, The non-display area includes a buffer area configured adjacent to the display area and comprising multiple GIP circuits, and At least one of the non-pixel conductive layers is electrically connected to the GIP circuit.

16. The transparent display device according to claim 15, wherein, The non-pixel conductive layer is used as a capacitor.

17. A transparent display device, the transparent display device comprising: A substrate, the substrate including a display area and a non-display area adjacent to the display area; Multiple pixels are disposed in the display area, each pixel including a first transmissive portion and multiple sub-pixels, and the multiple pixels including at least one sub-pixel configured to emit white light, the at least one sub-pixel having a stacked structure different from other sub-pixels emitting light of a different color than the white light; as well as Multiple in-panel gating driver GIP portions are disposed in the non-display area. Each GIP portion includes a second transmissive portion and multiple block portions, the multiple block portions including a first block portion disposed at a position corresponding to the at least one sub-pixel. in, The display area includes a common voltage line. At least one of the plurality of sub-pixels includes a transistor, wherein the gate and source or drain of the transistor overlap with the common voltage line, and The plurality of block portions include a dummy pattern having a first conductive layer, a second conductive layer and a third conductive layer, the dummy pattern being located in the first block portion, the first conductive layer being in the same layer as the common voltage line, the second conductive layer being in the same layer as the gate, the third conductive layer being in the same layer as at least one of the source or the drain, and the second conductive layer and the third conductive layer overlapping the first conductive layer.

18. The transparent display device according to claim 17, wherein, The plurality of block portions further include a plurality of second block portions, wherein the first block portion is disposed along a first direction, and each of the plurality of second block portions is disposed along a second direction intersecting the first direction.

19. The transparent display device according to claim 17, wherein, The first conductive layer, the second conductive layer, and the third conductive layer overlap each other.

20. The transparent display device according to claim 19, wherein, The dummy pattern includes a buffer layer located between the first conductive layer and the second conductive layer.

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