A display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a substrate, a plurality of pixel circuits and a plurality of light emitting elements on one side of the substrate. In the pixel circuit, the first electrode of the first transistor is electrically connected with a data signal line; the second electrode of the first transistor is electrically connected with the gate electrode of the second transistor; the first electrode of the second transistor is electrically connected with a power signal line; the first electrode of the third transistor is electrically connected with a reset signal line; the second electrode of the second transistor and the second electrode of the third transistor are both electrically connected with the light emitting element; the channel region of the first transistor and the channel region of the second transistor are arranged along a first direction; the channel region of the second transistor and the channel region of the third transistor are arranged along a second direction; and the first direction and the second direction are both perpendicular to the arrangement direction of the pixel circuit. The above technical scheme can reduce the area occupied by the pixel circuit, improve the resolution of the display panel, and meet the pixel demand of high resolution.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, people have higher and higher requirements for display devices. For example, display products such as organic electroluminescence display (OLED) and liquid crystal display (LCD) are widely used in near-eye fields such as virtual reality (VR) and augmented reality (AR) due to their characteristics of being thin, light-emitting, self-illuminating, and having fast response speed.

[0003] Due to the unique optical path structure of displays used in near-eye applications, these products often require high resolution (i.e., pixel density units (Pixels Per Inch, PPI)). However, because the pixel circuitry of display devices is relatively complex and requires a large layout space, it is difficult to meet the pixel requirements of high PPI display devices under the current limitations of manufacturing technology. Summary of the Invention

[0004] The present invention provides a display panel and a display device to reduce the area occupied by pixel circuits and improve the resolution of the display device.

[0005] According to one aspect of the present invention, a display panel is provided, comprising: a substrate, a plurality of pixel circuits located on one side of the substrate, and a plurality of light-emitting elements located on the side of the pixel circuits away from the substrate;

[0006] The pixel circuit includes a first transistor, a second transistor, and a third transistor; the first terminal of the first transistor is electrically connected to the data signal line; the second terminal of the first transistor is electrically connected to the gate of the second transistor; the first terminal of the second transistor is electrically connected to the power signal line; the first terminal of the third transistor is electrically connected to the reset signal line; and the second terminals of both the second and third transistors are electrically connected to the light-emitting element.

[0007] The channel regions of the first transistor and the second transistor are arranged along a first direction; the channel regions of the second transistor and the third transistor are arranged along a second direction; the first direction and the second direction intersect.

[0008] Both the first and second directions are parallel to the plane of the substrate, and both the first and second directions intersect the arrangement direction of the pixel circuit.

[0009] According to another aspect of the present invention, a display device is provided, including the above-described display panel.

[0010] The technical solution of this invention, by setting a first transistor to receive data signals and setting a second and a third transistor to transmit power signals and reset signals to the anode of the light-emitting element at different stages, achieves the control of the light-emitting element, which can reduce the number of transistors in the pixel circuit, thereby reducing the area occupied by the pixel circuit. Furthermore, by setting the channel regions of the first transistor and the second transistor, and the channel regions of the second transistor and the third transistor, respectively, to be arranged in two directions different from the pixel circuit arrangement direction, and the connecting lines between the transistors form a triangle, so that one of the pixel circuit transistors is located outside the straight line containing the other two transistors, the length of the pixel circuit in the straight line containing the other two transistors is reduced. In addition, the length of the pixel circuit in the arrangement direction can also be reduced, thereby reducing the area occupied by the pixel circuit, improving the resolution of the display panel, and meeting the requirements of high-resolution pixels.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the circuit structure of a pixel circuit in the prior art;

[0014] Figure 2 This is a schematic diagram of the layout structure of a display panel in the prior art;

[0015] Figure 3 This is a schematic diagram of the film layer structure of a display panel provided in an embodiment of the present invention;

[0016] Figure 4 This is a schematic diagram of the layout structure of a display panel provided in an embodiment of the present invention;

[0017] Figure 5 This is a schematic diagram of the layout structure of a pixel circuit provided in an embodiment of the present invention;

[0018] Figure 6This is a schematic diagram of the layout structure of a first semiconductor layer and a second semiconductor layer provided in an embodiment of the present invention;

[0019] Figure 7 This is a schematic diagram of the layout structure of a first transistor, a second transistor, and a third transistor provided in an embodiment of the present invention;

[0020] Figure 8 This is a schematic diagram of the layout structure of a first semiconductor layer and a first gate layer provided in an embodiment of the invention;

[0021] Figure 9 This is a schematic diagram of the layout structure of another first transistor, second transistor, and third transistor provided in an embodiment of the present invention;

[0022] Figure 10 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0023] Figure 11 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0024] Figure 12 This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention;

[0025] Figure 13 This is a schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present invention;

[0026] Figure 14 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0027] Figure 15 This is a schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present invention;

[0028] Figure 16 This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention;

[0029] Figure 17 This is a schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present invention;

[0030] Figure 18 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0031] Figure 19 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention;

[0032] Figure 20 This is a schematic diagram of the layout structure of a first pixel circuit and a second pixel circuit provided in an embodiment of the present invention;

[0033] Figure 21 This is a schematic diagram of the structure of a first semiconductor layer provided in an embodiment of the present invention;

[0034] Figure 22 This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention;

[0035] Figure 23 This is a schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present invention;

[0036] Figure 24 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of the present invention;

[0037] Figure 25 This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention;

[0038] Figure 26 This is a schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present invention;

[0039] Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0040] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0042] To reduce the area occupied by pixel circuits and improve the resolution of display devices, existing technologies have proposed a 3T1C pixel circuit, such as... Figure 1As shown, the 3T1C pixel circuit 01 includes a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor C. The second electrode of the first transistor T1 and the gate of the second transistor T2 are electrically connected to a first node N1. The second electrodes of the second transistor T2 and the third transistor T3 are electrically connected to a second node N2. The second node N2 is electrically connected to the anode of the light-emitting element LED, and the cathode of the light-emitting element LED is electrically connected to the second power line PVSS. By employing external compensation, the number of transistors is reduced, thereby simplifying the structure of the pixel circuit and reducing the area occupied by the pixel circuit.

[0043] Figure 2 This is a schematic diagram of the layout structure of a display panel in the prior art, for reference. Figure 2 The display panel 01 includes an array of pixel circuits 01. The second transistor T2 and the third transistor T3 are located in the same direction as the first transistor T1. The first transistor T1, the second transistor T2, and the third transistor T3 are arranged sequentially along the vertical direction, and the line connecting their positions is a straight line. The second electrode of the first transistor T1 and the gate of the second transistor T2 are connected through a bridge via, which is the first node N1. The second electrode of the second transistor T2 and the second electrode of the third transistor T3 are connected through an active layer, where a via is provided for connecting the light-emitting element LED. The second node is N2; the first scan signal line Scan1 is electrically connected to the gate of the first transistor T1, and the second scan signal line Scan2 is electrically connected to the gate of the third transistor T3. The first scan signal line Scan1 and the second scan signal line Scan2 are arranged on the same layer and both extend in the lateral direction. Pixel circuits located in the same row can share the first scan signal line Scan1 and the second scan signal line Scan2. Pixel circuits located in the same row can also share the reset signal line VINT. The reset signal line VINT extends in the same direction as the first scan signal line Scan1 and the second scan signal line Scan2, both extending in the lateral direction.

[0044] Although existing pixel circuits have reduced the area occupied by pixel circuits by reducing the number of transistors, sharing some traces, and compressing key dimensions, making the pixel density of display panels approach or even reach 1000 PPI, at least 1500 PPI or even 2000 PPI is required for applications such as VR and other near-eye displays. Traditional stacking methods are difficult to meet the high-resolution pixel requirements.

[0045] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, comprising: a substrate, a plurality of pixel circuits located on one side of the substrate, and a plurality of light-emitting elements located on the side of the pixel circuits away from the substrate; the pixel circuits include a first transistor, a second transistor, and a third transistor; the first electrode of the first transistor is electrically connected to a data signal line; the second electrode of the first transistor is electrically connected to the gate of the second transistor; the first electrode of the second transistor is electrically connected to a power signal line; the first electrode of the third transistor is electrically connected to a reset signal line; and the second electrodes of both the second and third transistors are electrically connected to the light-emitting elements.

[0046] In the pixel circuit, the channel regions of the first transistor and the second transistor are arranged along a first direction; the channel regions of the second transistor and the third transistor are arranged along a second direction; the first direction and the second direction intersect; both the first direction and the second direction are parallel to the plane of the substrate, and both the first direction and the second direction intersect with the arrangement direction of the pixel circuit.

[0047] By employing the above technical solution, by setting a first transistor to receive data signals and setting a second and third transistor to transmit power signals and reset signals to the anode of the light-emitting element at different stages, the light-emitting element can be controlled. This reduces the number of transistors in the pixel circuit, thereby reducing the area occupied by the pixel circuit. Furthermore, by arranging the channel regions of the first transistor and the second transistor, and the channel regions of the second transistor and the third transistor, respectively, along two directions different from the pixel circuit arrangement direction, and the connecting lines between the transistors forming a triangle, one of the pixel circuit transistors is located outside the straight line containing the other two transistors. This reduces the length of the pixel circuit in the direction containing the other two transistors. In addition, the length of the pixel circuit in the arrangement direction can also be reduced, thereby reducing the area occupied by the pixel circuit, improving the resolution of the display panel, and meeting the requirements of high-resolution pixels.

[0048] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0049] Figure 3 This is a schematic diagram of the film layer structure of a display panel according to an embodiment of the present invention. (Reference) Figure 3The display panel 04 includes a substrate 10, a plurality of pixel circuits 03 located on one side of the substrate 10, and a plurality of light-emitting elements 05 located on the side of the pixel circuits 03 away from the substrate 10. The pixel circuits 03 include a first transistor T1, a second transistor T2, and a third transistor T3. The first terminal T11 of the first transistor T1 is electrically connected to the data signal line VDATA. The second terminal T12 of the first transistor T1 is electrically connected to the gate T23 of the second transistor T2. The first terminal T21 of the second transistor T2 is electrically connected to the power signal line PVDD. The first terminal T31 of the third transistor T3 is electrically connected to the reset signal line VINT. The second terminals T22 of the second transistor T2 and T32 of the third transistor T3 are both electrically connected to the light-emitting elements 05.

[0050] Figure 4 This is a schematic diagram of the layout structure of a display panel provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of the layout structure of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 4 and Figure 5 In the pixel circuit 03, the channel region T01 of the first transistor T1 and the channel region T02 of the second transistor T2 are arranged along the first direction M; the channel region T02 of the second transistor T2 and the channel region T03 of the third transistor T3 are arranged along the second direction N; the first direction M and the second direction N intersect; both the first direction M and the second direction N are parallel to the plane where the substrate 10 is located, and both the first direction M and the second direction N intersect the arrangement direction of the pixel circuit 03.

[0051] The substrate 10 can be transparent, semi-transparent, or opaque. The substrate 10 can be a rigid substrate, such as a glass substrate or a silicon substrate. The substrate 10 can also be a flexible substrate, such as a flexible resin material or a polymer with a thin layer of material. Specific materials may include polyimide (PI), polyethylene terephthalate (PET), or polyethylene naphthalate (PEN).

[0052] In an optional embodiment, the substrate 10 may further include a buffer layer 11, which may include a multilayer inorganic and organic layer stacked structure to block oxygen and moisture, prevent moisture or impurities from diffusing through the substrate 10, and provide a flat surface on the upper surface of the substrate 10.

[0053] In this embodiment of the invention, the active layer of the transistor includes a channel region overlapping the gate in a direction perpendicular to the plane of the substrate, and a source region and a drain region doped with impurities, which are respectively the first and second electrodes of the transistor, or the second electrode and the first electrode. In an optional embodiment, the active layer of the transistor may include a silicon semiconductor material, such as polycrystalline silicon or amorphous silicon; the active layer of the transistor may also include an oxide semiconductor material. The light-emitting element 05 electrically connected to the pixel circuit 03 includes, but is not limited to, OLED, Mini LED and Micro OLED, and the light-emitting element 05 includes an anode 051, a light-emitting layer 052 and a cathode (the cathode is not shown in the figure).

[0054] Specifically, the location of the transistor is taken as the centroid of the channel region, with reference to... Figure 4 and Figure 5 The centroid of the channel region T01 of the first transistor T1 is the location of the first transistor T1; the centroid of the channel region T02 of the second transistor T2 is the location of the second transistor T2; and the centroid of the channel region T03 of the third transistor T3 is the location of the third transistor T3. The first transistor T1 and the third transistor T3 are located in different directions from the second transistor T2, and the second transistor T2 and the third transistor T3 are located in different directions from the first transistor T1. That is, the line connecting the locations of the first transistor T1, the second transistor T2, and the third transistor T3 is a broken line. The first transistor T1, the second transistor T2, and the third transistor T3 are not arranged on the same straight line; a maximum of two transistors can be arranged on each straight line simultaneously.

[0055] For example, continue to refer to Figure 4 and Figure 5 The pixel circuit 03 extends along both the third direction X and the fourth direction Y. Both the third direction X and the fourth direction Y are parallel to the plane containing the substrate 10 and intersect. In the direction perpendicular to the plane containing the substrate 10, the pixel circuit 03 is rectangular or rhomboid. The pixel circuit 03 is the smallest repeating unit of the circuit structure located in the display area of ​​the display panel 04. In an optional embodiment, the third direction X and the fourth direction Y are perpendicular, and the pixel circuit 03 is rectangular. The first transistor T1 and the second transistor T2 can be arranged along one of the diagonal directions of the pixel circuit 03, and the second transistor T2 and the third transistor T3 can be arranged along the other diagonal direction.

[0056] Taking the pixel circuit 03 as a rectangle as an example, the length L1 of the pixel circuit 03 in the third direction X and the length L2 of the pixel circuit 03 in the fourth direction Y are both smaller than the length of the diagonal of the pixel circuit 03. By setting the first transistor T1 and the second transistor T2 in one diagonal direction and setting the second transistor T2 and the third transistor T3 in the other diagonal direction, the length L1 of the pixel circuit 03 in the third direction X and the length L2 of the pixel circuit 03 in the fourth direction Y can be reduced, thereby reducing the area occupied by the pixel circuit 03 and improving the resolution of the display panel 04.

[0057] It should be noted that the pixel circuit can also be irregularly shaped in the direction perpendicular to the plane of the substrate. The figure only illustrates, exemplarily, the case where the pixel circuit is rectangular in the direction perpendicular to the plane of the substrate. This embodiment of the invention does not specifically limit the shape of the area occupied by the pixel circuit. The channel types of the first transistor, the second transistor, and the third transistor in the pixel circuit can all be P-type, all be N-type, or partially P-type and partially N-type. This embodiment of the invention also does not specifically limit the channel type of the transistors in the pixel circuit.

[0058] In summary, the embodiments of the present invention, by setting a first transistor to receive data signals and setting a second and a third transistor to transmit power signals and reset signals to the anode of the light-emitting element at different stages, achieve the control of the light-emitting element, thereby reducing the number of transistors in the pixel circuit and thus reducing the area occupied by the pixel circuit. Furthermore, the embodiments of the present invention, by setting the channel regions of the first transistor and the second transistor, and the channel regions of the second transistor and the third transistor, respectively, to be arranged in two directions different from the pixel circuit arrangement direction, with the connecting lines between the transistors forming a triangle, so that one of the pixel circuit transistors is located outside the straight line containing the other two transistors, reduces the length of the pixel circuit in the direction containing the other two transistors. In addition, it can also reduce the length of the pixel circuit in the arrangement direction, thereby reducing the area occupied by the pixel circuit, improving the resolution of the display panel, and meeting the requirements of high-resolution pixels.

[0059] In an alternative embodiment, reference continues. Figure 4 and Figure 5 , 0.9≤L1 / L2≤1.1.

[0060] For example, the length L1 of the pixel circuit 03 in the third direction X can be obtained by dividing the length of all pixel circuits 03 in the third direction X in the display panel 04 by the number of pixel circuits 03 arranged in the third direction X. Similarly, the length L2 of the pixel circuit 03 in the fourth direction Y can be obtained by dividing the length of all pixel circuits 03 in the fourth direction Y in the display panel 04 by the number of pixel circuits 03 arranged in the fourth direction Y. The lengths L1 and L2 of the pixel circuit 03 in the third direction X and the fourth direction Y are approximately equal, with a length difference of less than or equal to 1 μm, which is beneficial for uniform display and improves the display effect of the display panel.

[0061] Optionally, the length L1 of the pixel circuit in the third direction can be in the range of 7μm≤L1≤9μm; the length L2 of the pixel circuit in the fourth direction can be in the range of 7μm≤L2≤9μm. This satisfies the high-resolution pixel requirements in the near-eye display field.

[0062] In order to achieve the aforementioned high resolution effect, and to ensure display quality while maintaining high resolution, the embodiments of the present invention also propose many setting methods.

[0063] In an optional embodiment, in the pixel circuit 03, some transistors may include silicon semiconductor materials, and other thin-film transistors (TFTs) may include oxide semiconductor materials, for example, the active layer of the first transistor T1 is an oxide semiconductor active layer, and the active layer of the second transistor T2 is a silicon active layer.

[0064] For example, the active layer of the first transistor T1 can be fabricated using metal oxide materials such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and indium zinc aluminum oxide (IAZO), which can reduce the leakage current of the first transistor T1 and maintain the stability of the potential of the first node N1. The second transistor T2 can be fabricated using polysilicon technology such as low-temperature polysilicon (LTPS), which can increase the charging speed of the second transistor T2 and improve the response speed of the pixel circuit 03. In addition, the first transistor T2 and the third transistor T3 can be configured as a dual-gate structure. For example, a second bottom gate T24 can be set on the side of the active layer of the second transistor T2 away from its gate T23, and a third bottom gate T34 can be set on the side of the active layer of the third transistor T3 away from its gate T33. Figure 3 As shown, this can improve the control capabilities of the second transistor T2 and the third transistor T3 over the channel regions T02 and T03, thereby improving the working stability and reliability of the pixel circuit T03.

[0065] Optionally, in a direction perpendicular to the plane of the substrate 10, the first transistor T1 and the second transistor T2 at least partially overlap.

[0066] For example, to facilitate understanding, Figure 6 This is a schematic diagram of the layout structure of a first semiconductor layer and a second semiconductor layer provided in an embodiment of the present invention. (Refer to...) Figure 3 and Figure 6 The first transistor T1 and the second transistor T2 are located on different layers. The display panel 04 includes a first semiconductor layer 21 located on one side of the substrate 10 and a second semiconductor layer 22 located on the side of the first semiconductor layer 21 away from the substrate 10; the first semiconductor layer 21 includes the active layer of the second transistor T2, and the second semiconductor layer 22 includes the active layer of the first transistor T1. In the direction perpendicular to the plane of the substrate 10, the active layers of the first transistor T1 and the second transistor T2 partially overlap, which can reduce the occupied area of ​​the active layers of the transistors in the pixel circuit 03, thereby reducing the occupied area of ​​the transistors in the pixel circuit 03, and thus increasing the number of pixel circuits set per unit area, which is beneficial to high resolution.

[0067] Furthermore, the active layer of the third transistor T3 is connected to the active layer of the second transistor T2 into a single structure, and the first semiconductor layer 21 includes the active layer of the third transistor T3. On the one hand, this reduces the process complexity, decreases the number of deposited semiconductor layers, and improves production efficiency; on the other hand, it reduces the area occupied by the active layer of the transistor, which is beneficial for high resolution.

[0068] Optional, Figure 7 This is a schematic diagram of the layout structure of a first transistor, a second transistor, and a third transistor provided in an embodiment of the invention, with reference to... Figure 3 and Figure 7 The second terminal T12 of the first transistor T1 is electrically connected to the gate T23 of the second transistor T2 through the first via H01.

[0069] For example, the display panel 04 further includes a first gate layer 31 located on one side of the substrate 10 and a second gate layer 32 located on the side of the first gate layer 31 away from the substrate 10; the first gate layer 31 is located between the first semiconductor layer 21 and the second semiconductor layer 22, and the second gate layer 32 is located on the side of the second semiconductor layer away from the substrate 10; the first gate layer 31 includes the gate T23 of the second transistor T2 and the gate T33 of the third transistor, and the second gate layer 32 includes the gate T13 of the first transistor 1. In the direction perpendicular to the plane of the substrate 10, the second electrode T12 of the first transistor T1 overlaps with the gate T23 of the second transistor T2, and the electrical connection between the second electrode T12 of the first transistor T1 and the gate T23 of the second transistor T2 can be achieved through only one first via H01. In this way, bridge vias can be reduced, which is beneficial to reducing the area occupied by the pixel circuit.

[0070] Optional, Figure 8 This is a schematic diagram of the layout structure of a first semiconductor layer and a first gate layer provided in an embodiment of the invention, with reference to... Figure 8 The active layer of the second transistor T2 extends along the second direction N.

[0071] For example, the active layer of the second transistor T2 is located on the first semiconductor layer 21. The first electrode T21, channel region T02, and second electrode T22 of the second transistor T2 are arranged sequentially along the second direction N. The first electrode T21, channel region T02, and second electrode T22 of the second transistor T2 are all located on the same straight line, and the active layer of the second transistor T2 is linear, which can reduce the length of the active layer of the second transistor T2. In this way, it is beneficial to reduce the area occupied by the active layer in the pixel circuit 03 and increase the number of pixel circuits 03 per unit area. In an optional embodiment, the first electrode T31, channel region T03, and second electrode T32 of the third transistor T3 are also arranged sequentially along the second direction N. The first electrode T31, channel region T03, and second electrode T32 of the third transistor T3 are all located on the same straight line, and the active layer of the third transistor T3 is also linear.

[0072] Further reference Figure 8 The length of the channel region T02 of the second transistor T2 is equal to the length of the gate T23 of the second transistor T2 along the second direction N. By reducing the length of the channel region T02 of the second transistor T2 to be equal to the length of the gate T23 of the second transistor T2 along the second direction N, the area occupied by the channel region T02 of the second transistor T2 can be reduced, which is beneficial to meeting the high resolution requirements of the display panel.

[0073] Optional, see reference Figure 9 The active layer of the first transistor T1 extends along the first direction M; the angle α between the first direction M and the second direction N ranges from 75° to 105°.

[0074] For example, the first electrode T11, channel region T01, and second electrode T12 of the first transistor T1 extend sequentially along the first direction M. The first electrode T11, channel region T01, and second electrode T12 of the first transistor T1 are all located on the same straight line, and the active layer of the first transistor T1 is linear. The active layers of the first transistor T1 and the second transistor T2 both extend in only one direction, which can reduce the length of the active layer of the transistor in the pixel circuit 01. The angle α between the first direction M and the second direction N is greater than or equal to 75° and less than or equal to 105°. On the one hand, this can avoid excessive overlap between the first transistor T1 and the second transistor T2 in the direction perpendicular to the plane of the substrate 10 when the angle α is too small, which could lead to misconnection or signal interference between the first transistor T1 and the second transistor T2. On the other hand, it can avoid increasing the length of the pixel circuit 03 in the first direction M and the length of the pixel circuit 03 in the second direction N when the angle α is too large, which would be detrimental to improving the resolution of the display panel 04.

[0075] Optional, continue to refer to Figure 9 The display panel 04 also includes a first scan signal line Scan1, which is electrically connected to the gate T13 of the first transistor T1. The first scan signal line Scan1 includes a first part Scan1-1 extending along a third direction X and a second part Scan1-2 extending along a second direction N. The first part Scan1-1 and the second part Scan1-2 are interconnected.

[0076] For example, Figure 10 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention, for reference. Figure 3 , Figure 9 and Figure 10To save space and reduce wiring, the first scan signal line Scan1 can be located in the second gate layer 32. The first scan signal line Scan1 includes the gate T13 of the first transistor T1, which reduces the number of vias and the area occupied by the pixel circuit 03. At least a portion of the first scan signal line Scan1 extends along the third direction X. Multiple second portions Scan1-2 extending along the second direction N can connect to multiple first portions Scan1-1 extending along the third direction X. The first scan signal line Scan1 is arranged along the fourth direction Y, so that the pixel circuits 03 arranged along the third direction X can share the same first scan signal line Scan1, which reduces the number of signal traces and is beneficial to the high resolution of the display panel 04. Each pixel circuit 03 includes a first portion Scan1-1 and a second portion Scan1-2 of the first scan signal line Scan1. The first scan signal line Scan1 is a zigzag line, which can increase the length of the first scan signal line Scan1 in a limited space. Thus, the length of the pixel circuit 03 in the third direction X can be reduced, which is beneficial to the high resolution of the display panel 04.

[0077] Optional, continue to refer to Figure 9 and Figure 10 The display panel 04 also includes a second scan signal line Scan2, which is electrically connected to the gate T33 of the third transistor T3. The second scan signal line Scan2 includes a third part Scan2-3 extending along the third direction X and a fourth part Scan2-4 extending along the first direction M. The third part Scan2-3 and the fourth part Scan2-4 are interconnected.

[0078] For example, refer to Figure 3 , Figure 9 and Figure 10 The second scan signal line Scan2 can be located in the first gate layer 31. The second scan signal line Scan2 includes the gate T33 of the third transistor T3, which can reduce the number of connection vias and reduce the area occupied by the pixel circuit 03. At least a portion of the second scan signal line Scan2 extends along the third direction X. Multiple fourth portions Scan2-4 extending along the first direction M can connect to multiple third portions Scan2-3 extending along the third direction X. The second scan signal line Scan2 is arranged along the fourth direction Y, so that the pixel circuits 03 arranged along the third direction X share the same second scan signal line Scan2. Each pixel circuit 03 includes the third portion Scan2-3 and the fourth portion Scan2-4 of the second scan signal line Scan2. The second scan signal line Scan2 is a zigzag line, which can increase the length of the second scan signal line Scan2 in a limited space. In this way, the length of the pixel circuit 03 in the third direction X can be reduced, which is beneficial to the high resolution of the display panel 04.

[0079] Optional, Figure 11 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention, for reference. Figure 11 The reset signal line VINT of the display panel 04 is arranged along the third direction X and extends along the fourth direction Y; the first terminal T31 of the third transistor T3 of the pixel circuit 03 arranged along the third direction X is electrically connected to the same reset signal line VINT.

[0080] For example, taking the third direction X as the row direction and the fourth direction Y as the column direction, the reset signal line VINT extends along the column direction. The first terminal T31 of the third transistor T3 of the pixel circuit 03 located in the same column is electrically connected to the same reset signal line VINT. That is, the number of reset signal lines VINT can be equal to the number of columns of pixel circuits 03 in the display panel 04. In order to save space and reduce the wiring layout, two adjacent pixel circuits 03 located in the same row can be symmetrical along the column direction, so that two adjacent pixel circuits 03 located in the same row can share some structures. For example, two adjacent pixel circuits 03 located in the same row can share the reset signal line VINT. The first terminal T31 of the third transistor T3 of two adjacent pixel circuits 03 located in the same row is electrically connected to the same reset signal line VINT, so that the number of reset signal lines VINT is less than the number of columns of pixel circuits 03. This can further reduce the number of reset signal lines VINT, reduce the area occupied by a single pixel circuit 03, and help the display panel 04 meet the high resolution pixel requirements.

[0081] It is understood that when two adjacent pixel circuits 03 are symmetrical along a certain direction, the first direction M and the second direction N of the two adjacent pixel circuits 03 are also symmetrical along that direction. For ease of understanding and explanation, the embodiments of the present invention are all illustrated using the first direction M and the second direction N as examples.

[0082] Continue to refer to Figure 11 The reset signal line VINT extends along the fourth direction Y; at least a portion of the first scan signal line Scan1 and / or the second scan signal line Scan2 extends along the third direction X; wherein, the first scan signal line Scan1 is electrically connected to the gate T13 of the first transistor T1; and the second scan signal line Scan2 is electrically connected to the gate T33 of the third transistor T3. The reset signal line VINT extends in a different direction than the first scan signal line Scan1 and / or the second scan signal line Scan2, which reduces the length of the pixel circuit 03 in the arrangement direction of the first scan signal line Scan1 and / or the second scan signal line Scan2, thereby reducing the area occupied by the pixel circuit 03 and helping the display panel 04 meet the high-resolution pixel requirements.

[0083] In an alternative embodiment, Figure 12This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention, for reference. Figure 12 The display panel 04 also includes: a lap electrode plate 06, a first lap electrode 061, and an inorganic insulating layer 60; the second electrode T22 of the second transistor T2 and the second electrode T32 of the third transistor T3 are both electrically connected to the lap electrode plate 06; the first lap electrode 61 is located on the side of the lap electrode plate 06 away from the substrate 10; the inorganic insulating layer 60 is located between the lap electrode plate 06 and the first lap electrode 61; the lap electrode plate 06 is electrically connected to the anode 051 of the light-emitting element 05 through the first lap electrode 61.

[0084] For example, the display panel 04 further includes a second conductive layer 42 on the side of the second gate layer 32 away from the substrate 10 and a third conductive layer 43 on the side of the second conductive layer 42 away from the substrate 10. A lap electrode 06 is located on the second conductive layer 42, and a first lap electrode 61 is located on the third conductive layer 43. The lap electrode 06 is electrically connected to the first lap electrode 61 through a second via H02. By setting the lap electrode 06 and the first lap electrode 61, the drilling depth can be reduced, lowering the process difficulty. The second via H02 is formed by drilling through the inorganic insulating layer 60. Compared with conventional organic insulating layers, the inorganic insulating layer 60 has higher drilling precision, resulting in a smaller size for the second via H02 between the lap electrode 06 and the first lap electrode 61. In the direction parallel to the plane of the substrate 10, the length d0 of the second via H02 ranges from d0≤2μm. Therefore, the area of ​​the lap electrode 06 can be set to be smaller. Figure 13 As shown, this helps to reduce the area occupied by the pixel circuit 03.

[0085] In an alternative embodiment, Figure 14 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention, for reference. Figure 12 and Figure 14 The power signal line PVDD, the reset signal line VINT, and the connecting plate 06 are arranged on the same layer and are all located in the second conductive layer 42. The power signal line PVDD and the reset signal line VINT both extend along the fourth direction Y and are alternately arranged along the third direction X. The first pole T21 of the second transistor T2 of the part of the pixel circuit 03 arranged along the third direction X is electrically connected to the same power signal line PVDD.

[0086] Furthermore, Figure 15 This is a schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present invention, with reference to... Figure 12 and Figure 15The first bridging electrode 061 is disposed on the same layer as the data signal line VDATA. Both the first bridging electrode 061 and the data signal line VDATA can be located in the third conductive layer 43, which can improve the space utilization of the pixel circuit 03, reduce the number of film layers, simplify the process, and improve production efficiency. However, in the direction perpendicular to the plane of the substrate 10, the area of ​​the first bridging electrode 061 should not be too large, otherwise it may easily lead to misconnection between the first bridging electrode 061 and the data signal line VDATA, affecting the display effect.

[0087] Optional, Figure 16 This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention. Figure 17 This is a schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present invention. (Reference) Figure 16 and Figure 17 The display panel 04 also includes a second bridging electrode 062; the second bridging electrode 062 is located on the side of the first bridging electrode 061 away from the substrate 10; the first bridging electrode 061 is electrically connected to the anode 051 of the light-emitting element 05 through the second bridging electrode 062. Specifically, in a direction perpendicular to the plane of the substrate 10, the area of ​​the second bridging electrode 062 is larger than the area of ​​the first bridging electrode 061.

[0088] For example, the display panel 04 also includes a fourth conductive layer 44 located on the side of the third conductive layer 43 away from the substrate. Only the second lap electrode 062 is disposed in the fourth conductive layer 44, without any other conductive structures. Therefore, in the direction perpendicular to the plane of the substrate 10, the area of ​​the second lap electrode 062 can be set to be larger, and the possibility of misconnection of the second lap electrode 062 is less likely. The second lap electrode 062 is electrically connected to the anode 051 of the light-emitting element 05 through a third via H03. The third via H03 is formed by drilling a hole in the planarization layer 70 located on the side of the fourth conductive layer 44 away from the substrate 10. The larger area of ​​the second lap electrode 062 in the direction perpendicular to the plane of the substrate 10 allows for a larger length of the third via H03 in the direction parallel to the plane of the substrate 10, reducing the requirement for drilling precision of the third via H03 and preventing misalignment between the third via H03 and the second lap electrode 062 due to low drilling precision in the planarization layer 70, which would affect the display effect.

[0089] Furthermore, the area of ​​the second lap electrode 062 is set to be larger in the direction perpendicular to the plane of the substrate 10, which allows the third via H03 to have a larger drilling diameter, lower resistance, and higher current transmission rate, enabling the light-emitting element 05 to respond to the electrical signals of the pixel circuit 03 more quickly and improve the display effect.

[0090] In an optional embodiment, the insulating layer between the first ground electrode 061 and the second ground electrode 062 includes an inorganic insulating layer. This can improve the accuracy of the connection via between the first ground electrode 061 and the second ground electrode 062, making the size of the connection via between the first ground electrode 061 and the second ground electrode 062 smaller, which is beneficial to reducing the area occupied by the pixel circuit 03.

[0091] After the area occupied by the pixel circuit 03 is reduced, the transistor gate overlaps with the traces of other electrical signals transmitting changing potentials in the direction perpendicular to the plane of the substrate 10, causing signal interference to the transistor gate. To solve the signal interference problem, this embodiment of the invention proposes a display panel. Figure 18 (a) is a schematic diagram of the layout structure of the display panel without the shielding electrode plate. Figure 18 (b) is a schematic diagram of the display panel layout after the shielding plates are installed. (Reference) Figure 16 and Figure 18 The display panel 04 also includes a shielding plate C01; the shielding plate C01 is located on the side of the gate T33 of the third transistor T3 away from the substrate 10, and the shielding plate C01 is also located on the side of the data signal line VDATA close to the substrate 10; in the direction perpendicular to the plane of the substrate 10, the shielding plate C01 overlaps with the gate T33 of the third transistor T3 and the data signal line VDATA.

[0092] For example, the display panel 04 further includes a first conductive layer 41 located between the first gate layer 31 and the second semiconductor layer 22. In a direction perpendicular to the plane of the substrate 10, the gate T33 of the third transistor T3 overlaps with the data signal line VDATA. The shielding plate C01 can shield the signal interference of the data signal line VDATA to the gate T33 of the third transistor T3. The shielding plate C01 can be electrically connected to signal lines with fixed potentials, such as power signal line PVDD and ground line, to shield signal interference.

[0093] Further reference Figure 18 In a direction perpendicular to the plane of substrate 10, shielding plate C01 covers the first scan signal line Scan1. The first scan signal line Scan1 is electrically connected to the gate T33 of the third transistor T3. In this way, signal interference from data signal line VDATA, reset signal line VINT and other signal lines to the first scan signal line Scan1 can be shielded.

[0094] Optional, Figure 19 This is a schematic diagram of the layout structure of another display panel provided in an embodiment of the present invention. Figure 20 This is a schematic diagram of the layout structure of a first pixel circuit and a second pixel circuit provided in an embodiment of the present invention. (Reference) Figure 19 and Figure 20The pixel circuit 03 includes an adjacent first pixel circuit 031 and a second pixel circuit 032; the first pixel circuit 031 and the second pixel circuit 032 are arranged along a third direction X; the first terminal T31 of the third transistor T3 of the first pixel circuit 031 is multiplexed as the first terminal T31 of the third transistor T3 of the second pixel circuit 032; the channel region T03 of the third transistor T3 of the first pixel circuit 031 partially overlaps with the channel region T03 of the third transistor T3 of the second pixel circuit 032.

[0095] Specifically, the adjacent first pixel circuit 031 and second pixel circuit 032 share the first electrode T31 and part of the channel region T03 of the third transistor T3. On the one hand, this can reduce the area occupied by the first electrode T31 and the channel region T03 of the third transistor T3 in the pixel circuit 03, thereby reducing the area occupied by the pixel circuit 03. On the other hand, reducing the area occupied by the first electrode T31 and the channel region T03 of the third transistor T3 in the pixel circuit 03 can reserve more space to set the first lap electrode 061 or lap plate 06, which can reduce the drilling accuracy of the first lap electrode 061 or lap plate 06 on the side away from the substrate 10 and improve the product yield.

[0096] For example, the third transistor T3 has an active layer T30 located on the first semiconductor layer 21. Figure 21 This is a schematic diagram of the structure of a first semiconductor layer provided in an embodiment of the present invention, with reference to... Figure 21 The active layer T30 of the third transistor T3 includes a first semiconductor portion 201 and a second semiconductor portion 202 and a third semiconductor portion 203 respectively connected to the first semiconductor portion 201. The second semiconductor portion 202 and the third semiconductor portion 203 are mirror-symmetrical along the extension direction of the first semiconductor portion 201. The first semiconductor portion 201 and the second semiconductor portion 202 constitute the active layer T30 of the third transistor T3 of the first pixel circuit 031. The first semiconductor portion 201 and the third semiconductor portion 203 constitute the active layer T30 of the third transistor T3 of the second pixel circuit 032. In this way, the length of the active layer T30 of the third transistor T3 in the extension direction of the first semiconductor portion can be reduced, and the length of the active layer T30 of the third transistor T3 in the third direction X can also be reduced, thereby reducing the area occupied by the pixel circuit 03, which is beneficial to the high resolution of the display panel 04.

[0097] In an alternative embodiment, Figure 22 This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention, for reference. Figure 22The bonding plate 06 is disposed on a different layer from the power signal line PVDD and the reset signal line VINT. For example, the power signal line PVDD and the reset signal line VINT are located on the active layer of the first transistor T1 near the substrate 10, while the bonding plate 06 is located on the gate T11 of the first transistor away from the substrate 10. By displacing the bonding plate 06 from the power signal line PVDD and the reset signal line VINT, the area of ​​the bonding plate 06 can be increased, while reducing the likelihood of incorrect connections, lowering the drilling accuracy on the side of the bonding plate 06 away from the substrate 10, and improving product yield.

[0098] Furthermore, Figure 23 This is a schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present invention, with reference to... Figure 22 and Figure 23 By placing the overlapping electrode 06 on a different layer from the power signal line PVDD and the reset signal line VINT, the area of ​​the power signal line PVDD can be increased, while reducing the risk of misconnection. In an optional embodiment, the power signal line PVDD overlaps with the second electrode T12 of the first transistor T1 in a direction perpendicular to the plane of the substrate 10.

[0099] Specifically, the overlapping portion of the power signal line PVDD and the second electrode T12 of the first transistor T1 forms a capacitor C. One end of the capacitor C is electrically connected to the power signal line PVDD, and the other end is electrically connected to the gate T23 of the second transistor T2 through the second electrode T12 of the first transistor T1. When the first transistor T1 is not transmitting data signals, the capacitor C can maintain the stability of the potential of the gate T23 of the second transistor T2, enabling the light-emitting element 05 to emit light stably and improving the display effect of the display panel 04. In addition, the capacitor C reuses the power signal line PVDD and the active layer of the first transistor T1 as capacitor plates, effectively utilizing the space of the pixel circuit 03, which helps to reduce the area occupied by the pixel circuit 03, thereby enabling the display panel 04 to meet the high-resolution pixel requirements while improving the display effect.

[0100] In an optional embodiment, a capacitor C' is provided between the first node N1 and the second node N2, such as... Figure 24 As shown, preferably, the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type transistors. During the light-emitting phase, the capacitor C' can maintain the stability of the potential of the gate T23 of the second transistor T2, thereby improving the display effect.

[0101] Figure 25 This is a schematic diagram of the film layer structure of another display panel provided in an embodiment of the present invention. Figure 26 This is a schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present invention. (Reference) Figure 25 and Figure 26The overlapping electrode 06 is disposed on a different layer from the power signal line PVDD and the reset signal line VINT. In a direction perpendicular to the plane of the substrate 10, the overlapping electrode 06 overlaps with the second electrode T12 of the first transistor T1. The overlapping portion of the overlapping electrode 06 and the second electrode T12 of the first transistor T1 forms a capacitor C'. One end of the capacitor C' is electrically connected to the anode 051 of the light-emitting element 05, and the other end is electrically connected to the gate T23 of the second transistor T2 through the second electrode T12 of the first transistor T1. During the light-emitting stage, the capacitor C' can maintain the stability of the potential of the gate T23 of the second transistor T2, so that the light-emitting element 05 can emit light stably, improving the display effect of the display panel 04. In addition, the capacitor C' reuses the overlapping electrode 06 and the active layer of the first transistor T1 as capacitor plates, effectively utilizing the space of the pixel circuit 03, which helps to reduce the area occupied by the pixel circuit 03, thereby enabling the display panel 04 to meet the high-resolution pixel requirements while improving the display effect.

[0102] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 27 The display device 09 includes the display panel 04 provided in any embodiment of the present invention. The display device 09 provided in the embodiments of the present invention can be... Figure 27 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This embodiment of the invention does not impose any special limitations on these categories.

[0103] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: A substrate, a plurality of pixel circuits located on one side of the substrate, and a plurality of light-emitting elements located on the side of the pixel circuits away from the substrate; The pixel circuit includes a first transistor, a second transistor, and a third transistor; the first terminal of the first transistor is electrically connected to a data signal line; the second terminal of the first transistor is electrically connected to the gate of the second transistor; the first terminal of the second transistor is electrically connected to a power signal line; and the first terminal of the third transistor is electrically connected to a reset signal line. The second terminal of the second transistor and the second terminal of the third transistor are both electrically connected to the light-emitting element; The channel regions of the first transistor and the second transistor are arranged along a first direction; the channel regions of the second transistor and the third transistor are arranged along a second direction; the first direction and the second direction intersect. Both the first direction and the second direction are parallel to the plane where the substrate is located, and both the first direction and the second direction intersect the arrangement direction of the pixel circuit; The pixel circuits are arranged along a third direction and a fourth direction, respectively, and the third direction and the fourth direction intersect. The pixel circuit includes an adjacent first pixel circuit and a second pixel circuit; the first pixel circuit and the second pixel circuit are arranged along the third direction; the first electrode of the third transistor of the first pixel circuit is multiplexed as the first electrode of the third transistor of the second pixel circuit; the channel region of the third transistor of the first pixel circuit partially overlaps with the channel region of the third transistor of the second pixel circuit.

2. The display panel according to claim 1, characterized in that, The active layer of the first transistor is an oxide semiconductor active layer, and the active layer of the second transistor is a silicon active layer; in a direction perpendicular to the plane of the substrate, the first transistor and the second transistor at least partially overlap.

3. The display panel according to claim 2, characterized in that, The second terminal of the first transistor is electrically connected to the gate of the second transistor through a first via.

4. The display panel according to claim 1, characterized in that, The active layer of the second transistor extends along the second direction.

5. The display panel according to claim 4, characterized in that, The length of the channel region of the second transistor is equal to the length of the gate of the second transistor along the second direction.

6. The display panel according to claim 4, characterized in that, The active layer of the first transistor extends along the first direction; the angle α between the first direction and the second direction ranges from 75°≤α≤105°.

7. The display panel according to claim 1, characterized in that, The length of the pixel circuit in the third direction is L1, and the length of the pixel circuit in the fourth direction is L2, where 0.9 ≤ L1 / L2 ≤ 1.

1.

8. The display panel according to claim 7, characterized in that, The length L1 of the pixel circuit in the third direction has a range of 7μm≤L1≤9μm; the length L2 of the pixel circuit in the fourth direction has a range of 7μm≤L2≤9μm.

9. The display panel according to claim 7, characterized in that, Also includes: The first scan signal line is electrically connected to the gate of the first transistor; The first scan signal line includes a first portion extending along the third direction and a second portion extending along the second direction, the first portion and the second portion being interconnected.

10. The display panel according to claim 7, characterized in that, Also includes: The second scan signal line is electrically connected to the gate of the third transistor; The second scan signal line includes a third portion extending along the third direction and a fourth portion extending along the first direction, the third portion and the fourth portion being interconnected.

11. The display panel according to claim 7, characterized in that, The reset signal line is along the third direction. The third transistor of the pixel circuit, arranged along the fourth direction, is electrically connected to the same reset signal line.

12. The display panel according to claim 7, characterized in that, The reset signal line extends along the fourth direction; The display panel further includes a first scan signal line and a second scan signal line; the first scan signal line and the... The gate of the first transistor is electrically connected; the second scan signal line is electrically connected to the gate of the third transistor; at least a portion of the first scan signal line and / or the second scan signal line extends along the third direction.

13. The display panel according to claim 1, wherein the active layer of the third transistor comprises a first semiconductor portion and a second semiconductor portion and a third semiconductor portion respectively connected to the first semiconductor portion; The second semiconductor portion and the third semiconductor portion are mirror-symmetrical along the extending direction of the first semiconductor portion; The first semiconductor portion and the second semiconductor portion constitute the active layer of the third transistor of the first pixel circuit; the first semiconductor portion and the third semiconductor portion constitute the active layer of the third transistor of the second pixel circuit.

14. The display panel according to claim 1, characterized in that, Also includes: Overlapping electrode, first overlapping electrode and inorganic insulating layer; The second electrode of the second transistor and the second electrode of the third transistor are both electrically connected to the lap plate; The first lap electrode is located on the side of the lap electrode plate away from the substrate; the inorganic insulating layer is located between the lap electrode plate and the first lap electrode. The lap electrode plate is electrically connected to the anode of the light-emitting element through the first lap electrode.

15. The display panel according to claim 14, characterized in that, The first lap electrode is disposed on the same layer as the data signal line; The display panel further includes a second lap electrode; the second lap electrode is located on the side of the first lap electrode away from the substrate; The first electrode is electrically connected to the anode of the light-emitting element through the second electrode. In the direction perpendicular to the plane of the substrate, the area of ​​the second overlapping electrode is larger than the area of ​​the first overlapping electrode.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1-15.

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