An address decoding control circuit for FLASH redundancy repair

Abstract

The application discloses an address decoding control circuit for FLASH redundancy repair, which comprises a word line address decoding control circuit and a word line redundancy replacement repair circuit. The application realizes the shielding of standard word lines with defective storage units by increasing the circuit structure for controlling the word line address decoder, and simultaneously uses the redundant word lines for replacement repair. The repaired memory can be normally used, thereby significantly improving the yield of the FLASH memory.

Description

TECHNICAL FIELD

[0001] The application relates to an address decoding control circuit for FLASH redundancy repair and belongs to the technical field of memory chip design. BACKGROUND

[0002] In the production process of a FLASH memory, due to the uncertainty of a process, consistency of storage units is poor, and defective storage units are prone to be generated. A traditional word line address decoder can only select a corresponding target word line according to an input word line address signal, and when the defective storage unit exists on the target word line, the defective storage unit cannot be normally read or written and erased, so that the whole memory cannot be normally used. Especially, with the continuous development of the memory technology, the storage density is higher and higher, and the manufacturing process is more and more complex, so more and more process defects are generated, thereby further reducing the yield of the FLASH memory and making it difficult to improve the production of the memory product. SUMMARY

[0003] The application aims at overcoming the defects of the prior art, providing an address decoding control circuit for FLASH redundancy repair, increasing a circuit structure for controlling the word line address decoder, shielding the standard word line with the defective storage unit, and replacing and repairing the defective storage unit by using the redundant word line, so that the repaired memory can be normally used, thereby significantly improving the yield of the FLASH memory.

[0004] The above purpose of the application is mainly achieved by the following technical scheme.

[0005] The address decoding control circuit for FLASH redundancy repair comprises a word line address decoding control circuit and a word line redundancy replacement and repair circuit; the word line address decoding control circuit shields the standard word line with the defective storage unit, and the word line redundancy replacement and repair circuit replaces and repairs the shielded standard word line by using the redundant word line, thereby repairing the memory with the defective storage unit.

[0006] Further, the word line address decoding control circuit comprises an enable register REG_EN, a plurality of address registers REG_ADDR[0:i], a plurality of PMOS transistors P_0 and P[0:i], a plurality of latches LATCH_0 and LATCH[0:i], a plurality of inverters INV[0:i], a plurality of transmission gates TG[0:i] and TG_N[0:i].

[0007] The one enable register REG_EN is used to enable the word line address decoding control circuit to mask and replace the defective memory cell in the standard word line; the several address registers REG_ADDR[0:i] are used to store the address of the defective memory cell in the standard word line;

[0008] The several PMOS transistors P_0 and P[0:i], the several latches LATCH_0 and LATCH[0:i] are used to transmit the signal ENABLE in the enable register REG_EN and the signal ADDRESS[0:i] in the address register REG_ADDR[0:i] to the latches LATCH_0 and LATCH[0:i] and latch as the inverse signals out_0 and out[0:i];

[0009] The several inverters INV[0:i], the transmission gates TG[0:i] and TG_N[0:i] are used to control the transmission gate switch according to the signal out[0:i] and output the input word line address WL_ADDR[0:i] signal or its inverse signal as the A[0:i] signal.

[0010] Further, the word line address decoding control circuit further comprises a NOR gate and an OR gate; the NOR gate inputs the forcedisable signal, the out_0 signal and the A[0:i] signal and outputs the OUT signal;

[0011] The OR gate inputs the OUT signal and the forcematch signal and outputs the MATCH signal;

[0012] When the forcedisable signal is high and the forcematch signal is low, the MATCH signal is forced to be low, and when the forcematch signal is high, the MATCH signal is forced to be high.

[0013] Further, the signal ENABLE stored in the enable register REG_EN is the enable signal of the word line address decoding control circuit, and the signal ADDRESS[0:i] stored in the address register REG_ADDR[0:i] is the address of the defective memory cell in the standard word line.

[0014] Further, at power-on, the initial RESET signal is set to low, the PMOS transistors P_0 and P[0:i] are turned on, and the reset latches LATCH_0 and LATCH[0:i] are reset;

[0015] After the RESET signal is set to high, the PMOS transistors P_0 and P[0:i] are closed, and the ENABLE signal and the ADDRESS[0:i] signal stored in the enable register REG_EN and the address register REG_ADDR[0:i] are transmitted to the latches LATCH_0 and LATCH[0:i] and are latched as the inverse signals out_0 and out[0:i].

[0016] Further, the out[0:i] signal controls the switches of the transmission gates TG[0:i] and TG_N[0:i] to output the input word line address signal WL_ADDR[0:i] as the A[0:i] signal through the TG[0:i] or output the inverse signal of WL_ADDR[0:i] through the TG_N[0:i] as the A[0:i] signal after being inverted by the inverters INV[0:i];

[0017] When the ADDRESS[a] signal is high, the TG[a] is closed, and the TG_N[a] is opened. When the WL_ADDR[a] signal is high, the A[a] signal output after being inverted by the INV[a] is low, indicating that the input word line address and the standard word line address of the defective memory cell stored in the address register are the same. Conversely, the A[a] signal is high, indicating that the two addresses are different.

[0018] When the ADDRESS[a] signal is low, the TG[a] is opened, and the TG_N[a] is closed. When the WL_ADDR[a] signal is low, the A[a] signal output is low, indicating that the input word line address and the standard word line address of the defective memory cell stored in the address register are the same. Conversely, the A[a] signal is high, indicating that the two addresses are different.

[0019] Further, the out_0 signal, the A[0:i] signal, and the forcedisable signal are input into a NOR gate. When all the signals are low, the OUT signal output by the NOR gate is high, otherwise the OUT signal is low. The OUT signal and the forcematch signal are input into an OR gate. When both signals are low, the MATCH signal output by the OR gate is low, otherwise the MATCH signal is high. When the forcedisable signal is high and the forcematch signal is low, the MATCH signal is forced to be low. When the forcematch signal is high, the MATCH signal is forced to be high.

[0020] Further, the word line redundancy replacement repair circuit includes a NOR gate, a word line address decoder WLDEC, a plurality of word line drivers WLDR, a plurality of redundant word lines RWL[0:m], and a plurality of standard word lines WL[0:n];

[0021] The NOR gate is inputted by the MATCH[0:m] signals outputted by the several word line address decoding control circuits, and outputs the standard word line shielding signal disable.

[0022] The word line address decoder WL DEC is controlled by the input word line address WL ADDR[0:i] and the standard word line shielding signal disable, and shields or normally decodes the standard word lines WL[0:n].

[0023] The redundant word lines RWL[0:m] are used to replace the word lines of the defective memory cells in the standard word lines WL[0:n].

[0024] The inputs of the several word line drivers WLDR are the signals outputted by the word line address decoder WL DEC or the MATCH[0:m] signals outputted by the word line address decoding control circuits, which are used to output the voltage required for driving the standard word lines WL[0:n] or the redundant word lines RWL[0:m].

[0025] Further, the MATCH[0:m] signals outputted by all the word line address decoding control circuits are inputted into the NOR gate, and the NOR gate outputs the standard word line shielding signal disable; the input word line address WL ADDR[0:i] and the standard word line shielding signal disable are transmitted to the word line address decoder WL DEC.

[0026] When all the MATCH[0:m] signals are low, the disable signal outputted by the NOR gate is high, the signal outputted by the word line address decoder WL DEC is a normal decoding signal, and all the standard word lines connected thereto are not shielded.

[0027] When the MATCH[b] signal outputted by a certain word line address decoding control circuit is high, the disable signal outputted by the NOR gate is low, and the signal outputted by the word line address decoder WL DEC is low, and all the standard word lines connected thereto are shielded.

[0028] Further, each word line address decoding control circuit is connected with a redundant word line, and controls whether to replace the standard word line with the redundant word line.

[0029] When the stored signals in the enable registers REG_EN in all the word line address decoding control circuits are low, the MATCH[0:m] signals outputted are all low, and none of the redundant word lines is selected to replace the standard word line.

[0030] When the signal stored in the enable register REG_EN in the word line address decoding control circuit connected with the redundant word line RWL[b] is high, and the signal stored in the address register REG_ADDR[0:i] is the address of the standard word line WL[c] of the defective memory cell, it indicates that the redundant word line RWL[b] is used to replace the repaired standard word line WL[c]; at this time, when the input word line address WL_ADDR[0:i] is the same as the address WL[c] stored in the address register REG_ADDR[0:i], the MATCH[b] signal output by the word line address decoding control circuit is high, the redundant word line RWL[b] connected therewith is selected, and the remaining redundant word lines are not selected.

[0031] The beneficial effects of the present application compared with the prior art are:

[0032] The present application adds an address decoding control circuit for redundancy repair to the traditional word line address decoder in the FLASH memory, and the MATCH[0:m] signal output by the control circuit can control the standard word line of the defective memory cell to be shielded, and the corresponding redundant word line is selected to replace and repair the shielded standard word line. After all the defective memory cells caused in the production process are successfully replaced and repaired, the memory can be normally used. The address decoding control circuit for FLASH redundancy repair provided by the present application can significantly improve the yield of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a schematic diagram of the word line address decoding control circuit according to the embodiment of the present application.

[0034] Figure 2 is a schematic diagram of the word line redundancy replacement repair circuit according to the embodiment of the present application. DETAILED DESCRIPTION

[0035] The present application will be further described in detail below in combination with the drawings and embodiments:

[0036] The present application provides an address decoding control circuit for FLASH redundancy repair, which mainly has two parts, namely: the word line address decoding control circuit shields the standard word line of the defective memory cell, and the word line redundancy replacement repair circuit uses the redundant word line to replace and repair the shielded standard word line, thereby completing the repair of the defective memory cell of the memory.

[0037] As Figure 1The figure is a schematic diagram of the word line address decoding control circuit 100 of the present application, mainly including an enable register REG_EN, a plurality of address registers REG_ADDR[0:i], a plurality of PMOS transistors P_0 and P[0:i], a plurality of latches LATCH_0 and LATCH[0:i], a plurality of inverters INV[0:i], a plurality of transmission gates TG[0:i] and TG_N[0:i], a NOR gate and an OR gate.

[0038] The signal ENABLE stored in the enable register REG_EN is the enable signal of the control circuit. The signal ADDRESS[0:i] stored in the address register REG_ADDR[0:i] is the address of the standard word line of a defective memory cell. At power-up, the initial RESET signal is set to low, the PMOS transistors P_0 and P[0:i] are turned on, and the latches LATCH_0 and LATCH[0:i] are reset. Then the RESET signal is set to high, the PMOS transistors P_0 and P[0:i] are turned off, and the signals ENABLE and ADDRESS[0:i] stored in the enable register REG_EN and the address register REG_ADDR[0:i] are transmitted to the latches LATCH_0 and LATCH[0:i] and latched as the inverted signals out_0 and out[0:i].

[0039] The signal out[0:i] controls the switches of the transmission gates TG[0:i] and TG_N[0:i] to output the input word line address signal WLADDR[0:i] as the signal A[0:i] through TG[0:i] or as the inverted signal of WLADDR[0:i] through TG_N[0:i] after being inverted by the inverter INV[0:i]. When the signal ADDRESS[a] is high, TG[a] is turned off and TG_N[a] is turned on. When the signal WLADDR[a] is high, the signal A[a] output after being inverted by INV[a] is low, indicating that the input word line address and the standard word line address of the defective memory cell stored in the address register are the same. Conversely, the signal A[a] is high, indicating that the two addresses are different. When the signal ADDRESS[a] is low, TG[a] is turned on and TG_N[a] is turned off. When the signal WLADDR[a] is low, the signal A[a] output is low, indicating that the input word line address and the standard word line address of the defective memory cell stored in the address register are the same. Conversely, the signal A[a] is high, indicating that the two addresses are different.

[0040] The out_0 signal, the A[0:i] signal and the forcedisable signal are inputted into the NOR gate together. When all the signals are low, the OUT signal outputted from the NOR gate is high, otherwise the OUT signal is low. The OUT signal and the forcematch signal are inputted into the OR gate together. When both of the signals are low, the MATCH signal outputted from the OR gate is low, otherwise the MATCH signal is high. When the forcedisable signal is high and the forcematch signal is low, the MATCH signal is forced to be low. When the forcematch signal is high, the MATCH signal is forced to be high.

[0041] As shown in Figure 2 The figure is the circuit diagram of the word line redundancy replacement repair circuit of the present application, which mainly comprises a NOR gate, a word line address decoder WL DEC, a plurality of word line drivers WLDR, a plurality of redundant word lines RWL[0:m] and a plurality of standard word lines WL[0:n].

[0042] The MATCH[0:m] signals outputted from all the word line address decoding control circuits 100 are inputted into the NOR gate together, and the NOR gate outputs the standard word line shielding signal disable. The word line address WL ADDR[0:i] and the standard word line shielding signal disable are transmitted to the word line address decoder WL DEC. When all the MATCH[0:m] signals are low, the disable signal outputted from the NOR gate is high, and the signal outputted from the word line address decoder WL DEC is the normal decoding signal, and all the standard word lines connected therewith are not shielded. When the MATCH[b] signal outputted from a certain word line address decoding control circuit 100 is high, the disable signal outputted from the NOR gate is low, and the signal outputted from the word line address decoder WL DEC is low, and all the standard word lines connected therewith are shielded.

[0043] Meanwhile, each word line address decoding control circuit 100 is connected with a redundant word line, and controls whether to replace the standard word line with the redundant word line. When the signals stored in the enable registers REG_EN in all word line address decoding control circuits 100 are low, the output MATCH[0:m] signals are low, and none of the redundant word lines is selected to replace the standard word line. When the signal stored in the enable register REG_EN in the word line address decoding control circuit 100 connected with the redundant word line RWL[b] is high, and the signals stored in the address register REG_ADDR[0:i] are the address of the standard word line WL[c] of the defective memory cell, it indicates that the redundant word line RWL[b] is used to replace the standard word line WL[c]. At this time, when the input word line address WL_ADDR[0:i] is the same as the address WL[c] stored in the address register REG_ADDR[0:i], the MATCH[b] signal output by the word line address decoding control circuit 100 is high, and the redundant word line RWL[b] connected therewith is selected, and the other redundant word lines are not selected.

[0044] The address decoding control circuit output signal MATCH[0:m] can control the standard word line of the defective memory cell to be shielded, and select the corresponding redundant word line to replace and repair the shielded standard word line. After all the defective memory cells caused in the production process are successfully replaced and repaired, the memory can be normally used.

[0045] The above description is only the best specific embodiment of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

[0046] The contents not described in detail in the specification of the present application are the common technology of the person skilled in the art.

Claims

1. An address decoding control circuit for FLASH redundancy repair, characterized by, The application relates to a word line address decoding control circuit and a word line redundancy replacement repair circuit. The word line address decoding control circuit shields the standard word line of the defective storage unit, and the word line redundancy replacement repair circuit replaces and repairs the shielded standard word line by using a redundant word line, thereby completing the repair of the memory of the defective storage unit. The word line address decoding control circuit comprises an enable register REG_EN, a plurality of address registers REG_ADDR[0:i], a plurality of PMOS transistors P_0 and P[0:i], a plurality of latches LATCH_0 and LATCH[0:i], a plurality of inverters INV[0:i], a plurality of transmission gates TG[0:i] and TG_N[0:i]. The enable register REG_EN is used for enabling the word line address decoding control circuit to shield the standard word line of the defective storage unit and to replace the defective storage unit; and the plurality of address registers REG_ADDR[0:i] are used for storing the address of the standard word line of the defective storage unit. The plurality of PMOS transistors P_0 and P[0:i], the plurality of latches LATCH_0 and LATCH[0:i] are used for transmitting the signal ENABLE in the enable register REG_EN and the signal ADDRESS[0:i] in the address register REG_ADDR[0:i] to the latches LATCH_0 and LATCH[0:i] and latching the signals as inverse signals out_0 and out[0:i]. The plurality of inverters INV[0:i], the transmission gates TG[0:i] and TG_N[0:i] are used for controlling the transmission gate switch according to the signal out[0:i] and outputting the input word line address WL_ADDR[0:i] signal or the inverse signal thereof as an A[0:i] signal. The word line address decoding control circuit further comprises a NOR gate and an OR gate; the NOR gate inputs a forcedisable signal, an out_0 signal and an A[0:i] signal and outputs an OUT signal; 2. The address decoding control circuit for FLASH redundancy repair according to claim 1, wherein: The OR gate inputs the OUT signal and a forcematch signal and outputs a MATCH signal; When the forcedisable signal is high and the forcematch signal is low, the MATCH signal is forced to be low, and when the forcematch signal is high, the MATCH signal is forced to be high. The signal ENABLE stored in the enable register REG_EN is an enabling signal of the word line address decoding control circuit, and the signal ADDRESS[0:i] stored in the address register REG_ADDR[0:i] is the address of the standard word line of the defective storage unit.

3. The address decoding control circuit for FLASH redundancy repair according to claim 2, wherein: When powered on, the initial RESET signal is set to be low, the PMOS transistors P_0 and P[0:i] are opened, and the latches LATCH_0 and LATCH[0:i] are reset.

4. The address decoding control circuit for FLASH redundancy repair according to claim 2, wherein: ​ After the RESET signal is set high, the PMOS transistors P_0 and P[0:i] are closed, and the ENABLE signal and the ADDRESS[0:i] signal stored in the enable register REG_EN and the address register REG_ADDR[0:i] are transmitted to the latches LATCH_0 and LATCH[0:i] and are latched as the inverse signals out_0 and out[0:i].

5. The address decoding control circuit for FLASH redundancy repair according to claim 4, wherein: The out[0:i] signal controls the switches of the transmission gates TG[0:i] and TG_N[0:i] to output the input word line address signal WL_ADDR[0:i] as the A[0:i] signal through the TG[0:i] or output the inverse signal of WL_ADDR[0:i] through the TG_N[0:i] as the A[0:i] signal after being inverted by the inverters INV[0:i]; When the ADDRESS[a] signal is high, the TG[a] is closed, and the TG_N[a] is opened. When the WL_ADDR[a] signal is high, the A[a] signal output after being inverted by the INV[a] is low, indicating that the input word line address and the standard word line address of the defective memory cell stored in the address register are the same. Conversely, the A[a] signal is high, indicating that the two addresses are different. When the ADDRESS[a] signal is low, the TG[a] is opened, and the TG_N[a] is closed. When the WL_ADDR[a] signal is low, the A[a] signal output is low, indicating that the input word line address and the standard word line address of the defective memory cell stored in the address register are the same. Conversely, the A[a] signal is high, indicating that the two addresses are different.

6. The address decoding control circuit for FLASH redundancy repair according to claim 4, wherein: The out_0 signal, the A[0:i] signal, and the forcedisable signal are input into a NOR gate. When all the signals are low, the OUT signal output by the NOR gate is high. Otherwise, the OUT signal is low. The OUT signal and the forcematch signal are input into an OR gate. When both signals are low, the MATCH signal output by the OR gate is low. Otherwise, the MATCH signal is high. When the forcedisable signal is high and the forcematch signal is low, the MATCH signal is forced to be low. When the forcematch signal is high, the MATCH signal is forced to be high.

7. The address decoding control circuit for FLASH redundancy repair according to claim 1, wherein: The word line redundancy replacement repair circuit includes a NOR gate, a word line address decoder WL DEC, a plurality of word line drivers WLDR, a plurality of redundant word lines RWL[0:m], and a plurality of standard word lines WL[0:n]; The NOR gate is input by the MATCH[0:m] signals output by the plurality of word line address decoding control circuits. The NOR gate outputs a standard word line masking signal disable. The word line address decoder WL DEC is controlled by the input word line address WL_ADDR[0:i] and the standard word line masking signal disable to mask or normally decode the standard word lines WL[0:n]. The redundant word lines RWL[0:m] are used to replace the defective memory cells in the standard word lines WL[0:n]; The inputs of the word line drivers WLDR are the signals outputted by the word line address decoders WL DEC or the MATCH[0:m] signals outputted by the word line address decoding control circuits, which are used to output the required voltages for driving the standard word lines WL[0:n] or the redundant word lines RWL[0:m].

8. The address decoding control circuit for FLASH redundancy repair according to claim 7, wherein: The MATCH[0:m] signals outputted by all the word line address decoding control circuits are inputted into a NOR gate, and the NOR gate outputs a standard word line shielding signal disable; the word line address WL ADDR[0:i] and the standard word line shielding signal disable are transmitted to the word line address decoders WL DEC. When all the MATCH[0:m] signals are low, the disable signal outputted by the NOR gate is high, and the signals outputted by the word line address decoders WL DEC are normal decoding signals, and all the standard word lines connected thereto are not shielded. When the MATCH[b] signal outputted by a certain word line address decoding control circuit is high, the disable signal outputted by the NOR gate is low, and the signals outputted by the word line address decoders WL DEC are low, and all the standard word lines connected thereto are shielded.

9. The address decoding control circuit for FLASH redundancy repair according to claim 8, wherein: Each word line address decoding control circuit is connected with a redundant word line, and controls whether to replace the standard word line with the redundant word line; When the signals stored in the enable registers REG_EN in all the word line address decoding control circuits are low, the MATCH[0:m] signals outputted are all low, and none of the redundant word lines is selected to replace the standard word line. When the signal stored in the enable register REG_EN in a certain word line address decoding control circuit connected with the redundant word line RWL[b] is high, and the signal stored in the address register REG_ADDR[0:i] is the address of the standard word line WL[c] with defective memory cells, it indicates that the redundant word line RWL[b] is used to replace the standard word line WL[c]; at this time, when the inputted word line address WL ADDR[0:i] is the same as the address WL[c] stored in the address register REG_ADDR[0:i], the MATCH[b] signal outputted by the word line address decoding control circuit is high, and the redundant word line RWL[b] connected thereto is selected, and the other redundant word lines are not selected.

Images