Integrated circuit comprising memory cells

Abstract

The present disclosure relates to an integrated circuit comprising memory cells. An integrated circuit for accessing memory associated with a fluid ejection device, the integrated circuit comprising: a plurality of memory cells; an address decoder for selecting a memory cell in response to an address; activation logic for activating the selected memory cell based on a data signal and a fire signal; and configuration logic for enabling or disabling access to the plurality of memory cells.

Description

[0001] This application is a divisional application of the Chinese Patent Application No. 201980091366.5, filed on February 6, 2019, entitled “Integrated Circuit Including Memory Cells”. TECHNICAL FIELD

[0002] The present disclosure relates generally to integrated circuits including memory cells. BACKGROUND

[0003] An inkjet printing system, as one example of a fluid ejection system, can include a printhead, an ink supply that supplies liquid ink to the printhead, and an electronic controller that controls the printhead. The printhead, as one example of a fluid ejection device, ejects drops of ink through a plurality of nozzles or orifices and onto a print medium, such as a sheet of paper, to print on the print medium. In some examples, the orifices are arranged in at least one column or array, such that when the printhead and the print medium are moved relative to each other, properly sequenced ejection of ink from the orifices causes characters or other images to be printed on the print medium. SUMMARY

[0004] In one aspect, the present disclosure provides an integrated circuit for accessing memory associated with a fluid ejection device, the integrated circuit comprising: a plurality of memory cells; an address decoder to select a memory cell in response to an address; activation logic to activate the selected memory cell based on a data signal and a fire signal; and configuration logic to enable or disable access to the plurality of memory cells. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1A is a block diagram illustrating one example of an integrated circuit to drive a plurality of fluid actuation devices.

[0006] Figure 1B is a block diagram illustrating another example of an integrated circuit to drive a plurality of fluid actuation devices.

[0007] Figure 2 is a schematic diagram illustrating one example of circuitry to drive a plurality of fluid actuation devices or access corresponding memory cells.

[0008] Figure 3A is a block diagram illustrating one example of an integrated circuit to access memory associated with a fluid ejection device.

[0009] Figure 3B is a block diagram illustrating another example of an integrated circuit to access memory associated with a fluid ejection device.

[0010] Figure 4A and Figure 4B An example of a fluid ejection die is illustrated.

[0011] Figure 5A An enlarged view of one example of a portion of a fluid ejection die is illustrated.

[0012] Figure 5B is a block diagram illustrating one example of a set of memory cells of a fluid ejection die of Figure 5A

[0013] Figure 6A An enlarged view of another example of a portion of a fluid ejection die is illustrated.

[0014] Figure 6B is a block diagram illustrating one example of a set of memory cells of a fluid ejection die of Figure 6A

[0015] Figure 7 is a block diagram illustrating one example of a fluid ejection system. DETAILED DESCRIPTION

[0016] In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific examples in which a disclosure can be practiced. It is to be understood that other examples can be utilized and that structural or logical changes can be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. It is to be understood that features of the various examples described herein can be combined, in part or whole, with each other, unless otherwise specifically noted.

[0017] A fluid ejection die, such as a thermal inkjet (TIJ) die, can be a narrow and long silicon die. The silicon area used by the die is related to the cost of the die, such that any functionality that can be removed from the die should be removed, or modified to have multiple uses if possible. Non-volatile memory (NVM) can be used on the die to transfer information (such as thermal behavior, offsets, zone information, color maps, number of nozzles, etc.) from the die to the printer. Additionally, the NVM can also be used to transfer information (such as ink usage tables, nozzle health information, etc.) from the printer to the die. The memory can be made up of storage elements, read / write multiplexers, and enable / address circuitry. For small memories, the non-storage circuitry can take up a large portion of the total area used by the memory, such that the area efficiency of the small memory is low.

[0018] ​​Accordingly, disclosed herein are integrated circuits (e.g., fluid ejection dies) that include memory cells corresponding to fluid actuation devices. The same circuitry logic is used to activate selected fluid actuation devices or to access selected corresponding memory cells based on received addresses and nozzle data. Data stored in each memory cell can be read out of the integrated circuit through a single contact pad. The memory cells can be distributed along a length of the integrated circuit adjacent to the corresponding fluid actuation devices.

[0019] As used herein, a "logic high" signal is a logic "1" or "on" signal or a signal having a voltage about equal to a logic power supplied to an integrated circuit (e.g., between about 1.8 V and 15 V, such as 5.6 V). As used herein, a "logic low" signal is a logic "0" or "off signal or a signal having a voltage about equal to a logic power ground return of a logic power supplied to an integrated circuit (e.g., about 0 V).

[0020] Figure 1A is a block diagram illustrating one example of an integrated circuit 100 for driving a plurality of fluid actuation devices. The integrated circuit 100 includes a plurality of fluid actuation devices 1020 to 102 N , where "N" is any suitable number of fluid actuation devices. The integrated circuit 100 also includes a plurality of memory cells 1040 to 104 N , a selection circuit 106, control logic 108, and configuration logic 110. Each fluid actuation device 1020 to 102 N is electrically coupled to the control logic 108 by a signal path 1010 to 101 N , respectively. Each memory cell 1040 to 104 N is electrically coupled to the control logic 108 by a signal path 1030 to 103 N , respectively. The control logic 108 is electrically coupled to the selection circuit 106 by a signal path 107 and to the configuration logic 110 by a signal path 109.

[0021] In one example, each fluid actuation device 1020 to 102 N includes a nozzle or fluid pump for ejecting a droplet. Each memory cell 1040 to 104 N corresponds to a fluid actuation device 1020 to 102 N , respectively. In one example, each memory cell 1040 to 104 N includes a non-volatile memory cell (e.g., a floating gate transistor, a programmable fuse, etc.). The selection circuit 106 selects a fluid actuation device 1020 to 102 N and the memory cell 1040 to 104 N corresponding to the selected fluid actuation device 1020 to 102N The selection circuit 106 can include an address decoder, activation logic, and / or other suitable logic circuitry to select the fluid actuation devices 1020 to 102 N and corresponding memory cells 1040 to 104 N in response to address signals and nozzle data signals. The configuration logic 110 enables or disables access to the plurality of memory cells 1040 to 104 N . The configuration logic 110 can include a memory device or other suitable logic circuitry to enable or disable access to the plurality of memory cells 1040 to 104 N .

[0022] The control logic 108 activates the selected fluid actuation devices 1020 to 102 N or accesses the memory cells 1040 to 104 N corresponding to the selected fluid actuation devices based on a state of the configuration logic 110. The control logic 108 can include a microprocessor, an application specific integrated circuit (ASIC), or other suitable logic circuitry to control operation of the integrated circuit 100. Although the selection circuit 106, the control logic 108, and the configuration logic 110 are illustrated in separate blocks in Figure 1A , in other examples, the selection circuit 106, the control logic 108, and / or the configuration logic 110 can be combined into a single block or a different number of blocks.

[0023] Figure 1B is a block diagram illustrating another example of an integrated circuit 120 to drive a plurality of fluid actuation devices. The integrated circuit 120 includes a plurality of fluid actuation devices 1020 to 102 N , a plurality of memory cells 1040 to 104 N , a selection circuit 106, and a control logic 108. Additionally, the integrated circuit 120 includes a write circuit 130, a sensor 132, and configuration registers 136. In one example, Figure 1A The configuration logic 110 of the integrated circuit 100 includes the configuration registers 136.

[0024] In this example, the selection circuit 106 includes an address decoder 122 and activation logic 124. The address decoder 122 receives addresses and data through a data interface 126. The address decoder 122 is electrically coupled to the activation logic 124. The activation logic 124 receives firing signals through a firing interface 128. Each memory cell 1040 to 104 N is electrically coupled to the write circuit 130 through a sensing interface 134. The sensor 132 is electrically coupled to the control logic 108 and to the sensing interface 134 through a signal path 131.

[0025] An address decoder 122 selects fluid actuation devices 1020 through 102 N and memory cells 1040 through 104 N corresponding to the selected fluid actuation devices 1020 through 102 N in response to an address. The address can be received through a data interface 126. Activation logic 124 activates the selected fluid actuation devices 1020 through 102 N and memory cells 1040 through 104 N corresponding to the selected fluid actuation devices 1020 through 102 N based on a data signal and a firing signal. The data signal can include nozzle data indicating which fluid actuation device(s) to select for the provided address. The data signal can be received through the data interface 126. The firing signal indicates when the selected fluid actuation devices are activated (i.e., fired) or when the corresponding memory cells are accessed. The firing signal can be received through a firing interface 128. Each of the data interface 126, the firing interface 128, and a sensing interface 134 can be a contact pad, a pin, a bump, a wire, or other suitable electrical interface for transmitting signals to and / or from the integrated circuit 120. Each of the interfaces 126, 128, and 134 can be electrically coupled to a fluid ejection system (e.g., a host printing device, such as the fluid ejection system 500 described below with reference to Figure 7

[0026] A configuration register 136 stores data for enabling or disabling access to the plurality of memory cells 1040 through 104 N . The control logic 108 activates the selected fluid actuation devices 1020 through 102 N or accesses the memory cells 1040 through 104 N corresponding to the selected fluid actuation devices 1020 through 102 N based on the data stored in the configuration register 136. In one example, the configuration register 136 also stores data for enabling write access or read access to the plurality of memory cells 1040 through 104 N . In another example, the configuration register 136 also stores data for enabling or disabling the sensor 132.

[0027] ​Configuration register 136 may be a memory device (e.g., non-volatile memory, shift register, etc.) and may include any suitable number of bits (e.g., 4 bits to 24 bits, such as 12 bits). In some examples, configuration register 136 may also store configuration data for testing integrated circuit 120, detecting cracks in the substrate of integrated circuit 120, enabling timers of integrated circuit 120, setting analog delays of integrated circuit 120, verifying the operation of integrated circuit 120, or configuring other functions of integrated circuit 120.

[0028] When the selected memory cell is 1040 to 104 N When accessed via control logic 108, the memory stored in memory cells 1040 to 104 can be read via sensing interface 134. N The data in the memory. Additionally, when the selected memory cells are 1040 to 104... N When accessed via control logic 108, write circuitry 130 can write data to the selected memory cell. Sensor 132 can be a junction device (e.g., a thermal diode), a resistive device (e.g., a crack detector), or another suitable device for sensing the state of integrated circuit 120. Sensor 132 can be read via sensing interface 134.

[0029] Figure 2 This is a schematic diagram illustrating an example of a circuit 200 used to drive multiple fluid actuation devices or access corresponding memory cells. In one example, circuit 200 is... Figure 1A Integrated circuit 100 or Figure 1B This is part of integrated circuit 120. Circuit 200 illustrates a set of 16 fluid actuators and a corresponding set of 16 memory cells. Integrated circuits (such as...) Figure 1A Integrated circuit 100 or Figure 1B The integrated circuit 120 may include any suitable number of fluid actuation devices and corresponding memory cells. Although Figure 2 The diagram illustrates a group of 16 actuating devices and their corresponding memory units, but in other examples, the number of fluid actuating devices and their corresponding memory units within each group can vary.

[0030] Circuit 200 includes multiple fluid actuation devices 2020 to 202 15 Multiple memory cells 2040 to 204 15 Including logic gates 2220 to 222 15 The address decoder includes logic gates 227 and 2240 to 224. 15activation logic, write circuitry including memory write voltage regulator 230, transistors 238 and 240, and contact (e.g., sense) pad 241. A first input of logic gate 227 receives nozzle data through nozzle data signal path 226. A second input of logic gate 227 receives fire signal through fire signal path 228. An output of logic gate 227 is electrically coupled to a first input of each logic gate 2240 through signal path 229. Each logic gate 2240 through 224 15 through 222 15 An input of each logic gate 2220 through 222 15 through 222 15 An output of each logic gate 2220 through 222 15 through 222 15 through 222 15 through 222 15 through 222 15 .

[0031] Each fluid actuation device 2020 through 202 15 includes logic gate 208, transistor 210, and fire resistor 212. Although fluid actuation device 2020 is illustrated and described herein, other fluid actuation devices 2021 through 202 15 include similar circuitry. A first input of logic gate 208 is electrically coupled to signal path 2250. A second input (inverted) of logic gate 208 receives memory enable signal through memory enable signal path 207. An output of logic gate 208 is electrically coupled to a gate of transistor 210 through signal path 209. One side of a source-drain path of transistor 210 is electrically coupled to a common or ground node 214. Another side of the source-drain path of transistor 210 is electrically coupled to one side of fire resistor 212 through signal path 211. Another side of fire resistor 212 is electrically coupled to a power supply voltage node (e.g., VPP) 215.

[0032] Each memory cell 2040 through 204 15 includes transistors 216 and 218 and floating gate transistor 220. Although memory cell 2040 is illustrated and described herein, other memory cells 2041 through 204 15including similar circuitry. The gate of transistor 216 is electrically coupled to signal path 2250. One side of the source-drain path of transistor 216 is electrically coupled to the common or ground node 214. The other side of the source-drain path of transistor 216 is electrically coupled through signal path 217 to one side of the source-drain path of transistor 218. The gate of transistor 218 receives a memory enable signal through memory enable signal path 207. The other side of the source-drain path of transistor 218 is electrically coupled through signal path 219 to one side of the source-drain path of floating gate transistor 220. The other side of the source-drain path of floating gate transistor 220 is electrically coupled through signal path 234 to one side of the source-drain path of memory write voltage regulator 230 and transistor 238.

[0033] The memory write voltage regulator 230 receives a memory write signal through memory write signal path 232. The gate of transistor 238 and the gate of transistor 240 receive a memory read signal through memory read signal path 236. The other side of the source-drain path of transistor 238 is electrically coupled through signal path 239 to one side of the source-drain path of transistor 240. The other side of the source-drain path of transistor 240 is electrically coupled to sense pad 241.

[0034] The nozzle data signal on nozzle data signal path 226, the fire signal on fire signal path 228, and the address signal on address signal path 221 are used to activate fluid actuation devices 2020 through 202 15 or corresponding memory cells 2040 through 204 15 The memory enable signal on memory enable signal path 207 determines whether fluid actuation devices 2020 through 202 15 or corresponding memory cells 2040 through 204 15 are activated or accessed. In response to a logic high memory enable signal, transistor 218 is turned on to enable access to memory cells 2040 through 204 15 In addition, in response to a logic high memory enable signal, logic gate 208 outputs a logic low signal to turn off transistor 210 to prevent any fluid actuation devices 2020 through 202 15 from firing in response to a fire signal passed to signal paths 2250 through 225 15 In response to a logic low memory enable signal, transistor 218 is turned off to disable access to memory cells 2040 through 204 15 In addition, in response to a logic low memory enable signal, logic gate 208 allows a fire signal to pass to signal paths 2250 through 225 15 to fire fluid actuation devices 2020 through 202 15In one example, the memory enable signal is based on a data bit stored in a configuration register (e.g., configuration register 136) of the circuit 200. In another example, the memory enable signal is based on a data bit received by the circuit 200 along with the address and nozzle data, which is used by the configuration logic (e.g., configuration logic 110) to enable or disable the memory cells 2040-204 Figure 1B . Figure 1A 15 .

[0035] The nozzle data signal indicates whether the fluid actuation device 2020-202 15 or the corresponding memory cell 2040-204 15 is to be selected. In one example, the nozzle data signal includes a logic high signal to select the fluid actuation device 2020-202 15 or the corresponding memory cell 2040-204 15 and a logic low signal to deselect the fluid actuation device 2020-202 15 or the corresponding memory cell 2040-204 15 . In response to a logic high nozzle data signal, the logic gate 227 passes a logic high signal to the signal path 229 in response to a logic high fire signal. In response to a logic low nozzle data signal or a logic low fire signal, the logic gate 227 passes a logic low signal to the signal path 229.

[0036] The address signal selects one of the fluid actuation devices 2020-202 15 or the corresponding memory cells 2040-204 15 . In response to the address signal, one of the logic gates 2220-222 15 passes a logic high signal to the corresponding signal path 2230-223 15 . The other logic gates 2220-222 15 pass a logic low signal to the corresponding signal path 2230-223 15 .

[0037] In response to a logic high signal on the signal path 229 and a logic high signal on the corresponding signal path 2230-223 15 , each of the logic gates 2240-224 15 passes a logic high signal to the corresponding signal path 2250-225 15 . In response to a logic low signal on the signal path 229 or a logic low signal on the corresponding signal path 2230-223 15 , each of the logic gates 2240-224 15 passes a logic low signal to the corresponding signal path 2250-225 15 ​. Thus, in response to a logic low memory enable signal and a logic high signal on signal paths 2250 to 225 15 , the corresponding fluid actuation device 2020 to 202 15 is fired by activating the corresponding firing resistor 212. In response to a logic high memory enable signal and a logic high signal on signal paths 2250 to 225 15 , the corresponding memory cell 2040 to 204 15 is selected for access.

[0038] As the memory cells 2040 to 204 15 are selected for access, a memory write voltage regulator 230 can be enabled by a memory write signal on a memory write signal path 232 to apply a voltage to a signal path 234 to write a data bit to the floating gate transistor 220. Additionally, as the memory cells 2040 to 204 15 are selected for access, transistors 238 and 240 can be turned on in response to a memory read signal on a memory read signal path 236. As the transistors 238 and 240 are turned on, the data bit stored in the floating gate transistor 220 can be read by a sense pad 241 (e.g., by a host printing device coupled to the sense pad 241). In one example, the memory write signal and the memory read signal are based on data stored in a configuration register (e.g., configuration register 136). In another example, the memory write signal and the memory read signal are based on data received by the circuit 200 along with an address and nozzle data, which are used by configuration logic (e.g., configuration logic 110) to activate a read signal or a write signal. Figure 1B Figure 1A

[0039] Figure 3A is a block diagram illustrating one example of an integrated circuit 300 for accessing memory associated with a fluid ejection device. In this example, the fluid actuation devices can be located on a separate integrated circuit from the memory. The integrated circuit 300 includes a plurality of memory cells 3040 to 304 N , an address decoder 322, activation logic 324, and configuration logic 310. Each memory cell 3040 to 304 N is respectively accessed through signal paths 3030 to 303 N ​​Electrically coupled to activation logic 324. Activation logic 324 is electrically coupled to address decoder 322, electrically coupled to configuration logic 310 via signal path 309, and receives activation signals via activation interface 328. Address decoder 322 receives data signals via data interface 326. Each of data interface 326 and activation interface 328 may be a contact pad, pin, bump, wire, or other suitable electrical interface for transmitting signals to and / or from integrated circuit 300. Each of interfaces 326 and 328 may be electrically coupled to a fluid jetting system (e.g., a host printing device).

[0040] In one example, each memory cell is 3040 to 304. N This includes non-volatile memory cells (e.g., floating-gate transistors, programmable fuses, etc.). Address decoder 322 selects memory cells 3040 to 304 in response to an address. N The address can be received via data interface 326. Activation logic 324 activates selected memory cells 3040 to 304 based on the data signal on data interface 326 and the activation signal on activation interface 328. N Configuration logic 310 enables or disables multiple memory cells 3040 to 304. N Access.

[0041] Figure 3B This is a block diagram illustrating another example of an integrated circuit 320 for accessing memory associated with a fluid jetting device. Integrated circuit 320 includes a plurality of memory cells 3040 to 304... N Address decoder 322 and activation logic 324. Additionally, integrated circuit 320 includes write circuitry 330 and configuration register 336. In one example, Figure 3A The configuration logic 310 of the integrated circuit 300 includes a configuration register 336. Each memory cell 3040 to 304 N It is electrically coupled to the write circuit 330 through the sensing interface 334.

[0042] Configuration register 336 can store information for enabling or disabling multiple memory cells 3040 to 304. N The data accessed. Additionally, configuration register 336 can store data used to enable access to multiple memory cells 3040 to 3044. N The sensor interface 334 provides a single interface coupled to a plurality of memory cells 3040 to 3044. This allows for write access or read access of data. N Each of these interfaces is connected to a single contact point on the host printing device. In one example, the sensing interface 334 includes a single contact pad.

[0043] When selected memory cells 3040-304 N have been accessed by address decoder 322 and activation logic 324, data stored in memory cells 3040-304 N may be read through sense interface 334. Additionally, when selected memory cells 3040-304 N have been accessed by address decoder 322 and activation logic 324, write circuit 330 can write data to selected memory cells 3040-304 N .

[0044] Figure 4A FIG. 1 illustrates one example of a fluid ejection die 400, and Figure 4B FIG. 2 illustrates a magnified view of an end of fluid ejection die 400. In one example, fluid ejection die 400 includes integrated circuit 100 of Figure 1A , integrated circuit 120 of Figure 1B , or circuit 200 of Figure 2 . Die 400 includes a first column of contact pads 402, a second column of contact pads 404, and a column 406 of fluid actuation devices 408. Second column of contact pads 404 is aligned with and a distance (i.e., along the Y-axis) from first column of contact pads 402. Column 406 of fluid actuation devices 408 is arranged longitudinally with respect to first column of contact pads 402 and second column of contact pads 404. Column 406 of fluid actuation devices 408 is also arranged between first column of contact pads 402 and second column of contact pads 404. In one example, fluid actuation devices 408 are nozzles or fluid pumps for ejecting droplets.

[0045] In one example, first column of contact pads 402 includes six contact pads. First column of contact pads 402 can include, in order, a data contact pad 410, a clock contact pad 412, a logic power ground return contact pad 414, a multipurpose input / output (e.g., sense) contact pad 416, a first high voltage power supply contact pad 418, and a first high voltage power ground return contact pad 420. Thus, first column of contact pads 402 includes data contact pad 410 at a top of first column 402, first high voltage power ground return contact pad 420 at a bottom of first column 402, and first high voltage power supply contact pad 418 directly above first high voltage power ground return contact pad 420. Although contact pads 410, 412, 414, 416, 418, and 420 are illustrated in a particular order, in other examples, the contact pads can be arranged in a different order.

[0046] In one example, the second column of contact pads 404 includes six contact pads. The second column of contact pads 404 can include, in order, the following contact pads: a second high-voltage power ground return contact pad 422, a second high-voltage power supply contact pad 424, a logic reset contact pad 426, a logic power supply contact pad 428, a mode contact pad 430, and a fire contact pad 432. Thus, the second column of contact pads 404 includes the second high-voltage power ground return contact pad 422 at the top of the second column 404, the second high-voltage power supply contact pad 424 directly below the second high-voltage power ground return contact pad 422, and the fire contact pad 432 at the bottom of the second column 404. Although the contact pads 422, 424, 426, 428, 430, and 432 are illustrated in a particular order, in other examples, the contact pads can be arranged in a different order.

[0047] The data contact pads 410 (e.g., Figure 1B of the data interface 126) can be used to input serial data to the die 400 for selecting a fluid actuation device (e.g., via Figure 1B of the selection circuit 106), a memory bit (e.g., via Figure 1B of the selection circuit 106), a thermal sensor, a configuration mode (e.g., via Figure 1B of the configuration register 136), etc. The data contact pads 410 can also be used to output serial data from the die 400 for reading a memory bit, a configuration mode, status information, etc. The clock contact pads 412 can be used to input a clock signal to the die 400 to shift serial data on the data contact pads 410 into the die or to shift serial data out of the die to the data contact pads 410. The logic power ground return contact pads 414 provide a ground return path for logic power (e.g., about 0 V) supplied to the die 400. In one example, the logic power ground return contact pads 414 are electrically coupled to a semiconductor (e.g., silicon) substrate 440 of the die 400. The multipurpose input / output contact pads 416 (e.g., Figure 1B of the sensing interface 134 or Figure 2 of the sensing pads 241) can be used for analog sensing and / or digital test modes of the die 400. In one example, the multipurpose input / output contact pads 416 can be electrically coupled to Figure 1B each memory cell 1040 to 104 N , write circuit 130, and sensor 132.

[0048] The first high voltage power supply contact pad 418 and the second high voltage power supply contact pad 424 can be used to supply high voltage (e.g., about 32V) to the die 400. The first high voltage power ground return contact pad 420 and the second high voltage power ground return contact pad 422 can be used to provide a power ground return (e.g., about 0V) for the high voltage power supply. The high voltage power ground return contact pads 420 and 422 are not directly electrically connected to the semiconductor substrate 440 of the die 400. The particular contact pad order of the high voltage power supply contact pads 418 and 424 and the high voltage power ground return contact pads 420 and 422 as the innermost contact pads can improve power delivery to the die 400. Having the high voltage power ground return contact pads 420 and 422 at the bottom of the first column 402 and the top of the second column 404, respectively, can improve reliability of manufacturing and can improve ink short protection.

[0049] The logic reset contact pad 426 can be used as a logic reset input to control an operational state of the die 400. The logic power supply contact pad 428 can be used to supply logic power (e.g., between about 1.8V and 15V, such as 5.6V) to the die 400. The mode contact pad 430 can be used as a logic input to control access to enable / disable a configuration mode (i.e., a functional mode) of the die 400. The fire contact pad 432 (e.g., of the fire interface 128 of the Figure 1B The fire contact pad 432 (e.g., of the fire interface 128 of the

[0050] The die 400 includes an elongate substrate 440 having a length 442 (along the Y-axis), a thickness 444 (along the Z-axis), and a width 446 (along the X-axis). In one example, the length 442 is at least twenty times the width 446. The width 446 can be 1 mm or less, and the thickness 444 can be less than 500 microns. The fluid actuation device 408 (e.g., fluid actuation logic) and the contact pads 410-432 are provided on the elongate substrate 440 and arranged along the length 442 of the elongate substrate. The fluid actuation device 408 has a strip length 452 that is less than the length 442 of the elongate substrate 440. In one example, the strip length 452 is at least 1.2 cm. The contact pads 410-432 can be electrically coupled to the fluid actuation logic. The first column of contact pads 402 can be arranged near a first longitudinal end 448 of the elongate substrate 440. The second column of contact pads 404 can be arranged near a second longitudinal end 450 of the elongate substrate 440 opposite the first longitudinal end 448.

[0051] Figure 5A illustrates (as Figure 4A and Figure 4B(Another example of the fluid jetting die 400) A magnified view of the central portion of the fluid jetting die 400a. As previously referenced Figure 4A and Figure 4B As described, the fluid jet die 400a includes a plurality of nozzles 408 arranged in a row along the length of an elongated substrate 440. Additionally, the fluid jet die 400 includes a plurality of memory cells arranged in a group 460 adjacent to the plurality of nozzles 408. Figure 5B As illustrated, each group of 460 memory cells may include a first memory cell 4620 and a second memory cell 4621. Each memory cell 462 corresponds to a nozzle 408. As previously described, the fluid actuation logic of the fluid jet die 400 either jets fluid from the selected nozzle 408 or accesses the memory cell 462 corresponding to the selected nozzle 408.

[0052] In one example, each of the plurality of nozzles 408 has a corresponding memory cell 462. In another example, every other nozzle 408 has a corresponding memory cell 462. In yet another example, the plurality of memory cells may include a single memory cell 462 corresponding to each nozzle 408. In yet another example, the plurality of memory cells may include at least two memory cells 462 corresponding to each nozzle 408. The plurality of memory cells 462 may be arranged into a plurality of groups 460, wherein each group 460 includes at least two memory cells 462. The plurality of groups 460 are spaced apart from each other along the length of the elongated substrate 440.

[0053] Figure 6A The illustration shows (as) Figure 4A and Figure 4B (Another example of the fluid jet die 400) An enlarged view of the central portion of the fluid jet die 400b. The fluid jet die 400b includes a plurality of nozzles 408a arranged in a first column along the length of an elongated substrate 440 and a plurality of nozzles 408b arranged in a second column along the length of the elongated substrate 440. The first column is adjacent to the second column. The nozzles 408a in the first column may be offset relative to the nozzles 408b in the second column. In addition, the fluid jet die 400b includes a plurality of memory cells arranged in groups 470 adjacent to the plurality of nozzles 408a and 408b. The groups 470 are spaced apart from each other along the length of the elongated substrate 440.

[0054] like Figure 6B As illustrated, each group 470 may include six memory cells arranged in three banks 4821 to 4823. The first bank 4821 includes a first memory cell 472. 1-0 Second memory unit 472 1-1The second bank 4822 includes first memory cells 472 2-0 and second memory cells 472 2-1 The third bank 4823 includes first memory cells 472 3-0 and second memory cells 472 3-1 Each bank 4821-4823 can be selected in response to a bank enable signal on a bank enable signal path 4801-4803, respectively.

[0055] In one example, the plurality of memory cells includes three memory cells 472 corresponding to each nozzle 408a and / or 408b. A first memory cell (e.g., memory cell 472 1-0 ) corresponding to each nozzle is arranged into a first memory cell bank (e.g., bank 4821), a second memory cell (e.g., memory cell 472 2-0 ) corresponding to each nozzle is arranged into a second memory cell bank (e.g., bank 4822), and a third memory cell (e.g., memory cell 472 3-0 ) corresponding to each nozzle is arranged into a third memory cell bank (e.g., bank 4823). Fluid actuation logic ejects fluid from a selected nozzle 408a and / or 408b or accesses a memory cell 472 corresponding to the selected nozzle and the selected memory cell bank.

[0056] In one example, the first, second, and third bank enable signals are based on data stored in a configuration register (e.g., configuration register 136 of Figure 1B ). In another example, the first, second, and third bank enable signals are based on data received by the fluid ejection die 400b along with an address and nozzle data, which are used by configuration logic (e.g., configuration logic 110 of Figure 1A ) to enable a selected bank 4821-4823.

[0057] Figure 7 is a block diagram illustrating one example of a fluid ejection system 500. The fluid ejection system 500 includes fluid ejection assemblies, such as a printhead assembly 502, and fluid supply assemblies, such as an ink supply assembly 510. In the illustrated example, the fluid ejection system 500 also includes a service station assembly 504, a carriage assembly 516, a print media transport assembly 518, and an electronic controller 520. Although the following description provides examples of systems and assemblies for fluid handling with respect to ink, the disclosed systems and assemblies are also applicable to handling fluids other than ink.

[0058] The printhead assembly 502 includes the previously referenced Figure 4A and Figure 4BThe described and illustrated at least one printhead or fluid ejection die 400 ejects drops of ink or fluid through a plurality of orifices or nozzles 408. In one example, the drops are directed toward a media, such as print media 524, to print onto the print media 524. In one example, the print media 524 includes any type of suitable sheet material, such as paper, cardstock, transparency film, Mylar, fabric, etc. In another example, the print media 524 includes media for three-dimensional (3D) printing, such as a powder bed, or media for bioprinting and / or drug discovery testing, such as reservoirs or containers. In one example, the nozzles 408 are arranged in at least one column or array such that proper sequential ejection of ink from the nozzles 408 causes characters, symbols, and / or other graphics or images to be printed on the print media 524 as the printhead assembly 502 and the print media 524 are moved relative to each other.

[0059] The ink supply assembly 510 supplies ink to the printhead assembly 502 and includes a reservoir 512 for storing ink. Thus, in one example, ink flows from the reservoir 512 to the printhead assembly 502. In one example, the printhead assembly 502 and the ink supply assembly 510 are housed together in an inkjet or fluid ejection print cartridge or pen. In another example, the ink supply assembly 510 is separate from the printhead assembly 502 and supplies ink to the printhead assembly 502 through an interface connection 513, such as a supply tube and / or valve.

[0060] The carriage assembly 516 positions the printhead assembly 502 relative to the print media transport assembly 518, and the print media transport assembly 518 positions the print media 524 relative to the printhead assembly 502. Thus, a print zone 526 is defined as the area adjacent to the nozzles 408 in between the printhead assembly 502 and the print media 524. In one example, the printhead assembly 502 is a scanning printhead assembly such that the carriage assembly 516 moves the printhead assembly 502 relative to the print media transport assembly 518. In another example, the printhead assembly 502 is a non-scanning printhead assembly such that the carriage assembly 516 fixes the printhead assembly 502 at a prescribed position relative to the print media transport assembly 518.

[0061] The service station assembly 504 provides for priming, wiping, capping, and / or priming of the printhead assembly 502 to maintain the printhead assembly 502, and more specifically the nozzles 408, in operation. For example, the service station assembly 504 can include a rubber blade or wiper that is periodically passed over the printhead assembly 502 to wipe and clean excess ink from the nozzles 408. Additionally, the service station assembly 504 can include a cap that covers the printhead assembly 502 for protection of the nozzles 408 from drying out during periods of non-use. Additionally, the service station assembly 504 can include an inkwell into which the printhead assembly 502 ejects ink during priming to ensure that the reservoir 512 maintains an appropriate level of pressure and fluidity, and to ensure that the nozzles 408 do not become clogged or leak. The functions of the service station assembly 504 can include relative motion between the service station assembly 504 and the printhead assembly 502.

[0062] The electronic controller 520 communicates with the printhead assembly 502 through a communication path 503, with the service station assembly 504 through a communication path 505, with the carriage assembly 516 through a communication path 517, and with the print media transport assembly 518 through a communication path 519. In one example, the electronic controller 520 and the printhead assembly 502 can communicate through the carriage assembly 516 via a communication path 501 when the printhead assembly 502 is installed in the carriage assembly 516. The electronic controller 520 can also communicate with the ink supply assembly 510 so that, in one implementation, a new (or used) ink supply can be detected.

[0063] The electronic controller 520 receives data 528 from a host system, such as a computer, and can include memory for temporarily storing the data 528. The data 528 can be sent to the fluid ejection system 500 along an electronic, infrared, optical, or other information transfer path. The data 528 represents, for example, a document and / or file to be printed. Thus, the data 528 forms a print job for the fluid ejection system 500 and includes at least one print job command and / or command parameter.

[0064] In one example, the electronic controller 520 provides control of the printhead assembly 502, including timing control for ejection of drops of ink from the nozzles 408. Thus, the electronic controller 520 defines a pattern of ejected drops of ink that form characters, symbols, and / or other graphics or images on the print media 524. The timing control, and thus the pattern of ejected drops of ink, is determined by the print job command and / or command parameter. In one example, logic and drive circuitry forming part of the electronic controller 520 is located on the printhead assembly 502. In another example, logic and drive circuitry forming part of the electronic controller 520 is located off the printhead assembly 502.

[0065] Although specific examples have been illustrated and described herein, various alternatives and / or equivalents can be substituted for the specific examples shown and described without departing from the scope of the disclosure. This application is intended to cover any alternatives, modifications and equivalents of the specific examples discussed herein. Therefore, the disclosure is intended to be limited only by the claims and their equivalents.

Claims

1. An integrated circuit for accessing memory associated with fluid ejection devices, the integrated circuit comprising: a plurality of memory cells; an address decoder for selecting a memory cell in response to an address; activation logic for activating the selected memory cell based on a data signal and a fire signal; and configuration logic for enabling or disabling access to the plurality of memory cells. the configuration logic comprises a configuration register that stores data for enabling or disabling access to the plurality of memory cells, and 2. The integrated circuit of claim 1, wherein, wherein the configuration register stores data for enabling write access or read access to the plurality of memory cells. the configuration register stores data for enabling or disabling the sensor.

3. The integrated circuit of claim 2, further comprising a sensor, wherein, 4. The integrated circuit of any of claims 1 to 3, further comprising: a single interface coupled to each of the plurality of memory cells, the single interface for connecting to a single contact of a host printing device.

5. The integrated circuit of claim 4, further comprising: a write circuit coupled to the single interface, the write circuit for writing data to the memory cells. each memory cell comprises a non-volatile memory cell.

6. The integrated circuit of any one of claims 1 to 3, wherein, the single interface comprises a single contact pad.

7. The integrated circuit of claim 4, wherein, the activation logic comprises a first logic gate and a set of second logic gates.

8. The integrated circuit of any one of claims 1 to 3, wherein, a first input of the first logic gate is the data signal, a second input of the first logic gate is the fire signal, and the first logic gate is electrically coupled to a first input of each of the second logic gates.

9. The integrated circuit of claim 8, wherein, the address decoder comprises a set of third logic gates, an input of each of the third logic gates is the address, and an output of each of the third logic gates is electrically coupled to a second input of a corresponding one of the second logic gates.

10. The integrated circuit of claim 8, wherein, an output of each second logic gate is electrically coupled to a respective memory cell through a signal path.

11. The integrated circuit of claim 8, wherein, the output of each second logic gate is electrically coupled to a respective fluid actuation device through the signal path.

12. The integrated circuit of claim 11, wherein, each of the plurality of memory cells comprises a first transistor and a second transistor, a gate of each first transistor is electrically coupled to a respective signal path.

13. The integrated circuit of claim 11, wherein, a gate of each second transistor receives a memory enable signal through a memory signal enable path.

14. The integrated circuit of claim 13, wherein, a logic high data signal selects a memory cell, and a logic high memory enable signal turns on a respective second transistor to enable access to the memory cell.

15. The integrated circuit of claim 14, wherein, ​

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