A simulation method, device and storage medium for the working stress of a storage chip

Abstract

The present invention relates to the technical field of working stress simulation of storage chips, and discloses a method, device and storage medium for simulating the working stress of storage chips, including the following steps: S1: The test platform system obtains the basic information of the storage chip; S2: The storage chip is partitioned according to requirements, and the working stress application area and the non-working stress application area are divided; S3: The test platform system extracts an algorithm from the algorithm library and allocates it to the working stress application area; S4: The working stress application area simulates and controls the parameter configuration of the storage chip through the test platform system; S5: The working stress application area obtains the drive configuration from the drive library according to the basic information of the storage chip through the test platform system; S6: After passing through the drive configuration in S5, the test platform system performs working stress simulation on the working stress application area. By dividing the storage chip into a working stress application area and a non-working stress application area, the sensitivity of different areas of the storage chip to stress is tested.

Description

Technical Field

[0001] The present invention relates to the technical field of working stress simulation of storage chips, and particularly relates to a method, device and storage medium for simulating the working stress of storage chips. Background Art

[0002] The lifespan of a storage chip can be used for many years in an ideal environment. However, we cannot wait until the storage chip fails several years later to study the failure mechanism. Therefore, it is necessary to apply stress to the storage chip to accelerate the exposure of potential defects of the storage chip, so as to better study the failure mechanism of the storage chip.

[0003] Generally, the stress includes environmental stresses such as magnetic field stress, electrical stress, and temperature stress applied to the chip. Most of the existing technologies also test the reliability of storage chips under environmental stresses. However, with the development of new energy vehicle technology, in a more complex environment, there are higher requirements for the reliability of storage chips. The existing tests of storage chips do not have clear requirements for the working load of the storage chips, and the exposure speed of potential defects of the storage chips is relatively slow. And due to different usage scenarios of the storage chips, their working loads are also different. If the working load of the storage chip is relatively low, even if the above environmental stresses are applied, it may not be possible to expose the potential defects of the storage chip. Summary of the Invention

[0004] In order to solve the problem that the working load of the storage chip is not considered in the test process of the reliability of the existing storage chip, the present invention provides a method, device and storage medium for simulating the working stress of the storage chip.

[0005] The technical solution of the present invention includes the following:

[0006] The present invention provides a method for simulating the working stress of a storage chip, which is implemented through a test platform system and includes the following steps:

[0007] S1: The test platform system obtains the basic information of the storage chip;

[0008] S2: Partition the storage chip according to requirements, and divide the working stress application area and the non-working stress application area;

[0009] S3: The test platform system extracts an algorithm from the algorithm library and assigns it to the working stress application area;

[0010] S4: The working stress application area simulates and controls the parameter configuration of the storage chip through the test platform system;

[0011] S5: The working stress application area obtains the drive configuration from the drive library according to the basic information of the storage chip through the test platform system;

[0012] S6: After being configured by the drive in S5, the test platform system performs a working stress simulation on the working stress application area.

[0013] Further, S1 includes:

[0014] The basic information of the storage chip is described by text or code that can be read and parsed by the test platform system;

[0015] The basic information of the storage chip includes, but is not limited to, the storage chip name, page size, sector size, communication rate, communication protocol, and storage capacity.

[0016] Further, S2 includes:

[0017] The working stress application areas divided by the storage chip include one or more.

[0018] Further, S3 includes:

[0019] The test platform system allocates one or more algorithms to the working stress application areas according to the working load status of the storage chip.

[0020] Further, S3 further includes:

[0021] The algorithm library includes various operation algorithms for the storage chip, including but not limited to positive and reverse checkerboard algorithms.

[0022] Further, S4 includes:

[0023] The simulation control of the parameter configuration of the storage chip includes setting the number of loops, loop time, and area execution order of the algorithm combination in each working stress application area.

[0024] Further, S5 includes:

[0025] The working stress application area searches for the corresponding driver program from the driver library by the test platform system according to the name of the storage chip.

[0026] The present invention provides a simulation device for the working stress of a storage chip, including:

[0027] A memory for storing a computer program;

[0028] A processor for implementing the steps of the simulation method for the working stress of the storage chip described in any one of the above when executing the computer program.

[0029] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the simulation method for the working stress of the storage chip described in any one of the above are implemented.

[0030] The beneficial effects of the present invention include: by dividing the storage chip into a working stress application area and a non-working stress application area, testing the sensitivity of different areas of the storage chip to stress, and through flexible configuration of the working stress application area allocation algorithm and the driver program, the working load of the storage chip is controllable and adjustable. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic flowchart of a simulation method for the working stress of a storage chip provided by the present invention.

[0032] Figure 2 It is a schematic diagram of the division of the working stress application area of a simulation method for the working stress of a storage chip provided by the present invention.

[0033] Figure 3 It is a schematic diagram of an example division of the working stress application area of a simulation method for the working stress of a storage chip provided by the present invention.

[0034] Figure 4 It is a schematic diagram of the algorithm allocation of a simulation method for the working stress of a storage chip provided by the present invention.

[0035] Figure 5 It is a schematic diagram of the parameter configuration of a simulation method for the working stress of a storage chip provided by the present invention.

[0036] Figure 6 It is a schematic diagram of the driver configuration of a simulation method for the working stress of a storage chip provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0038] Combined with Figure 1 As shown, the present invention provides a simulation method for the working stress of a storage chip, which is implemented through a test platform system and includes the following steps:

[0039] S1: The test platform system obtains the basic information of the storage chip;

[0040] S2: Partition the storage chip according to requirements, and divide the working stress application area and the non - working stress application area;

[0041] S3: The test platform system extracts algorithms from the algorithm library and allocates them to the working stress application area;

[0042] S4: The working stress application area simulates and controls the parameter configuration of the storage chip through the test platform system;

[0043] S5: The working stress application area obtains the drive configuration from the drive library according to the basic information of the storage chip through the test platform system;

[0044] S6: After the test platform system passes through the drive configuration in S5, it performs working stress simulation on the working stress application area.

[0045] Further, S1 includes:

[0046] The basic information of the storage chip is described by text or code that can be read and parsed by the test platform system;

[0047] The basic information of the storage chip includes, but is not limited to, the storage chip name, page size, sector size, communication rate, communication protocol, and storage capacity, and all of the basic information can be obtained from the storage chip manual.

[0048] Further, S2 includes:

[0049] The working stress application area divided on the storage chip includes one or more.

[0050] As Figure 2 shown, when partitioning the storage chip, one area or multiple areas can be divided, and the divided areas are regarded as the areas to be tested for applying working stress. When divided into one area, the area to be tested can be the entire area or a part of the storage chip; when divided into multiple areas, at this time, the area to be tested can be formed by dividing the entire storage chip into multiple areas, or can be formed by dividing a part of the storage chip into multiple areas. The area to be tested is used to apply working stress for testing, and the other remaining areas of the storage chip can be regarded as invalid areas.

[0051] The working stress application area on the storage chip is artificially defined. Determine the area for applying working stress according to requirements. For example, when testing 10% of the space of a storage chip with a capacity of 1GB, only need to apply working stress from the start of the storage chip to the space of 1GB×10%.

[0052] As Figure 3As shown, the storage capacity of the storage chip is 1 GB. If the working stress application area requirement is between 25% and 50% of the entire storage space, then the starting position corresponding to the working stress application area is 1 GB × 25%, and the ending position is 1 GB × 50%.

[0053] Further, the S3 includes:

[0054] The test platform system allocates one or more algorithms to the working stress application area according to the working load status of the storage chip.

[0055] The algorithm library is stored in the test platform system. As Figure 4 shown, according to the test requirements, if the test requires the storage chip to work in a low load state, the test platform system can allocate a simple algorithm. If the test requires the storage chip to work in a higher load state, the test platform system allocates a combination of multiple complex algorithms.

[0056] The algorithm library refers to a warehouse of algorithms. The warehouse contains various operation algorithms for the storage chip, including but not limited to the positive and negative checkerboard algorithms, or algorithms customized by the test object according to its own needs.

[0057] Further, the S3 also includes:

[0058] The algorithm library includes various operation algorithms for the storage chip, including but not limited to the positive and negative checkerboard algorithms.

[0059] Further, the S4 includes:

[0060] The analog control of the parameter configuration of the storage chip includes setting the number of cycles, cycle time, and area execution order of the algorithm combination in each working stress application area, as Figure 5 shown.

[0061] The test platform system includes a computer and a test board. The storage chip is set on the test board. The computer is connected to the test board through a data cable. The computer selects the working stress application area to configure the parameters of the storage chip for analog control, and then outputs them to the test board through the data cable. The test board applies the working stress to the storage chip according to the configuration information.

[0062] The test board is provided with structures such as a CPU, a memory, an indicator light, and a power supply circuit.

[0063] Further, the S5 includes:

[0064] The working stress application area searches for the corresponding driver program from the driver library through the test platform system according to the name of the storage chip.

[0065] The driver is the driver program of the storage chip. It is a software program developed by developers for different types of storage chips, thus forming a driver library. Figure 6 As shown, the working stress application area searches for the corresponding driver from the driver library according to the name of the storage chip. After completing the driver configuration, the test platform system starts the working stress simulation test of the storage chip.

[0066] The present invention provides a device for simulating working stress of a storage chip, comprising:

[0067] Memory for storing computer programs;

[0068] A processor is used to implement the steps of any of the above-mentioned methods for simulating the working stress of a storage chip when executing the computer program.

[0069] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for simulating the working stress of a memory chip are implemented.

[0070] The parameter configuration of the memory chip is the information describing the memory chip for the test platform system, so that the test platform system can support the working stress test of memory chips of different types, interfaces and capacities. The driver library in the present invention is the corresponding driver developed by the developer for different types of memory chips, so that the implementation scheme provided by the present invention can realize the working stress test of different types of memory chips.

[0071] By dividing the test area of ​​the memory chip, the sensitivity of different areas of the memory chip to working stress can be tested and studied.

[0072] The algorithm combination of the test area divided by the memory chip is combined with the flexible configuration of the communication rate. According to the test requirements, for example, if the test requires the memory chip to work in a low-load state, a simple algorithm is assigned; if the test requires the memory chip to work in a higher-load state, a combination of multiple complex algorithms can be assigned. At the same time, the communication rate can be changed by a fixed algorithm to achieve controllable and adjustable workload of the memory chip.

[0073] The simulation method provided by the present invention can be applied to the performance test, function test and reliability test of the storage chip.

[0074] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A simulation method for the working stress of a storage chip, implemented through a test platform system, characterized in that: It includes the following steps: S1: The test platform system acquires the basic information of the storage chip; S2: Partition the storage chip according to requirements, and divide the working stress application area and the non-working stress application area; S3: The test platform system extracts algorithms from the algorithm library and assigns them to the working stress application area; S4: The working stress application area simulates and controls the parameter configuration of the storage chip through the test platform system; S5: The working stress application area obtains the driver configuration from the driver library according to the basic information of the storage chip through the test platform system; S6: After passing through the driver configuration of S5, the test platform system performs working stress simulation on the working stress application area; Among them, S3 includes: The test platform system assigns one or more algorithms to the working stress application area according to the working load state of the storage chip; S4 includes: The simulation control of the parameter configuration of the storage chip includes setting the number of cycles, cycle time, and area execution order of the algorithm combination in each working stress application area.

2. The simulation method of the working stress of a storage chip according to claim 1, characterized in that: S1 includes: The basic information of the storage chip is described by text or code that can be read and parsed by the test platform system; The basic information of the storage chip includes but is not limited to the storage chip name, page size, sector size, communication rate, communication protocol, and storage capacity.

3. The simulation method of the working stress of a storage chip according to claim 1, wherein: S2 includes: The working stress application area divided by the storage chip includes one or more.

4. A method for simulating the working stress of a storage chip according to claim 1, characterized in that: S3 also includes: The algorithm library includes various operation algorithms for storage chips, including but not limited to positive and reverse checkerboard algorithms.

5. The simulation method of the working stress of a storage chip according to claim 1, characterized in that: S5 includes: The working stress application area searches for the corresponding driver program from the driver library according to the name of the storage chip through the test platform system.

6. An analog device for the working stress of a storage chip, characterized in that: It includes: A memory for storing a computer program; A processor for implementing the steps of the simulation method of the working stress of the storage chip as described in any one of claims 1-5 when executing the computer program.

7. A computer-readable storage medium, on which a computer program is stored, characterized in that: When the computer program is executed by the processor, it implements the steps of the simulation method of the working stress of the storage chip as described in any one of claims 1-5.

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