A method for adjusting the height uniformity of active operable areas within a wafer

Abstract

The present invention provides a method for adjusting the height uniformity of active operable areas within a wafer. The wafer surface is divided into a central region and an edge region. The central region is provided with an active area structure spaced apart from each other. A pad oxide layer and a silicon nitride layer are sequentially provided on top of the active area structure. The central region and the edge region are both covered with silicon oxide. The silicon oxide is filled between the active area structures and covered with the silicon nitride layer. The silicon oxide above the active area structure is removed, and then the silicon nitride layer on the active area structure is removed, exposing the pad oxide layer on top of the active area structure. The pad oxide layer and silicon oxide in the central region of the wafer, as well as the silicon oxide in the edge region, are etched using hydrofluoric acid to reduce the height difference between the silicon oxide in the central region and the edge region. The present invention uses DHF to adjust the silicon oxide height inside and outside the wafer before the deep well ion implantation process, ensuring good uniformity of the silicon oxide height within the wafer and improving the silicon oxide height uniformity within the wafer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for adjusting the height uniformity of an active operable area in a wafer. Background Art

[0002] After the shallow trench isolation chemical mechanical polishing (STI-CMP) process in 14nm and below processes, there is a certain difference in the silicon oxide height inside and outside the wafer to ensure the morphology of the silicon oxide on the fin. This difference is transmitted to the vapor phase etch fin back process, resulting in poor fin height uniformity within the wafer after fin back. Process optimization is needed to improve fin height uniformity within the wafer.

[0003] Therefore, a new method needs to be proposed to solve the above problems. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for adjusting the height uniformity of the active operable area within a wafer, so as to solve the problem of poor height uniformity of silicon oxide within a wafer in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for adjusting the height uniformity of an active operable area within a wafer, comprising at least:

[0006] Step 1: Provide a wafer, wherein the wafer surface is divided into a central area and an edge area, wherein the central area is an area within a radius of 30 mm from the center of the wafer; the edge area is an annular area outside the radius of 30 mm from the center of the wafer; the central area is provided with active area structures spaced apart from each other; a pad oxide layer is provided on top of the active area structure; a silicon nitride layer is provided on the pad oxide layer; the central area and the edge area on the wafer are both covered with silicon oxide; the silicon oxide is filled between the active area structures and covers the silicon nitride layer;

[0007] Step 2: removing the silicon oxide above the active area structure by chemical mechanical polishing, and then removing the silicon nitride layer on the active area structure by phosphoric acid to expose the pad oxide layer on the top of the active area structure;

[0008] Step 3: using a hydrofluoric acid etchant to etch the silicon oxide in the shallow trench isolation region in the center area of ​​the wafer and the silicon oxide in the shallow trench isolation region in the edge area, so as to reduce the height difference between the silicon oxide in the shallow trench isolation region in the center area and the silicon oxide in the shallow trench isolation region in the edge area;

[0009] Step 4: performing well ion implantation on the wafer;

[0010] Step 5: Vapor-etching the silicon oxide and pad silicon oxide in the shallow trench isolation region to expose the top of the active area structure.

[0011] Preferably, the active region structure in step 1 is a silicon structure.

[0012] Preferably, in step 1, the active area structure on the wafer is divided into a sparse area and a dense area according to the density of its distribution.

[0013] Preferably, the top of the silicon oxide in step 1 has been planarized.

[0014] Preferably, after the hydrofluoric acid etching in step three, the height of the silicon oxide in the central region is 2 to 10 nm higher than that of the active area structure.

[0015] Preferably, the etching thickness of the silicon oxide in the central area and the edge area in step three is 0.3-3 nm.

[0016] Preferably, in step 3, the thickness of the silicon oxide etched in the central area is smaller than the thickness of the silicon oxide etched in the edge area.

[0017] Preferably, in step 3, the difference between the thickness of the silicon oxide etched in the central area and the thickness of the silicon oxide etched in the edge area is 0.4-1 nm.

[0018] Preferably, in step five, the silicon oxide in the central area is etched using a Certas vapor etching process.

[0019] As described above, the method of adjusting the height uniformity of the active operable area in the wafer of the present invention has the following beneficial effects: the present invention adjusts the silicon oxide height inside and outside the wafer by adding DHF before the deep well ion implantation process, ensures good uniformity of the silicon oxide height in the wafer before the key process Certas vapor phase etching back process, and improves the uniformity of the silicon oxide height in the wafer after the Certas vapor phase etching Fin back process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown is a schematic cross-sectional structural diagram of an active area structure in a central area on a wafer of the present invention;

[0021] Figure 2 Shown is a schematic diagram of the structure after the silicon nitride layer on the active area structure is removed in the present invention;

[0022] Figure 3 Shown is a schematic diagram of the structure formed after etching silicon oxide in the central area and the edge area in the present invention;

[0023] Figure 4It is a schematic diagram showing the structure of the top of the active area structure exposed by etching in the present invention;

[0024] Figure 5 The electronic image showing the uniformity of the central and edge regions after hydrofluoric acid etching in the present invention;

[0025] Figure 6 Shown is a flow chart of the method for adjusting the height uniformity of the active operable area within a wafer according to the present invention. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] See also Figures 1 to 6 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0028] The present invention provides a method for adjusting the height uniformity of the active operable area in a wafer, such as Figure 6 As shown, Figure 6 The flowchart of the method for adjusting the height uniformity of the active operable area in the wafer according to the present invention is shown. The method comprises at least the following steps:

[0029] Step 1: Provide a wafer, wherein the wafer surface is divided into a central area and an edge area, wherein the central area is an area within a radius of 30 mm from the center of the wafer; the edge area is an annular area outside the radius of 30 mm from the center of the wafer; the central area is provided with active area structures spaced apart from each other; a pad oxide layer is provided on top of the active area structure; a silicon nitride layer is provided on the pad oxide layer; the central area and the edge area on the wafer are both covered with silicon oxide; the silicon oxide is filled between the active area structures and covers the silicon nitride layer;

[0030] Furthermore, in the present invention, the active region structure in step 1 of this embodiment is a silicon structure.

[0031] Furthermore, in the present invention, in step 1 of this embodiment, the active area structure on the wafer is divided into a sparse area and a dense area according to the density of its distribution.

[0032] Furthermore, in the present invention, the top of the silicon oxide in step 1 of this embodiment is not planarized.

[0033] like Figure 1 As shown, Figure 1 The cross-sectional structure of the active area structure in the center region of a wafer according to the present invention is shown. In step 1, the center region is provided with spaced-apart active area structures 01; a pad oxide layer 02 is formed on top of the active area structures; a silicon nitride layer 03 is formed on the pad oxide layer 02; the center and edge regions of the wafer are covered with silicon oxide 04; the silicon oxide 04 fills the spaces between the active area structures 01 and covers the silicon nitride layer 03. The active area structure in step 1 of this embodiment is a silicon structure. In other words, the active area structure in this embodiment is a Fin structure in a FinFET.

[0034] In step 1 of this embodiment, the active area structure 01 on the wafer is divided into a sparse area (ISO) and a dense area (Dense) according to their distribution density. In step 1 of this embodiment, the top of the silicon oxide is not planarized (CMP).

[0035] Step 2: removing the silicon oxide above the active area structure by planarization, and then removing the silicon nitride layer on the active area structure by phosphoric acid to expose the pad oxide layer on the top of the active area structure; Figure 2 As shown, Figure 2 This is a schematic diagram of the structure after the silicon nitride layer on the active area structure is removed. Step 2 involves removing the silicon oxide 04 above the active area structure 01 through a planarization process. Then, the silicon nitride layer 02 on the active area structure 01 is removed using phosphoric acid, exposing the pad oxide layer 02 on top of the active area structure 01.

[0036] Step 3: using a hydrofluoric acid etchant to etch the silicon oxide in the shallow trench isolation region in the center area of ​​the wafer and the silicon oxide in the shallow trench isolation region in the edge area, so as to reduce the height difference between the silicon oxide in the shallow trench isolation region in the center area and the silicon oxide in the shallow trench isolation region in the edge area;

[0037] Furthermore, in the present invention, after the hydrofluoric acid etching in step three of this embodiment, the height of the silicon oxide in the central region is 2 to 10 nm higher than that of the active region structure.

[0038] Furthermore, in the present invention, the etching thickness of the silicon oxide in the central area and the edge area in step three of this embodiment is 0.3-3 nm.

[0039] Furthermore, in the present invention, in step three of this embodiment, the thickness of the silicon oxide etched in the central area is smaller than the thickness of the silicon oxide etched in the edge area.

[0040] Furthermore, in the present invention, in step three of this embodiment, the difference between the thickness of the silicon oxide etched in the central area and the thickness of the silicon oxide etched in the edge area is 0.4-1 nm.

[0041] like Figure 3 As shown, Figure 3 It is a schematic diagram showing the structure formed after etching silicon oxide in the central area and the edge area in the present invention.

[0042] In step 3, hydrofluoric acid etchant (DHF) is used to etch the silicon oxide 04 in the shallow trench isolation region in the center area of ​​the wafer and the silicon oxide ( Figures 1 to 4 The edge region is not shown) to reduce the height difference between the silicon oxide in the central region and the shallow trench isolation region on the edge region. After hydrofluoric acid etching, the height of the silicon oxide 04 in the central region is 2 to 10 nm higher than the active area structure 01. In this embodiment, the etching thickness of the silicon oxide in the central region and the edge region is 0.3 to 3 nm. The thickness of the silicon oxide etched in the central region is less than the thickness of the silicon oxide etched in the edge region. The difference between the thickness of the silicon oxide etched in the central region and the thickness of the silicon oxide etched in the edge region is 0.4 to 1 nm.

[0043] Step 4: performing well ion implantation on the wafer;

[0044] Step 5: Vapor-etch the silicon oxide and pad silicon oxide 02 in the shallow trench isolation region to expose the top of the active region structure. Figure 4 As shown, Figure 4 The diagram shows the structure of the top of the active area structure exposed by etching in the present invention. In step five, the silicon oxide 04 and the pad silicon oxide 02 of the shallow trench isolation region are etched so that the top of the active area structure 01 is exposed, forming Figure 4 The structure shown.

[0045] The present invention further comprises that in step five of this embodiment, the silicon oxide in the shallow trench isolation region is etched using a Certas vapor phase etching process.

[0046] like Figure 5 As shown, Figure 5The optical height images show the uniformity of the center and edge regions after hydrofluoric acid etching in the present invention. As can be seen, the improved fin height uniformity after fin back etching has been reduced from approximately 1.6nm in the full map range to approximately 1.3nm, and the CDU full range has been improved by 18.7%.

[0047] In summary, the present invention regulates the silicon oxide height inside and outside the wafer by adding DHF before the deep-well ion implantation process. This ensures good silicon oxide height uniformity within the wafer before the critical Certas vapor-phase etch-back process, and improves silicon oxide height uniformity within the wafer after the Certas vapor-phase etch-back Fin process. Therefore, the present invention effectively overcomes the shortcomings of the existing technology and has high industrial application value.

[0048] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for adjusting the height uniformity of the active operable area in a wafer, characterized in that: At least: Step 1: Provide a wafer, wherein the wafer surface is divided into a central area and an edge area, wherein the central area is an area within a radius of 30 mm from the center of the wafer; the edge area is an annular area outside the radius of 30 mm from the center of the wafer; the central area is provided with active area structures spaced apart from each other; a pad oxide layer is provided on top of the active area structure; a silicon nitride layer is provided on the pad oxide layer; the central area and the edge area on the wafer are both covered with silicon oxide; the silicon oxide is filled between the active area structures and covers the silicon nitride layer; Step 2: removing the silicon oxide above the active area structure by chemical mechanical polishing, and then removing the silicon nitride layer on the active area structure by phosphoric acid to expose the pad oxide layer on the top of the active area structure; Step 3: Etching the silicon oxide in the shallow trench isolation region in the center area of ​​the wafer and the silicon oxide in the shallow trench isolation region in the edge area using a hydrofluoric acid etchant to reduce the height difference between the silicon oxide in the shallow trench isolation region in the center area and the silicon oxide in the shallow trench isolation region in the edge area, so that the height of the silicon oxide in the center area is 2 to 10 nm higher than that of the active area structure; Step 4: performing well ion implantation on the wafer; Step 5: Vapor-etching the silicon oxide and pad oxide layer in the shallow trench isolation region to expose the top of the active area structure.

2. The method for adjusting the height uniformity of the active operable area within a wafer according to claim 1, wherein: The active region structure in step 1 is a silicon structure.

3. The method for adjusting the height uniformity of the active operable area within a wafer according to claim 1, wherein: In step 1, the active area structure on the wafer is divided into a sparse area and a dense area according to the density of its distribution.

4. The method for adjusting the height uniformity of the active operable area within a wafer according to claim 1, wherein: The top of the silicon oxide in step 1 has been planarized by chemical mechanical polishing.

5. The method for adjusting the height uniformity of the active operable area within a wafer according to claim 1, wherein: The etching thickness of the silicon oxide in the central area and the edge area in step 3 is 0.3-3 nm.

6. The method for adjusting the height uniformity of the active operable area within a wafer according to claim 1, wherein: In step 3, the thickness of the silicon oxide etched in the central area is smaller than the thickness of the silicon oxide etched in the edge area.

7. The method for adjusting the height uniformity of the active operable area within a wafer according to claim 6, wherein: In step 3, the difference between the thickness of the silicon oxide etched in the central area and the thickness of the silicon oxide etched in the edge area is 0.4-1 nm.

8. The method for adjusting the height uniformity of the active operable area within a wafer according to claim 1, wherein: In step five, the silicon oxide in the central area is etched using a Certas vapor phase etching process.

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