Interface polarity deflection in InGaP / GaAs heterojunction bipolar transistors and methods of making the same

Abstract

This invention relates to an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection and its fabrication method. The method includes: fabricating a nucleation layer on a substrate; fabricating a collector ohmic contact layer on the nucleation layer; fabricating an etch stop layer on the collector ohmic contact layer; fabricating a collector transition layer on the etch stop layer; fabricating a first collector region layer on the collector transition layer; fabricating a second collector region layer on the first collector region layer; fabricating a p+GaAs base region layer on the second collector region layer; fabricating an n-InGaP emitter region layer on the p+GaAs base region layer; fabricating a first cap layer on the n-InGaP emitter region layer; and fabricating a second cap layer on the first cap layer. This invention solves the performance degradation problem caused by the low conduction band and valence band energy difference and low current gain in existing devices.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology and relates to an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection and its fabrication method. Background Technology

[0002] Since the beginning of the 21st century, with the rapid development of global informatization, digital services, radio frequency communication, and microwave technology have developed rapidly and been widely applied to various aspects of society. Among them, the heterojunction bipolar transistor (HBT) has a high amplification factor β and a high cutoff frequency f due to its highly doped base region. T HBTs are primarily used in high-frequency power amplifiers, such as those in the X-band (8–12 GHz) and S-band (2–4 GHz). They are also used in frequency synthesizers, A / D converters, and D / A converters in microwave communications. HBTs have wide applications in microwave communications and radar.

[0003] Compared to earlier AlGaAs / GaAs HBT devices, InGaP / GaAs HBTs offer numerous advantages, including higher breakdown voltage, higher current gain, and better high-frequency characteristics. However, in terms of material properties, due to the higher reactivity of Al, AlGaAs / GaAs heterojunctions are more prone to forming deep-level recombination centers (DX centers), leading to a decrease in beta and an increase in low-frequency noise. In terms of fabrication, InGaP and GaAs exhibit high selective etching ratios and good etching anisotropy, resulting in easier device fabrication. These advantages make InGaP / GaAs materials the most suitable and popular choice for III-V compound HBTs.

[0004] For HBTs, improving device speed and high-frequency performance requires increasing carrier injection efficiency to enhance current gain and achieve a higher amplification factor β. Simultaneously, improving high-frequency performance also necessitates minimizing the increase in resistance due to doping, which negatively impacts the cutoff frequency f. T The impact.

[0005] However, many current HBT heterojunction structures suffer from low conduction band and valence band energy differences, low current gain, and poor temperature stability, which leads to a reduction in the overall performance of the integrated device. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] This invention provides a method for fabricating an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection, comprising the following steps:

[0008] Select a substrate layer;

[0009] A core layer is formed on the substrate layer;

[0010] A current collector ohmic contact layer is prepared on the nucleation layer;

[0011] An etching barrier layer is prepared on the current collector ohmic contact layer;

[0012] A collector transition layer is fabricated on the etching stop layer;

[0013] A first current collector region layer is prepared on the current collector transition layer;

[0014] A second current collector layer is fabricated on the first current collector layer;

[0015] A p+GaAs-based region layer is prepared on the second current collector region layer;

[0016] An n-InGaP emitter layer is prepared on the p+GaAs base layer, and an InGaP / GaAs heterojunction is formed between the p+GaAs base layer and the n-InGaP emitter layer, where the Ga / In surface of the n-InGaP emitter layer contacts the Ga surface of the p+GaAs base layer.

[0017] A first cap layer is fabricated on the n-InGaP emitter region layer;

[0018] A second cap layer is prepared on the first cap layer.

[0019] In one embodiment of the present invention,

[0020] Fabricating an n-InGaP emitter layer on the p+GaAs base layer includes:

[0021] The surface of the p+GaAs base layer is subjected to a staged heating and cooling pretreatment, which involves raising the temperature from a first temperature to a second temperature and then cooling it back to the first temperature. At both the first and second temperatures, a heat preservation treatment is performed.

[0022] The n-InGaP emitter layer is epitaxially grown on the p+GaAs base layer after a staged heating and cooling pretreatment by a stepped heating method.

[0023] In one embodiment of the present invention, the first temperature is 480-500℃ and the second temperature is 530-550℃, and the heat preservation time at both the first temperature and the second temperature is 100s.

[0024] In one embodiment of the present invention,

[0025] The n-InGaP emitter layer is epitaxially grown on the p+GaAs base layer after a staged heating and cooling pretreatment, including:

[0026] An MOCVD apparatus employing an up-intake reaction chamber structure is used to epitaxially grow the n-InGaP emitter layer on the p+GaAs base layer after staged heating and cooling pretreatment via a stepped heating method. The source is PH3 / TMGa / TMIn / Si2H6, and the driving gas method is pulsed carrier gas driving. The stepped heating method involves first heating from a third temperature to a fourth temperature, and then heating from the fourth temperature to a fifth temperature, with heat preservation treatment performed at the third, fourth, and fifth temperatures.

[0027] In one embodiment of the present invention, the third temperature is 550±5℃, the fourth temperature is 570±5℃, the fifth temperature is 590±5℃, and the holding time at the third temperature, the fourth temperature, and the fifth temperature is 100s.

[0028] In one embodiment of the present invention, the substrate layer is made of GaAs, the nucleation layer is made of AlGaAs, the collector ohmic contact layer is made of n+GaAs, the etch stop layer is made of n+InGaP, the collector transition layer is made of n+GaAs, the first collector region layer and the second collector region layer are both made of n-GaAs, the first cap layer is made of n+GaAs, the second cap layer is made of n+InGaAs, and the In composition of the second cap layer is x = 0 to 0.55, gradually increasing from bottom to top.

[0029] In one embodiment of the present invention, the doping concentration of the collector ohmic contact layer is 5 × 10⁻⁶. 18 cm -3 The doping concentration of the etching stop layer is 1×10⁻⁶. 18 cm -3 The doping concentration of the collector transition layer is 5 × 10⁻⁶. 18 cm -3 The doping concentration of the first collector layer is 4×10⁻⁶. 16 cm -3 The doping concentration of the second collector layer is 1.5 × 10⁻⁶. 16 cm -3 The doping concentration of the p+GaAs base layer is 4×10⁻⁶. 19 cm -3The doping concentration of the n-InGaP emitter layer is 3×10⁻⁶. 17 cm -3 The doping concentration of the first cap layer is 3×10 18 cm -3 The doping concentration of the second cap layer is 1.5 × 10⁻⁶. 19 cm -3 .

[0030] In one embodiment of the present invention, the doping elements of the collector ohmic contact layer, the etch stop layer, the collector transition layer, the first collector region layer, the second collector region layer, the n-InGaP emitter region layer, and the first cap layer are all Si, the doping element of the p+GaAs base region layer is C, and the doping element of the second cap layer is Te.

[0031] In one embodiment of the present invention, the thickness of the substrate layer is 660 μm, and the thickness of the nucleation layer is... The thickness of the collector ohmic contact layer is: The thickness of the etching stop layer is The thickness of the collector transition layer is The thickness of the first collector layer is The thickness of the second collector layer is The thickness of the p+GaAs base layer is The thickness of the n-InGaP emitter layer is The thickness of the first cap layer is The thickness of the second cap layer is

[0032] Another embodiment of the present invention provides an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection, wherein the InGaP / GaAs heterojunction bipolar transistor is fabricated by the fabrication method described in any of the above embodiments.

[0033] The InGaP / GaAs heterojunction bipolar transistor includes:

[0034] Substrate layer;

[0035] Nucleation layer, located on the substrate layer;

[0036] A collector ohmic contact layer is located on the nucleation layer;

[0037] An etch stop layer is located on the collector ohmic contact layer;

[0038] A collector transition layer is located on the etching stop layer;

[0039] The first collector region layer is located on the collector transition layer;

[0040] The second collector layer is located above the first collector layer;

[0041] The p+GaAs base region layer is located on the second collector region layer;

[0042] The n-InGaP emitter region layer is located on the p+GaAs base region layer;

[0043] The first cap layer is located on the n-InGaP emitter region layer;

[0044] The second cap layer is located on top of the first cap layer.

[0045] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0046] This invention proposes a high-performance and highly stable InGaP / GaAs-based HBT epitaxial growth method, which utilizes InGaP with polarity-direction-biased InGaP to form an InGaP / GaAs heterojunction interface, resulting in a high bandgap ΔE. g This results in high current gain, increases the β value of the device, and solves the problem of low performance caused by low conduction band and valence band energy difference and small current gain in existing devices.

[0047] Other aspects and features of the invention will become apparent from the following detailed description with reference to the accompanying drawings. However, it should be understood that the drawings are for illustrative purposes only and not as a limitation of the scope of the invention, as reference should be made to the appended claims. It should also be understood that, unless otherwise indicated, the drawings are not necessarily drawn to scale; they are merely intended to conceptually illustrate the structures and processes described herein. Attached Figure Description

[0048] Figure 1 A schematic flowchart illustrating a method for fabricating an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection, provided in an embodiment of the present invention.

[0049] Figure 2 A schematic diagram of the structure of an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection provided in an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of a conventional InGaP / GaAs heterojunction provided for an embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of a polarity-direction-deflected InGaP / GaAs heterojunction provided in an embodiment of the present invention. Detailed Implementation

[0052] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0053] Example 1

[0054] Please see Figure 1 , Figure 2 , Figure 1 This is a schematic flowchart illustrating a method for fabricating an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection, as provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection, provided as an embodiment of the present invention. The present invention provides a method for fabricating an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection, the method comprising the following steps:

[0055] Step 1: Select substrate layer 1.

[0056] Preferably, the substrate 1 is made of GaAs, which is a semi-insulating (SI) type or an N type.

[0057] Preferably, the thickness of the substrate layer 1 is 660 μm.

[0058] Step 2: Prepare the core layer 2 on the substrate layer 1.

[0059] Specifically, a nucleation layer 2 is epitaxially grown on a substrate layer 1 that has undergone surface pretreatment.

[0060] Preferably, the material of nucleation layer 2 is AlGaAs, and the doping type is unintentional doping.

[0061] Preferably, the thickness of the nucleation layer 2 is

[0062] In one specific embodiment, an epitaxial growth of thickness is performed on the surface-pretreated substrate layer 1. The undoped AlGaAs nucleation layer 2 was formed from AsH3 / TMGa / TMAl at a growth temperature of 600℃.

[0063] Step 3: Prepare the current collector ohmic contact layer 3 on the nucleation layer 2.

[0064] Specifically, the collector ohmic contact layer 3 is on the collector ohmic contact layer 3.

[0065] Preferably, the material of the collector ohmic contact layer 3 is n+GaAs.

[0066] Preferably, the doping concentration of the collector ohmic contact layer 3 is 5 × 10⁻⁶. 18 cm-3 The doping element is Si.

[0067] Preferably, the thickness of the collector ohmic contact layer 3 is [missing information].

[0068] In one specific embodiment, an epitaxial growth layer with a thickness of [missing information] is grown on nucleation layer 2. Doping concentration is 5×10 18 cm -3 The n+GaAs collector ohmic contact layer 3 is doped with Si, sourced from AsH3 / TMGa / Si2H6, and grown at a temperature of 650℃.

[0069] Step 4: Prepare an etch stop layer 4 on the collector ohmic contact layer 3.

[0070] Specifically, an etch stop layer 4 is epitaxially grown on the collector ohmic contact layer 3.

[0071] Preferably, the material of the etch stop layer 4 is n+InGaP.

[0072] Preferably, the doping concentration of the etch stop layer 4 is 1×10⁻⁶. 18 cm -3 The doping element is Si.

[0073] Preferably, the thickness of the etch stop layer 4 is [missing information].

[0074] In one specific embodiment, an epitaxial growth layer with a thickness of [missing information] is grown on the collector ohmic contact layer 3. Doping concentration of 1×10 18 cm -3 The n+InGaP etch stop layer 4 is sourced from PH3 / TMGa / TMIn / Si2H6 and grown at a temperature of 650℃.

[0075] Step 5: Prepare the collector transition layer 5 on the etch stop layer 4.

[0076] Specifically, a collector transition layer 5 is epitaxially grown on the etch stop layer 4.

[0077] Preferably, the material of the collector transition layer 5 is n+GaAs.

[0078] Preferably, the doping concentration of the collector transition layer 5 is 5 × 10⁻⁶. 18 cm -3 The doping element is Si.

[0079] Preferably, the thickness of the collector transition layer 5 is [missing information].

[0080] In one specific embodiment, an epitaxial growth of thickness is performed on the etch stop layer 4. Doping concentration is 5×10 18 cm -3 The n+GaAs collector transition layer 5 is sourced from AsH3 / TMGa / Si2H6 and grown at a temperature of 650℃.

[0081] Step 6: Prepare the first collector region layer 6 on the collector transition layer 5.

[0082] Specifically, a first collector region layer 6 is epitaxially grown on the collector transition layer 5.

[0083] Preferably, the material of the first collector layer 6 is n-GaAs.

[0084] Preferably, the doping concentration of the first collector layer 6 is 4 × 10⁶. 16 cm -3 The doping element is Si.

[0085] Preferably, the thickness of the first collector layer 6 is

[0086] In one specific embodiment, an epitaxial growth of thickness is performed on the collector transition layer 5. Doping concentration is 4×10 16 cm -3 The first collector layer 6 of the n-GaAs is sourced from AsH3 / TMGa / Si2H6 and grown at a temperature of 650℃.

[0087] Step 7: Prepare a second collector layer 7 on the first collector layer 6.

[0088] Specifically, a second collector layer 7 is epitaxially grown on the first collector layer 6.

[0089] Preferably, the material of the second collector layer 7 is n-GaAs.

[0090] Preferably, the doping concentration of the second collector layer 7 is 1.5 × 10⁻⁶. 16 cm -3 The doping element is Si.

[0091] Preferably, the thickness of the second collector layer 7 is

[0092] In one specific embodiment, an epitaxial growth layer with a thickness of [missing information] is grown on the first collector region layer 6. The doping concentration is 1.5 × 10⁻⁶. 16 cm -3 The second collector layer 7 of n-GaAs is sourced from AsH3 / TMGa / Si2H6 and grown at a temperature of 650℃.

[0093] Step 8: Prepare p+GaAs base layer 8 on the second collector layer 7.

[0094] Specifically, a p+GaAs base layer 8 is epitaxially grown on the second collector layer 7.

[0095] Preferably, the doping concentration of the p+GaAs base layer 8 is 4 × 10⁸. 19 cm -3 The doping element is C.

[0096] Preferably, the thickness of the p+GaAs base layer 8 is [missing information].

[0097] In one specific embodiment, an epitaxial growth layer with a thickness of [missing information] is grown on the second collector region layer 7. Doping concentration is 4×10 19 cm -3 The p+GaAs base region layer 8 was sourced from AsH3 / TMGa / CBr4 and grown at a temperature of 550℃.

[0098] Step 9: Prepare an n-InGaP emitter layer 9 on the p+GaAs base layer 8. An InGaP / GaAs heterojunction is formed between the p+GaAs base layer 8 and the n-InGaP emitter layer 9, with the Ga / In surface of the n-InGaP emitter layer 9 in contact with the Ga surface of the p+GaAs base layer 8.

[0099] In one specific embodiment, step 9 may include steps 9.1-9.2, wherein:

[0100] Step 9.1 Perform a staged heating and cooling pretreatment on the surface of the p+GaAs base layer 8, which involves heating from a first temperature to a second temperature and then cooling from the second temperature back to the first temperature, and perform heat preservation treatment at both the first and second temperatures.

[0101] Preferably, the first temperature is 480-500℃ and the second temperature is 530-550℃, and the holding time at both the first and second temperatures is 100s.

[0102] Specifically, a staged heating and cooling pretreatment process is implemented on the surface of the p+GaAs base layer 8, which is as follows: the temperature is held at 480-500℃ for 100 seconds, then heated to 530-550℃ for 300 seconds, held at 530-550℃ for 100 seconds, then cooled from 530-550℃ to 480-500℃ for 300 seconds, and held at 480-500℃ for 100 seconds, for a total pretreatment time of 900 seconds.

[0103] Step 9.2: On the p+GaAs base layer 8 after the staged heating and cooling pretreatment, the n-InGaP emitter layer 9 is epitaxially grown by step heating method. The step heating method is to first heat from the third temperature to the fourth temperature, and then heat from the fourth temperature to the fifth temperature.

[0104] Specifically, an MOCVD (Metal-organic Chemical Vapor Deposition) device with an up-intake reaction chamber structure was used to epitaxially grow an n-InGaP emitter layer 9 on the p+GaAs base layer 8 after staged heating and cooling pretreatment by a stepped heating method. The source was PH3 / TMGa / TMIn / Si2H6, the driving gas method was pulsed carrier gas driving method, and the stepped heating method was to first heat from the third temperature to the fourth temperature, and then heat from the fourth temperature to the fifth temperature, and heat preservation treatment was performed at the third, fourth and fifth temperatures.

[0105] Preferably, the third temperature is 550±5℃, the fourth temperature is 570±5℃, and the fifth temperature is 590±5℃, and the growth time at the third, fourth, and fifth temperatures is 100s.

[0106] Specifically, an epitaxial growth with a thickness of [missing information] is performed on layer 8 of the p+GaAs base region. Doping concentration is 3×10 17 cm -3 The n-InGaP emitter layer 9 was grown using a PH3 / TMGa / TMIn / Si2H6 source via a pulsed carrier gas injection method. The n-InGaP emitter layer 9 was injected sequentially with PH3 / TMGa / TMIn (phosphine / trimethylgallium / trimethylindium) pulsed carrier gas at a duty cycle of 1 / 3, while Si2H6 (silane) was continuously supplied. A stepped temperature increase growth method was used: first, growth at 550±5℃ for 100 seconds; then, growth at 570±5℃ for 100 seconds; then, growth at 590±5℃ for 100 seconds; and finally, growth at 590±5℃ for 100 seconds.

[0107] Preferably, the doping concentration of the n-InGaP emitter layer 9 is 3 × 10⁻⁶. 17 cm -3 The doping element is Si.

[0108] Preferably, the thickness of the n-InGaP emitter layer 9 is [missing information].

[0109] Step 10: Prepare the first cap layer 10 on the n-InGaP emitter layer 9.

[0110] Specifically, a first cap layer 10 is epitaxially grown on the n-InGaP emitter layer 9.

[0111] Preferably, the material of the first cap layer 10 is n+GaAs.

[0112] Preferably, the doping concentration of the first cap layer 10 is 3 × 10⁻⁶. 18 cm -3 The doping element is Si.

[0113] Preferably, the thickness of the first cap layer 10 is

[0114] In one specific embodiment, an epitaxial growth layer with a thickness of [thickness missing] is grown on the n-InGaP emitter layer 9. Doping concentration is 3×10 18 cm -3 The first cap layer of n+GaAs is 10, with the source being AsH3 / TMGa / Si2H6, and the growth temperature is 650℃.

[0115] Step 11: Prepare a second cap layer 11 on the first cap layer 10.

[0116] Specifically, a second cap layer 11 is epitaxially grown on the first cap layer 10.

[0117] Preferably, the material of the second cap layer 11 is n+InGaAs, and the In composition of the second cap layer 11 is gradually increasing from x = 0 to 0.55.

[0118] Preferably, the doping concentration of the second cap layer 11 is 1.5 × 10⁻⁶. 19 cm -3 The dopant element is Te.

[0119] Preferably, the thickness of the second cap layer 11 is

[0120] In one specific embodiment, an epitaxial growth layer with a thickness of [missing information] is grown on the first cap layer 10. The doping concentration is 1.5 × 10⁻⁶. 19 cm -3 The In composition is graded n+InGaAs second cap layer 11, source is AsH3 / TMGa / TMIn / DETe, and growth temperature is 500℃.

[0121] The performance of an HBT is largely determined by the emitter junction, specifically the band difference ΔE in the InGaP / GaAs heterojunction. g Mainly due to the price band difference ΔE V The determining factor is the valence band difference ΔE in the InGaP / GaAs heterojunction system. V Much greater than the conduction band difference ΔEC Theoretically, the current gain β of an HBT device is proportional to Exp(ΔE). g / kT), that is, β∝Exp(△E V / kT), so increase ΔE V This can increase the β value of the device.

[0122] Due to the numerous advantages of InGaP / GaAs heterojunctions as described above, improving the β value of devices without changing the materials has been a hot research topic. The lattice arrangement of the base GaAs layer and the emitter InGaP layer at the heterojunction interface, as well as the transition interface from base GaAs to emitter InGaP, is particularly important, as they largely determine the β characteristics of HBT devices. This invention discovered during epitaxial growth that, since both materials forming the heterojunction are compounds, different contact surface states exist at the heterojunction interface. Typically, the P-atom facet of the InGaP layer contacts the Ga-atom facet of the GaAs layer, such as... Figure 3 As shown. When the lattice atomic arrangement at the contact surface is changed, the band difference of the resulting InGaP / GaAs heterojunction changes significantly, which can be used to adjust the β value.

[0123] Based on this principle, this invention proposes using an MOCVD device with an up-gas-intake reaction chamber structure for epitaxial growth. On top of the GaAs base layer, through GaAs surface pretreatment and controlled InGaP growth processes, an emitter region InGaP crystal structure layer with polarity deflection is obtained. Specifically, the Ga / In plane of the InGaP layer contacts the Ga plane of the GaAs layer at the InGaP / GaAs heterojunction interface. Figure 4 As shown. The main purpose of this measure is: (1) to increase the bandgap difference of the InGaP / GaAs heterojunction, thereby effectively increasing the current gain β; (2) due to the polarity deflection of InGaP, the InGaP / GaAs heterojunction interface can generate a more stable atomic bonding structure, thereby obtaining an HBT device with higher β value stability. Batch epitaxial growth experiments have shown that, compared with conventional heterojunction interface devices, after the polarity deflection of InGaP at the heterojunction interface, the β value of the InGaP / GaAs HBT device is increased by an average of 10%, and its burn-in can be reduced to about 4%, thereby significantly improving stability. At the same time, for HBT, when the doping concentration of the device base region is very high, a higher cutoff frequency f can be obtained. T Based on this principle, carbon doping is used in the base region. Carbon doping has high mobility and a relatively small diffusion coefficient. This can reduce the base region resistance and improve the reliability of the device, thereby improving the high-frequency performance of the device.

[0124] The HBT of this invention achieves InGaP polarity direction deflection at the InGaP / GaAs heterojunction interface through epitaxial growth control, thereby improving the valence band discontinuity ΔE. V This results in a high band gap ΔE g Meanwhile, the improved interfacial atomic bonding stability gives HBT devices high stability and high uniformity of current gain characteristics.

[0125] The epitaxial growth of the device of the present invention is carried out using an MOCVD equipment with an up-gas-intake reaction chamber structure. After the surface layer of the p+GaAs base layer is pretreated, the n-InGaP emitter layer is injected with a pulse carrier gas driven by PH3 / TMGa / TMIn in sequence at a duty cycle of 1 / 3 during the cycle, while Si2H6 is continuously passed through, in order to achieve the polarity direction deflection of the n-InGaP emitter layer.

[0126] The surface of the p+GaAs base layer of this invention is subjected to a heating and cooling pretreatment method, and a stepped heating method is used in the pulse growth process of the n-InGaP emitter layer to form a highly uniform polarity-direction-deflected InGaP layer.

[0127] By deflecting the polarity of the n-InGaP emitter layer in an InGaP / GaAs heterojunction HBT device, the average β value can be increased by 10% and the burn-in can be reduced to 4% while keeping other parameters constant, resulting in a significant improvement in the overall performance of the device.

[0128] Example 2

[0129] Please see Figure 2 , Figure 2 This is a schematic diagram of an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection provided in an embodiment of the present invention. Based on the above embodiments, the present invention further provides an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection, which is fabricated by the fabrication method of the InGaP / GaAs heterojunction bipolar transistor described in the above embodiments. The InGaP / GaAs heterojunction bipolar transistor includes:

[0130] Substrate 1;

[0131] Nucleation layer 2 is located on substrate layer 1;

[0132] The collector ohmic contact layer 3 is located on the nucleation layer 2;

[0133] Etching barrier layer 4 is located on collector ohmic contact layer 3;

[0134] Collector transition layer 5 is located on etch stop layer 4;

[0135] The first collector region layer 6 is located on the collector transition layer 5;

[0136] The second collector layer 7 is located on the first collector layer 6;

[0137] p+GaAs base layer 8 is located on the second collector layer 7;

[0138] n-InGaP emitter layer 9 is located on p+GaAs base layer 8;

[0139] The first cap layer 10 is located on the n-InGaP emitter layer 9;

[0140] The second cap layer 11 is located on the first cap layer 10.

[0141] This invention proposes a high-performance and highly stable InGaP / GaAs-based HBT epitaxial growth structure, utilizing InGaP with polarity-direction-biased InGaP to form an InGaP / GaAs heterojunction interface, resulting in a high bandgap ΔE. g This results in high current gain, increases the β value of the device, and solves the problem of low performance caused by low conduction band and valence band energy difference and small current gain in existing devices.

[0142] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0143] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or data point described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or data points described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0144] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating an InGaP / GaAs heterojunction bipolar transistor with interface polarity deflection, characterized in that, The method comprises the following steps: selecting a substrate layer (1); preparing a nucleation layer (2) on the substrate layer (1); preparing a collector ohmic contact layer (3) on the nucleation layer (2); preparing an etching stop layer (4) on the collector ohmic contact layer (3); preparing a collector transition layer (5) on the etching stop layer (4); preparing a first collector region layer (6) on the collector transition layer (5); preparing a second collector region layer (7) on the first collector region layer (6); preparing a p+ GaAs base region layer (8) on the second collector region layer (7); preparing an n-InGaP emitter region layer (9) on the p+ GaAs base region layer (8), and forming an InGaP / GaAs heterojunction between the p+ GaAs base region layer (8) and the n-InGaP emitter region layer (9) with the Ga / In surface of the n-InGaP emitter region layer (9) contacting the Ga surface of the p+ GaAs base region layer (8); preparing a first cap layer (10) on the n-InGaP emitter region layer (9); preparing a second cap layer (11) on the first cap layer (10).

2. The method of claim 1, wherein the InGaP / GaAs heterojunction bipolar transistor is prepared by the steps of: The method for preparing the n-InGaP emitter region layer (9) on the p+ GaAs base region layer (8) comprises: carrying out stage-wise temperature rising and falling pretreatment on the surface of the p+ GaAs base region layer (8) by rising from a first temperature to a second temperature and then falling from the second temperature to the first temperature, and carrying out holding treatment at the first temperature and the second temperature; epitaxially growing the n-InGaP emitter region layer (9) on the p+ GaAs base region layer (8) after the stage-wise temperature rising and falling pretreatment by means of step-wise temperature rising.

3. The method of claim 2, wherein the InGaP / GaAs heterojunction bipolar transistor is prepared by the steps of: The first temperature is 480-500℃, the second temperature is 530-550℃, and the holding time at the first temperature and the second temperature is 100s.

4. The method of claim 2, wherein the InGaP / GaAs heterojunction bipolar transistor is prepared by the steps of: The method for epitaxially growing the n-InGaP emitter region layer (9) on the p+ GaAs base region layer (8) after the stage-wise temperature rising and falling pretreatment comprises: using a MOCVD device with an upper gas absorption reaction cavity structure to epitaxially grow the n-InGaP emitter region layer (9) on the p+ GaAs base region layer (8) after the stage-wise temperature rising and falling pretreatment by means of step-wise temperature rising, the source being PH3 / TMGa / TMIn / Si2H6, the gas driving mode being pulse carrier gas driving mode, and the step-wise temperature rising mode being first rising from a third temperature to a fourth temperature and then rising from the fourth temperature to a fifth temperature, and holding treatment being carried out at the third temperature, the fourth temperature and the fifth temperature.

5. The method of claim 4, wherein the InGaP / GaAs heterojunction bipolar transistor is prepared by the steps of: The third temperature is 550±5℃, the fourth temperature is 570±5℃, the fifth temperature is 590±5℃, and the holding time at the third temperature, the fourth temperature and the fifth temperature is 100s.

6. The method of claim 1, wherein the InGaP / GaAs heterojunction bipolar transistor is prepared by the steps of: The material of the substrate layer (1) is GaAs, the material of the nucleation layer (2) is AlGaAs, the material of the collector ohmic contact layer (3) is n+GaAs, the material of the etching stop layer (4) is n+InGaP, the material of the collector transition layer (5) is n+GaAs, the material of the first collector region layer (6) and the second collector region layer (7) is n-GaAs, the material of the first cap layer (10) is n+GaAs, the material of the second cap layer (11) is n+InGaAs, and the In component of the second cap layer (11) gradually changes from x = 0 to 0.55, gradually increasing from bottom to top.

7. The method for fabricating an InGaP / GaAs heterojunction bipolar transistor according to claim 6, characterized in that, The doping concentration of the collector ohmic contact layer (3) is 5x10 18 cm -3 -3, the doping concentration of the etching stop layer (4) is 1x10 18 cm -3 -3, the doping concentration of the collector transition layer (5) is 5x10 18 cm -3 -3, the doping concentration of the first collector region layer (6) is 4x10 16 cm -3 -3, the doping concentration of the second collector region layer (7) is 1.5x10 16 cm -3 -3, the doping concentration of the p+ GaAs base region layer (8) is 4x10 19 cm -3 -3, the doping concentration of the n-InGaP emitter region layer (9) is 3x10 17 cm -3 -3, the doping concentration of the first cap layer (10) is 3x10 18 cm -3 -3, and the doping concentration of the second cap layer (11) is 1.5x10 19 cm -3 -3.

8. The method of claim 7, wherein the InGaP / GaAs heterojunction bipolar transistor is prepared by the steps of: The doping elements of the collector ohmic contact layer (3), the etching stop layer (4), the collector transition layer (5), the first collector region layer (6), the second collector region layer (7), the n-InGaP emitter region layer (9), and the first cap layer (10) are all Si, the doping element of the p+GaAs base region layer (8) is C, and the doping element of the second cap layer (11) is Te.

9. The method of claim 7, wherein the InGaP / GaAs heterojunction bipolar transistor is prepared by the steps of: The thickness of the substrate layer (1) is 660 μm, the thickness of the nucleation layer (2) is 2000 Å, the thickness of the collector ohmic contact layer (3) is 5000 Å, the thickness of the etching stop layer (4) is 200 Å, the thickness of the collector transition layer (5) is 500 Å, the thickness of the first collector region layer (6) is 5000 Å, the thickness of the second collector region layer (7) is 5000 Å, the thickness of the p+GaAs base region layer (8) is 1100 Å, the thickness of the n-InGaP emitter region layer (9) is 450 Å, the thickness of the first cap layer (10) is 1200 Å, and the thickness of the second cap layer (11) is 800 Å.

10. An InGaP / GaAs heterojunction bipolar transistor with interface polarity biasing, characterized by, The InGaP / GaAs heterojunction bipolar transistor is prepared by the preparation method of any one of claims 1 to 9, and the InGaP / GaAs heterojunction bipolar transistor comprises: a substrate layer (1); a nucleation layer (2) on the substrate layer (1); a collector ohmic contact layer (3) on the nucleation layer (2); an etching stop layer (4) on the collector ohmic contact layer (3); a collector transition layer (5) on the etching stop layer (4); a first collector region layer (6) on the collector transition layer (5); a second collector region layer (7) on the first collector region layer (6); a p+GaAs base region layer (8) on the second collector region layer (7); an n-InGaP emitter region layer (9) on the p+GaAs base region layer (8); a first cap layer (10) on the n-InGaP emitter region layer (9); a second cap layer (11) on the first cap layer (10).

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