Method of manufacturing a semiconductor device

Abstract

The application provides a semiconductor device manufacturing method. A gate is formed on a substrate. A first side wall and a second side wall are sequentially formed on the side wall of the gate. The first side wall covers part of the substrate on both sides of the gate. The second side wall covers the side surface and top surface of the first side wall. Part of the second side wall is removed, so that the top surface of the part of the first side wall covering the substrate is exposed. An ion implantation region is formed in the substrate on both sides of the gate which is not covered by the second side wall. The part of the ion implantation region far from the gate and not covered by the first side wall has a first depth. The part of the ion implantation region close to the gate and covered by the first side wall has a second depth. The first depth is greater than the second depth. The second side wall is removed. The second depth of the part of the ion implantation region close to the gate is less than the first depth of the part of the ion implantation region far from the gate. The side wall width is shortened. The short channel effect of the semiconductor device is inhibited. The device size of the semiconductor device is reduced without affecting the device performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] With the continuous development of semiconductor technology, lower manufacturing costs, lower power consumption, and faster speeds have become one of the common goals pursued by the semiconductor and electronics industries. To achieve these goals, it is necessary to continuously shrink the size of semiconductor devices by increasing integration density and reducing cell area to manufacture more transistors within the same chip area.

[0003] Figure 1 This is a schematic cross-sectional view of a MOSFET. (See attached diagram.) Figure 1 As the size of MOSFETs continues to shrink, the width of the sidewall 10 also decreases, and the distance between the source region 20 and the drain region 30 and the channel gradually decreases. This exacerbates the short-channel effect, DIBL effect (Drain Induced Barrier Low), and GIDL effect (Gate Induced Drain Leakage) of the MOSFET, leading to an increase in channel leakage current and consequently a decrease in the breakdown voltage of the semiconductor device.

[0004] Therefore, a method is needed to suppress the short-channel effect of semiconductor devices while reducing the sidewall width. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a semiconductor device that suppresses the short-channel effect of the semiconductor device while shortening the sidewall width.

[0006] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] A substrate is provided, on which a gate is formed, a first sidewall is formed on the sidewall of the gate and the first sidewall covers a portion of the substrate on both sides of the gate, and a second sidewall is formed on the first sidewall, the second sidewall covering the side and top surface of the first sidewall;

[0008] Remove a portion of the second sidewall to expose the top of the portion of the first sidewall covering the substrate;

[0009] An ion implantation process is performed to form ion implantation regions in the substrate on both sides of the gate that are not covered by the second sidewall. The portion of the ion implantation region away from the gate and not covered by the first sidewall has a first depth, and the portion of the ion implantation region near the gate and covered by the first sidewall has a second depth, wherein the first depth is greater than the second depth; and...

[0010] Remove the second sidewall.

[0011] Optionally, after the ion implantation process and before removing the second sidewall, the process further includes:

[0012] An annealing process is performed to repair the damage to the first and second sidewalls caused by the ion implantation process.

[0013] Optionally, the annealing process is a rapid thermal annealing process.

[0014] Optionally, a wet etching process can be used to remove the second sidewall.

[0015] Optionally, during the removal of the second sidewall, the portion of the first sidewall not covered by the second sidewall is also removed, exposing a portion of the sidewall near the top of the gate.

[0016] Optionally, after removing the second sidewall, the method further includes:

[0017] A metal silicide barrier layer is formed on the top of the gate, the exposed sidewalls of the gate, and the portion of the substrate not covered by the first sidewall.

[0018] Optionally, the first sidewall has an L-shaped cross-section along the extension direction perpendicular to the gate.

[0019] Optionally, the first sidewall includes a silicon oxide layer and a silicon nitride layer, the silicon oxide layer covering the sidewall of the gate and a portion of the substrate, the silicon nitride layer being formed on the surface of the silicon oxide layer, and the second sidewall being a silicon oxide layer.

[0020] Optionally, the energy of the ion implantation can penetrate the first sidewall to the substrate.

[0021] Optionally, the method for manufacturing the semiconductor device is used to manufacture a MOS device.

[0022] In summary, this invention provides a method for manufacturing a semiconductor device, comprising: forming a gate on a substrate, wherein a first sidewall and a second sidewall are sequentially formed on the sidewalls of the gate, the first sidewall covering a portion of the substrate on both sides of the gate, and the second sidewall covering the side and top surfaces of the first sidewall; removing a portion of the second sidewall to expose the top surface of the portion of the first sidewall covering the substrate; performing an ion implantation process to form an ion implantation region in the substrate on both sides of the gate not covered by the second sidewall, wherein the portion of the ion implantation region away from the gate and not covered by the first sidewall has a first depth, and the portion of the ion implantation region near the gate and covered by the first sidewall has a second depth, the first depth being greater than the second depth; and removing the second sidewall. This invention controls the morphology of the first and second sidewalls to change the depth of different portions of the ion implantation region, making the second depth of the portion of the ion implantation region near the gate less than the first depth of the portion of the ion implantation region away from the gate, thereby reducing the short-channel effect of the semiconductor device while shortening the sidewall width, so as to reduce the device size of the semiconductor device without affecting device performance. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the cross-sectional structure of a semiconductor device;

[0024] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0025] Figures 3 to 8 This is a schematic diagram of the structure corresponding to each step in the manufacturing method of a semiconductor device provided in an embodiment of the present invention;

[0026] The reference numerals in the attached figures are as follows:

[0027] 10 - Sidewall; 20 - Source region; 30 - Drain region; 40 - Gate;

[0028] 100 - Substrate; 101 - Ion implantation region; 101a - Source region; 101b - Drain region; 110 - Gate; 111 - Gate oxide layer; 120 - First sidewall; 120a - Silicon oxide layer; 120b - Silicon nitride layer; 121 - Second sidewall; 130 - Metal silicide barrier layer;

[0029] H1 - First depth; H2 - Second depth. Detailed Implementation

[0030] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0031] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. (See attached document.) Figure 2 The semiconductor device manufacturing method described in this embodiment includes:

[0032] Step S01: Provide a substrate, on which a gate is formed, a first sidewall is formed on the sidewall of the gate, and the first sidewall covers a portion of the substrate on both sides of the gate, and a second sidewall is formed on the first sidewall, the second sidewall covering the side and top surface of the first sidewall;

[0033] Step S02: Remove a portion of the second sidewall to expose the top surface of the portion of the first sidewall covering the substrate;

[0034] Step S03: Perform an ion implantation process to form ion implantation regions in the substrate not covered by the second sidewalls on both sides of the gate. The portion of the ion implantation region away from the gate and not covered by the first sidewall has a first depth, and the portion of the ion implantation region near the gate and covered by the first sidewall has a second depth. The first depth is greater than the second depth.

[0035] Step S04: Remove the second sidewall.

[0036] Figures 3 to 8 This is a schematic diagram of the structure corresponding to each step in the manufacturing method of the semiconductor device provided in this embodiment. The following is in conjunction with... Figures 3 to 8 The manufacturing method of the semiconductor device described in this embodiment is explained in detail.

[0037] First, refer to Figure 3 In step S01, a substrate 100 is provided, on which a gate 110 is formed. A first sidewall 120 is formed on the sidewall of the gate 110, and the first sidewall 120 covers a portion of the substrate 100 on both sides of the gate 110. A second sidewall 121 is formed on the first sidewall 120, and the second sidewall 121 covers the side and top surfaces of the first sidewall 120.

[0038] In this embodiment, the first sidewall 120 has an L-shaped cross-section along the extension direction perpendicular to the gate 110. The first sidewall 120 includes a silicon oxide layer 120a and a silicon nitride layer 120b. The silicon oxide layer 120a covers the sidewall of the gate 110 and part of the substrate 100. The silicon nitride layer 120b is formed on the surface of the silicon oxide layer 120a. The second sidewall 121 is a silicon oxide layer. The first sidewall 120 and the second sidewall 121 constitute an ONO stacked structure (i.e., a stacked structure composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer). In other embodiments of the present invention, the specific structure and materials of the first sidewall 120 and the second sidewall 121 can be adjusted according to actual needs, as long as the condition that "the etching rates of the first sidewall 120 and the second sidewall 121 are different" is met. The present invention does not impose any limitations on this.

[0039] In this embodiment, a gate oxide layer 111 is further formed between the gate 110 and the substrate 100. The substrate 100 is a silicon substrate, the gate 110 is a polysilicon gate, and the gate oxide layer 111 is a silicon oxide layer. In other embodiments of the present invention, the specific materials of each film layer in the semiconductor device can be adjusted according to process requirements, and the present invention does not impose any limitations on this.

[0040] Next, refer to Figure 4 Step S02 is executed to remove a portion of the second sidewall 121, thereby exposing the top surface of the portion of the first sidewall 120 covering the substrate 100. In this embodiment, a wet etching process is used to remove a portion of the second sidewall 121.

[0041] It should be noted that since the second sidewall 121 covers the first sidewall 120, the first sidewall 120 is not etched or is only slightly etched in step S02. At this time, the thickness of the second sidewall 121 is reduced, exposing the portion of the first sidewall 120 that is away from the gate 110 and covers the substrate 100, and also exposing the portion of the first sidewall 120 that is near the top of the gate 110.

[0042] Next, refer to Figure 5 and Figure 6 Step S03 is executed to perform an ion implantation process, forming an ion implantation region 101 in the substrate 100 on both sides of the gate 110 that is not covered by the second sidewall 121. The portion of the ion implantation region 101 that is far from the gate 110 and not covered by the first sidewall 120 has a first depth H1, and the portion of the ion implantation region 101 that is close to the gate 110 and covered by the first sidewall 120 has a second depth H2. The first depth H1 is greater than the second depth H2.

[0043] In this embodiment, the process parameters of the ion implantation process include arsenic ion implantation, an implantation energy of 30 keV to 80 keV, and an implantation dose of 1E14 / cm. 2 ~1E16 / cm 2 Boron ion implantation, with an implantation energy of 3 keV to 8 keV and an implantation dose of 1 E14 / cm². 2 ~1E16 / cm 2 Optionally, the first depth H1 ranges from 0.03 μm to 0.05 μm, and the second depth H2 ranges from 0.01 μm to 0.03 μm.

[0044] In this embodiment, the ion implantation regions 101 on both sides of the gate 110 are the source region 101a and the drain region 101b, respectively. The width of the portion of the ion implantation region 101 with the second depth H2 is related to the thickness of the second sidewall 121 removed in step S02. The greater the thickness of the second sidewall 121 etched in step S02, the wider the exposed surface in the first sidewall 120, and the wider the width of the ion implantation region 101 below the exposed first sidewall 120 (i.e., the portion of the ion implantation region 101 with the second depth H2).

[0045] It should be noted that, since the second depth H2 of the portion of the ion implantation region 101 near the gate 110 is less than the first depth H1 of the portion of the ion implantation region 101 away from the gate 110, the junction depth of the portion of the ion implantation region 101 away from the gate 110 (i.e., the portion with the first depth H1) is deeper, and the junction depth of the portion of the ion implantation region 101 near the gate 110 (i.e., the portion with the second depth H2) is shallower, thereby suppressing the short-channel effect of the semiconductor device.

[0046] Furthermore, after the ion implantation process and before step S04, the semiconductor device manufacturing method of this embodiment further includes: performing an annealing process to repair the damage caused to the first sidewall 120 and the second sidewall 121 by the ion implantation process. Optionally, the annealing process is a rapid thermal annealing (RTA) process.

[0047] Then refer to Figure 7 Step S04 is executed to remove the second sidewall 121. In this embodiment, a wet etching process is used to remove the second sidewall 121.

[0048] It should be noted that during the removal of the second sidewall 121, the portion of the first sidewall 120 not covered by the second sidewall 121 (i.e., the portion of the first sidewall 120 away from the gate 110 and covering the substrate 100, and the portion of the first sidewall 120 near the top of the gate 110) is also removed, exposing the portion of the sidewall near the top of the gate 110 and the portion of the substrate 100 near the gate 110, thereby increasing the process window for the subsequent formation of the metal silicide barrier layer (not shown in the figure) and the process window for the subsequent metal interconnect process.

[0049] In addition, see Figure 8 In the semiconductor device manufacturing method described in this embodiment, after removing the second sidewall 121, the method further includes forming a metal silicide barrier layer 130 on the top of the gate 110, on the exposed sidewalls of the gate 110, and on the portion of the substrate 100 not covered by the first sidewall 120, to reduce resistance. Optionally, the thickness of the metal silicide barrier layer ranges from 100 μm to 200 μm.

[0050] contrast Figure 1 and Figure 8 As is known, in existing semiconductor devices, the depths of the source region 20 and drain region 30 are the same everywhere. As the device size shrinks, the distance between the source region 20 and drain region 30 and the channel gradually decreases, thereby aggravating the short-channel effect, DIBL effect, and GIDL effect of the semiconductor device, leading to increased channel leakage current and consequently a decrease in the breakdown voltage of the semiconductor device. In the semiconductor device manufacturing method described in this embodiment, the depth of different parts in the ion implantation region 101 is changed by controlling the morphology of the first sidewall 120 and the second sidewall 121, so that the second depth H2 of the part of the ion implantation region 101 near the gate 110 is smaller than the first depth H1 of the part of the ion implantation region 101 away from the gate 110, thereby suppressing the short-channel effect of the semiconductor device and achieving a reduction in the device size of the semiconductor device without affecting the device performance.

[0051] Furthermore, in existing semiconductor devices, the sidewalls of the gate 40 are covered by the sidewall 10, and the subsequently prepared metal silicide barrier layer (not shown in the figure) is only formed on the top of the gate 40 and the substrate surface. However, in the semiconductor device manufacturing method described in this embodiment, the metal silicide barrier layer 130 is not only formed on the top of the gate 110 and the surface of the substrate 100, but also on part of the sidewalls of the gate 110, thereby increasing the area of ​​the metal silicide barrier layer 130 and reducing the resistance.

[0052] In summary, this invention provides a method for manufacturing a semiconductor device, comprising: forming a gate on a substrate, wherein a first sidewall and a second sidewall are sequentially formed on the sidewalls of the gate, the first sidewall covering a portion of the substrate on both sides of the gate, and the second sidewall covering the side and top surfaces of the first sidewall; removing a portion of the second sidewall to expose the top surface of the portion of the first sidewall covering the substrate; performing an ion implantation process to form an ion implantation region in the substrate on both sides of the gate not covered by the second sidewall, wherein the portion of the ion implantation region away from the gate and not covered by the first sidewall has a first depth, and the portion of the ion implantation region near the gate and covered by the first sidewall has a second depth, the first depth being greater than the second depth; and removing the second sidewall. This invention controls the morphology of the first and second sidewalls to change the depth of different portions of the ion implantation region, making the second depth of the portion of the ion implantation region near the gate less than the first depth of the portion of the ion implantation region away from the gate, thereby reducing the short-channel effect of the semiconductor device while shortening the sidewall width, so as to reduce the device size of the semiconductor device without affecting device performance.

[0053] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, on which a gate is formed, a first sidewall is formed on the sidewall of the gate and the first sidewall covers a portion of the substrate on both sides of the gate, a second sidewall is formed on the first sidewall and the second sidewall covers the side and top surface of the first sidewall; the first sidewall has an L-shaped cross-section along the extension direction perpendicular to the gate. Remove a portion of the second sidewall to expose the top surface of the portion of the first sidewall covering the substrate, and expose the portion of the first sidewall near the top of the gate. An ion implantation process is performed to form ion implantation regions in the substrate on both sides of the gate that are not covered by the second sidewall. The portion of the ion implantation region away from the gate and not covered by the first sidewall has a first depth, and the portion of the ion implantation region near the gate and covered by the first sidewall has a second depth, wherein the first depth is greater than the second depth; and... Remove the second sidewall.

2. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, After the ion implantation process but before removing the second sidewall, the procedure further includes: An annealing process is performed to repair the damage to the first and second sidewalls caused by the ion implantation process.

3. The method for manufacturing a semiconductor device as described in claim 2, characterized in that, The annealing process is a rapid thermal annealing process.

4. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The second sidewall was removed using a wet etching process.

5. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, After removing the second sidewall, the following is also included: A metal silicide barrier layer is formed on the top of the gate, the exposed sidewalls of the gate, and the portion of the substrate not covered by the first sidewall.

6. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The first sidewall includes a silicon oxide layer and a silicon nitride layer, the silicon oxide layer covering the sidewall of the gate and a portion of the substrate, the silicon nitride layer being formed on the surface of the silicon oxide layer, and the second sidewall being a silicon oxide layer.

7. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The energy from the ion implantation can penetrate the first sidewall to the substrate.

8. The method for manufacturing a semiconductor device as described in claim 1, characterized in that, The method for manufacturing the semiconductor device is used to manufacture MOS devices.

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