Chip insulating layer manufacturing method and wafer insulating layer manufacturing method

Abstract

The application discloses a chip insulating layer manufacturing method and a wafer insulating layer manufacturing method. The chip is provided with a slot hole. The chip insulating layer manufacturing method comprises the following steps: providing a silk screen provided with a shielding part; laying the silk screen on the surface of the chip, and the shielding part at least partially covers the slot hole; printing insulating layer material on the surface of the chip through the silk screen; removing the silk screen, so that the insulating layer material slides along the inner wall of the slot hole and at least covers part of the inner surface of the slot hole; and solidifying the insulating layer material to form an insulating layer. The chip insulating layer manufacturing method can reduce the amount of insulating layer material in the slot hole in the chip packaging process, and can reduce the chip warping problem caused by too much insulating layer material in the slot hole.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor packaging technology, and in particular, to a method for manufacturing a chip insulating layer and a method for manufacturing a wafer insulating layer. BACKGROUND

[0002] At present, in the packaging process of a wafer, there is too much SMF photoresist (insulating layer) in the slot hole, which cannot be controlled, causing the wafer to have a large warpage after the photoresist is cured, which seriously affects the packaging (such as BGA, LM, etc.) of the subsequent process; due to too much SMF photoresist in the slot hole, the metal layer in the slot hole is cracked during the reliability test of the chip, causing the failure of the reliability of the chip.

[0003] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the background of the present application and should not be taken as an acknowledgment or any form of suggestion that this information forms prior art that is publicly known. SUMMARY

[0004] The present application aims to provide a method for manufacturing a chip insulating layer and a method for manufacturing a wafer insulating layer, which can reduce the amount of insulating layer material in the slot hole in the chip packaging process and reduce the warpage problem of the chip caused by too much insulating layer material in the slot hole.

[0005] To achieve the above-mentioned purpose, the embodiment of the present application provides a method for manufacturing a chip insulating layer, a slot hole is formed on the chip, and the method comprises the following steps: providing a screen, a shielding part is formed on the screen; laying the screen on the surface of the chip, the shielding part at least partially covers the slot hole; printing insulating layer material on the surface of the chip through the screen; removing the screen, so that the insulating layer material slides along the inner wall of the slot hole and covers at least part of the inner surface of the slot hole; curing the insulating layer material to form an insulating layer.

[0006] In one or more embodiments of the present application, before the step of curing the insulating layer material to form an insulating layer, the method further comprises the following steps: printing the insulating layer material on the surface of the chip through the screen multiple times; removing the screen, so that the insulating layer material slides along the inner wall of the slot hole and covers the inner surface of the slot hole.

[0007] In one or more embodiments of the present application, the shielding part corresponds to the slot hole of the chip.

[0008] In one or more embodiments of the present application, the shape of the shielding part of the screen is adapted to the shape of the slot hole of the chip.

[0009] In one or more embodiments of the present application, a gap is formed between the edge of the shielding part of the screen and the edge of the slot hole of the chip.

[0010] In one or more embodiments of the present application, the projection of the shielding portion of the wire mesh in the direction perpendicular to the thickness direction of the chip falls within the slot of the chip.

[0011] In one or more embodiments of the present application, the shielding portion of the wire mesh can be combined by a plurality of shielding portion units, and a gap is formed between adjacent shielding portion units.

[0012] In one or more embodiments of the present application, the shape of the shielding portion unit can be one or more of a circle, a square, a triangle, a strip, a polygon, or a special shape.

[0013] In one or more embodiments of the present application, a support portion is provided on the wire mesh; when the wire mesh is laid on the surface of the chip, the support portion is located within the slot of the chip.

[0014] In one or more embodiments of the present application, when the wire mesh is laid on the surface of the chip, the surface of the support portion is not in complete contact with the inner wall of the slot of the chip.

[0015] In one or more embodiments of the present application, the height of the support portion of the wire mesh is not greater than the depth of the slot of the chip.

[0016] In one or more embodiments of the present application, the support portion is provided corresponding to the shielding portion.

[0017] In one or more embodiments of the present application, the insulating layer material includes epoxy resin.

[0018] An embodiment of the present application also provides a method for manufacturing an insulating layer of a wafer, the wafer comprising a plurality of arranged chip units, each chip unit being formed with a slot, and adjacent chip units being formed with a cutting channel, the method comprising: providing a wire mesh, the wire mesh being formed with a shielding portion; laying the wire mesh on the surface of the wafer, the shielding portion at least partially covering the slot and the cutting channel; printing an insulating layer material on the surface of the wafer through the wire mesh; removing the wire mesh, so that the insulating layer material slides along the inner wall of the slot and covers at least part of the inner surface of the slot; and curing the insulating layer material to form an insulating layer.

[0019] In one or more embodiments of the present application, a support portion is provided on the wire mesh, the support portion being provided corresponding to the shielding portion; when the wire mesh is laid on the surface of the wafer, the support portion is located within the cutting channel of the wafer.

[0020] Compared with the prior art, the chip insulating layer manufacturing method and the wafer insulating layer manufacturing method according to the embodiments of the present application use a screen with a shielding part to print the chip surface insulating layer, which can reduce the amount of insulating layer material in the slot hole in the chip packaging process and reduce the chip warping problem caused by too much insulating layer material in the slot hole. The screen is patterned, and the shielding part is formed on the screen mainly at the position of the slot hole of the chip, so as to reduce the amount of insulating layer material in the slot hole during printing.

[0021] The chip insulating layer manufacturing method and the wafer insulating layer manufacturing method according to the embodiments of the present application are suitable for all packaging processes that form slot holes, especially the TSV packaging process, and can specifically limit the amount of insulating layer material in the slot hole in the TSV packaging process. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a process flow chart of the chip insulating layer manufacturing method according to an embodiment of the present application;

[0023] Figure 2 is a packaging step sectional view of the chip insulating layer manufacturing method according to embodiment 1 of the present application;

[0024] Figure 3 is a screen structure diagram in the chip insulating layer manufacturing method according to an embodiment of the present application;

[0025] Figure 4 is a screen structure diagram in the chip insulating layer manufacturing method according to another embodiment of the present application.

[0026] Figure 5 is a packaging step sectional view of the chip insulating layer manufacturing method according to embodiment 2 of the present application.

[0027] Figure 6 is a process flow chart of the wafer insulating layer manufacturing method according to an embodiment of the present application;

[0028] Figure 7 is a packaging step sectional view of the wafer insulating layer manufacturing method according to embodiment 1 of the present application;

[0029] Figure 8 is a packaging step sectional view of the wafer insulating layer manufacturing method according to embodiment 2 of the present application. DETAILED DESCRIPTION

[0030] The specific embodiments of the present application are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present application is not limited by the specific embodiments.

[0031] Unless specifically stated otherwise, throughout the specification and claims, the term "comprising" or variations such as "comprise" or "comprises" will be understood to imply the inclusion of a stated element or group of elements but not the exclusion of any other element or group of elements.

[0032] As described in the background, in the existing wafer or chip packaging process, the insulating layer material in the slot hole is laid in excess, causing the wafer or chip to be greatly warped after solidification, affecting the subsequent packaging.

[0033] In order to solve the above technical problems, the application creatively proposes a chip insulating layer manufacturing method and a wafer insulating layer manufacturing method. By screen patterning, a shielding part is formed on the screen to reduce the amount of insulating layer material in the slot hole during printing.

[0034] As shown in Figure 1 The chip insulating layer manufacturing method according to an embodiment of the application comprises: s1 providing a screen, the screen having a shielding part formed thereon; s2 laying the screen on the surface of the chip, the shielding part at least partially covering the slot hole of the chip; s3 printing the insulating layer material on the surface of the chip through the screen; s4 removing the screen, causing the insulating layer material to slide along the inner wall of the slot hole and at least cover part of the inner surface of the slot hole; and s5 solidifying the insulating layer material to form an insulating layer.

[0035] It can be understood that the chip has a first surface and a second surface arranged oppositely, the chip has a functional area formed on the first surface and a solder pad coupled to the functional area, in the packaging process of the chip (especially the tsv packaging process), a through hole or slot hole exposing the solder pad of the chip is usually formed on the second surface of the chip, and a metal layer electrically connected to the solder pad is formed on the second surface of the chip and the inner wall of the through hole or slot hole, and then an insulating layer is formed on the metal layer to electrically isolate the metal layer (except for the position where the solder bump is formed) from the outside to protect the metal layer.

[0036] In the application, the screen is specially patterned and laid on the second surface of the chip, so that the shielding part thereon at least partially covers the slot hole on the chip. When printing the insulating layer material, the shielding part can block a large amount of insulating layer material from flowing into the slot hole of the chip, so as to control the amount of insulating layer material in the slot hole.

[0037] For example, referring to Figure 2 , the chip insulating layer manufacturing method according to an embodiment of the application comprises the following steps. Figure 2is a cross-sectional view of the chip packaging step. The packaging structure includes a chip 10, a solder pad 20, a slot hole 30, and a metal layer 40. The solder pad 20 is formed on the first surface of the chip 10. The slot hole 30 is formed on the second surface of the chip 10 and exposes the solder pad 20. The metal layer 40 covers the second surface of the chip 10 and extends on the inner wall of the slot hole 30, and is electrically connected between the solder pad 20.

[0038] The shielding part A on the screen corresponds to the slot hole 30 of the chip 10, so that when the screen is laid on the surface of the chip 10, the shielding part A of the screen can partially cover the slot hole 30 on the chip 10. For example, the shape of the shielding part A of the screen is adapted to the shape of the slot hole 30 of the chip 10. The projection of the shielding part A of the screen in the direction perpendicular to the thickness of the chip 10 falls into the slot hole 30 of the chip 10. For example, a gap is formed between the edge of the shielding part A of the screen and the edge of the slot hole 30 of the chip 10, so that when the insulating layer material is printed on the screen, the insulating layer material can partially slide along the gap and cover part of the inner surface of the slot hole 30.

[0039] Referring to Figure 3 As shown, the shielding part A of the screen can be composed of a plurality of shielding part units A1 arranged in combination, and a gap is formed between adjacent shielding part units. The shape of the shielding part unit can be one or more of circular, square, triangular, strip, polygonal, or irregular shape. The shape of the shielding part A is not limited, as long as it has a certain blocking effect on the slot hole of the chip.

[0040] Referring to Figure 4 As shown, the shielding part A of the screen can be composed of a plurality of shielding part units A1 arranged in combination, and a gap is formed between adjacent shielding part units. The shape of the shielding part unit can be one or more of circular, square, triangular, strip, polygonal, or irregular shape. The shape of the shielding part A is not limited, as long as it has a certain blocking effect on the slot hole of the chip.

[0041] In addition, before the step of curing the insulating layer material to form the insulating layer, the method for manufacturing the insulating layer of the chip further comprises: printing the insulating layer material on the surface of the chip through the screen multiple times; removing the screen, so that the insulating layer material slides along the inner wall of the slot hole and covers the inner surface of the slot hole. In the above technical solution, multiple printing can make the amount of insulating layer material sufficient to cover the inner surface of the slot hole, so as to prevent the insulating layer from not covering the metal layer completely, affecting the effect of the subsequent packaging body.

[0042] Referring to Figure 5 As shown, in another embodiment of the present application, a support part B is further provided on the screen, and the support part B is arranged corresponding to the shielding part A. When the screen is laid on the surface of the chip 10, the support part B is located in the slot hole 30 of the chip 10. The provision of the support part B can improve the strength of the screen itself, and can also make the screen placed on the surface of the chip have a certain supporting strength, preventing the insulating layer material from pressing the screen into the slot hole during printing, affecting the printing effect of the insulating layer material.

[0043] In one embodiment, the height of the support portion B of the screen is no greater than the depth of the slot 30 of the chip 10, and the surface of the support portion B is not in complete contact with the inner wall of the slot of the chip 10. This allows the insulating layer material of the screen shielding portion A and the edge of the slot 30 to flow smoothly along the inner wall of the slot 30 into the slot 30, thus covering the inner surface of the slot 30. The support portion B being located within the slot 30 reduces the volume within the slot 30 and the amount of insulating layer material flowing into the slot 30. Preferably, the insulating layer material is epoxy resin.

[0044] like Figure 6 As shown, a method for fabricating a wafer insulating layer according to an embodiment of the present invention includes: s10 providing a screen with a shielding portion formed thereon; s20 laying the screen onto the wafer surface, the shielding portion at least partially covering wafer vias and dicing channels on the wafer; s30 screen printing an insulating layer material onto the wafer surface; s40 removing the screen, allowing the insulating layer material to slide down the inner wall of the vias and at least cover a portion of the inner surface of the vias; and s50 curing the insulating layer material to form an insulating layer.

[0045] Understandably, reference Figure 7 As shown, the wafer includes a plurality of arranged chip cells 100, each chip cell having a via 101 formed thereon, the via 101 exposing the bonding pads 102 of the chip cell 100. A dicing channel 103 is formed between adjacent chip cells 100. Specifically, the dicing channel 103 is located between two vias 101 of adjacent chip cells 100, and the top of the sidewall of the dicing channel 103 is partially etched so that the height H of the dicing channel 103 is less than the thickness I of the wafer.

[0046] In this invention, the screen is specially patterned and laid on the wafer surface, so that the shielding part on it is located above the dicing channel 103 and partially covers the slot near the dicing channel 103. When printing the insulating layer material, the shielding part can prevent the insulating layer material from flowing into the slot of the wafer in large quantities, so as to control the amount of insulating layer material in the slot.

[0047] For example, refer to Figure 7 As shown, Figure 7 This is a partial cross-sectional view of the wafer packaging process. The packaging structure includes a chip cell 100, solder pads 102, vias 101, a metal layer 400, and dicing channels 103. Each chip cell 100 includes solder pads 102. The vias 101 are formed on the chip cell 100 and expose the solder pads 102. The dicing channels 103 are located between adjacent chip cells 100. The metal layer 400 is formed on the surface of the chip cell 100 away from the solder pads 102 and extends on the inner surface of the vias 101, electrically connecting to the solder pads 102.

[0048] The shielding portion A on the screen corresponds to the via hole 101 of the chip unit 100. Specifically, the shielding portion A is located above the cutting channel 103 and partially covers the via hole 101 close to the cutting channel 103, so that when the screen is laid on the wafer surface, the shielding portion A of the screen can partially cover the via hole 101 on the chip unit 100 and the cutting channel 103 between adjacent chip units 100. A gap is formed between the edge of the shielding portion A of the screen and the edge of the via hole 101 of the chip unit 100, so that when the insulating layer material is printed on the screen, the insulating layer material can partially slide along the gap and cover part of the inner surface of the via hole 101.

[0049] The shielding portion A of the screen can be composed of a plurality of shielding portion units arranged in combination, and a gap is formed between adjacent shielding portion units. The shape of the shielding portion unit can be one or more of a circle, a square, a triangle, a strip, a polygon, or a special shape. The shape of the shielding portion A is not limited, as long as it has a certain blocking effect on the via hole of the chip. The shielding portion A of the screen can also be a whole strip structure, which extends along the arrangement direction of the chip via hole, so that when the screen is placed on the chip surface, the shielding portion A can partially cover the via hole.

[0050] In addition, before the step of curing the insulating layer material to form the insulating layer, the method for manufacturing the wafer insulating layer further comprises: printing the insulating layer material on the wafer surface through the screen multiple times; removing the screen, so that the insulating layer material slides along the inner wall of the via hole and covers the inner surface of the via hole. In the above technical solution, multiple printing can make the amount of insulating layer material sufficient to cover the inner surface of the via hole, so as to prevent the insulating layer from not covering the metal layer completely and affecting the subsequent package effect.

[0051] Reference Figure 8 As shown in another embodiment of the present application, a supporting portion B is further provided on the screen, and the supporting portion B corresponds to the shielding portion A. When the screen is laid on the wafer surface, the supporting portion B is located in the cutting channel 103 between adjacent chip units 100. The provision of the supporting portion B can improve the strength of the screen itself, and can also make the screen have a certain supporting strength when it is placed on the wafer surface, so as to prevent the insulating layer material from pressing the screen into the via hole during printing and affecting the printing effect of the insulating layer material. The supporting portion B is located in the cutting channel 103, which can reduce the volume of the cutting channel 103 and reduce the amount of insulating layer material flowing into the via hole 101 and the cutting channel 103. The insulating layer material is preferably epoxy resin.

[0052] Compared with the prior art, the manufacturing method of the chip insulation layer of the embodiment of the application uses a screen with a shielding part to print and manufacture the chip surface insulation layer, which can reduce the amount of insulation layer material in the slot hole in the chip packaging process and reduce the chip warping problem caused by too much insulation layer material in the slot hole. Among them, the screen is patterned, and a shielding part is formed on the screen mainly for the position of the slot hole of the chip, so as to achieve the effect of reducing the insulation layer material in the slot hole during printing.

[0053] The manufacturing method of the chip insulation layer of the embodiment of the application is suitable for all packaging processes forming slot holes, especially the TSV packaging process, and can specifically limit the amount of insulation layer material in the slot hole in the TSV packaging process.

[0054] Aspects, embodiments, features, and examples of the application are to be considered in all respects as illustrative only and not restrictive, the scope of the application being defined only by the claims. Other embodiments, modifications, and uses will occur to those skilled in the art upon consideration of the specification, and it is intended to include all such embodiments, modifications, and uses within the scope of the application. It will be apparent to one of ordinary skill in the art that aspects, embodiments, features, and examples of the application can be practiced in other ways than those specifically set forth herein without departing from the spirit and scope of the claimed application.

[0055] The use of the title and sections in this application is not meant to limit the application; each section can apply to any aspect, embodiment, or feature of the application.

[0056] Throughout this application, where compositions, processes, means, methods, etc. are described as having, including, or comprising specific components, steps, etc., it is contemplated to also consist essentially thereof, and that the compositions, processes, means, methods, etc. also can include other components, steps, etc. in addition to or instead of those recited.

[0057] In this application, where an element or component is said to be included in or selected from a list of recited elements or components, it should be understood that the element or component can be any one of the recited elements or components individually and can be selected from a group consisting of two or more of the recited elements or components. Further, it should be understood that elements and / or limitations described herein can be combined in a manner not specifically set forth in the descriptions and / or claims herein without departing from the spirit and scope of the present disclosure.

[0058] The use of the terms "including," "containing," "having," "with," etc. generally should be understood to be open-ended and not limiting.

[0059] The use of the singular herein includes the plural (and vice versa) unless specifically stated otherwise. Additionally, the use of "one" and "the" to describe singular elements includes the plural unless the context clearly dictates otherwise. Further, the use of the term "about" in connection with a quantity is inclusive of the specific quantity plus or minus ten percent unless specifically stated otherwise.

[0060] It should be understood that the order of steps or order for performing certain actions is immaterial so long as the present teachings remain operable. Moreover, two or more steps or actions can be conducted simultaneously.

[0061] It is to be understood that the figures and descriptions of the present application have been simplified to illustrate elements that are relevant for a clear understanding of the present application, while eliminating, for the purpose of clarity, other elements. Those of ordinary skill in the art will recognize that other elements can be desirable in a particular implementation. However, because such elements are well known in the art, and because they do not facilitate a better understanding of the present application, a discussion of such elements is not provided herein. It should be appreciated that the various figures are presented for purposes of illustration and not as constructive schematics. Omitted details and alternate embodiments are within the purview of one of ordinary skill in the art.

[0062] It can be appreciated that in certain aspects of the application, a single component can be replaced by multiple components and multiple components can be replaced by a single component to provide an element or a structure or to perform one or more given functions. Except where such substitution would not operate to practice particular embodiments of the present application, such substitution is considered within the scope of the present application.

[0063] While the present application has been described with reference to illustrative embodiments, those with ordinary skill in the art will understand that various other modifications, omissions, and / or additions can be made without departing from the spirit and scope of the present application. Additionally, many modifications can be made to adapt a particular situation or material to the teachings of the present application without departing from the scope of the application. Accordingly, the present application is not intended to be limited to the particular disclosed embodiments, but rather is to be given broadest interpretation of the appended claims so as to encompass all embodiments falling within the scope of the claims. Furthermore, to the extent that the terms first, second, etc. are used herein to describe various elements or

[0064] The foregoing description of specific exemplary embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. It is intended that the scope of the application be limited not with this detailed description, but rather by the claims appended hereto.

Claims

1. A method for manufacturing an insulating layer of a chip, a through-hole being formed in the chip, characterized by, The method comprises: providing a screen having a shielding portion formed thereon; laying the screen on the chip surface, the shielding portion at least partially covering the via hole; printing an insulation layer material through the screen on the chip surface; removing the screen, so that the insulation layer material slides along the inner wall of the via hole and covers at least part of the inner surface of the via hole; curing the insulation layer material to form an insulation layer.

2. The method for fabricating a chip insulating layer as described in claim 1, characterized in that, Before the step of curing the insulation layer material to form an insulation layer, the method further comprises: printing the insulation layer material through the screen on the chip surface for multiple times; removing the screen, so that the insulation layer material slides along the inner wall of the via hole and covers the inner surface of the via hole.

3. The method for fabricating a chip insulating layer as described in claim 1, characterized in that, The shielding portion corresponds to the via hole of the chip; and / or, The insulation layer material comprises epoxy resin.

4. The method for fabricating a chip insulating layer as described in claim 3, characterized in that, The shielding portion of the screen is shaped to fit the shape of the via hole of the chip; and / or, The projection of the shielding portion of the screen in the direction perpendicular to the thickness direction of the chip falls into the via hole of the chip.

5. The method for fabricating a chip insulating layer as described in claim 4, characterized in that, A gap is formed between the edge of the shielding portion of the screen and the edge of the via hole of the chip.

6. The method for fabricating a chip insulating layer as described in claim 1, characterized in that, The shielding portion of the screen is composed of multiple shielding portion units, and a gap is formed between adjacent shielding portion units.

7. The method for fabricating a chip insulating layer as described in claim 6, characterized in that, The shielding portion unit is circular, square, triangular, strip-shaped, polygonal or irregularly shaped.

8. The method for fabricating a chip insulating layer as described in claim 1, characterized in that, The screen is provided with a supporting portion; When the screen is laid on the chip surface, the supporting portion is located in the via hole of the chip.

9. The method for fabricating a chip insulating layer as described in claim 8, characterized in that, When the screen is laid on the chip surface, the surface of the supporting portion is not in complete contact with the inner wall of the via hole of the chip; and / or, The supporting portion corresponds to the shielding portion.

10. The method for fabricating a chip insulating layer as described in claim 9, characterized in that, The height of the supporting portion of the screen is not greater than the depth of the via hole of the chip.

11. A method for manufacturing an insulating layer of a wafer, the wafer comprising a plurality of arranged chip units, each chip unit being formed with a slot hole, and a cutting channel being formed between adjacent chip units, characterized in that, The method comprises: providing a screen having a shielding portion formed thereon; laying the screen on the wafer surface, the shielding portion at least partially covering the via hole and the cutting channel; printing an insulation layer material through the screen on the wafer surface; removing the screen, so that the insulation layer material slides along the inner wall of the via hole and covers at least part of the inner surface of the via hole; curing the insulation layer material to form an insulation layer.

12. The method of claim 11, wherein the step of forming the insulating layer is performed by a method selected from the group consisting of sputtering, vacuum deposition, and plasma CVD. The screen is provided with a supporting portion, which corresponds to the shielding portion; When the screen is laid on the wafer surface, the supporting portion is located in the cutting channel of the wafer.

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