A SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance

Abstract

The present invention relates to the technical field of power electronic device packaging and integration, and particularly to a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance, which includes a metal substrate, a positive power terminal, a negative power terminal, an AC terminal, an upper half-bridge SiC MOS chip, a lower half-bridge SiC MOS chip, a bottom chip, a top DBC substrate serving as an AC terminal lead-out layer, an intermediate DBC substrate serving as a negative terminal lead-out layer, a bottom DBC substrate serving as a positive terminal lead-out layer, and power loop metal posts; the upper half-bridge SiC MOS chip is connected to the copper layer of the top DBC substrate through the power loop metal posts; the lower half-bridge SiC MOS chip is connected to the copper layer of the bottom DBC substrate through the power loop metal posts. The present invention adopts a multi-layer stacked double-sided structure, so that the commutation path is a vertical commutation structure, which not only reduces the area of the commutation loop, but also generates good negative mutual inductance cancellation through the opposite current flow directions of each layer, optimizing the commutation path of the module.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic device packaging and integration, and particularly to a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance. Background Technique

[0002] In recent years, wide bandgap (WBG) semiconductor devices represented by silicon carbide (SiC) have developed rapidly. Compared with traditional silicon devices, SiC has many excellent characteristics such as a higher breakdown electric field strength (4 - 20 times), a larger bandgap (3 times), a lower intrinsic carrier concentration (10 - 35 orders of magnitude), a higher thermal conductivity (3 - 13 times), and a larger saturated electron drift velocity (2 - 2.5 times). Moreover, due to the limitations of silicon devices in terms of a blocking voltage of 6.5 kV and an operating temperature of 175 °C, and their relatively slow switching speed, they are restricted in many applications. Therefore, SiC power devices have greater potential and broad development prospects, and are more suitable than silicon devices for many applications such as electric vehicle charging piles and motor drive systems, photovoltaic inverters, multi-electric aircraft, ship power systems, and DC circuit breakers in the power grid.

[0003] In the production and manufacturing process of SiC devices, in order to improve the yield of chips, the area of a single SiC device is usually small, which further results in a small current capacity of a single SiC device. To further increase the current capacity of SiC devices, a module packaging method is usually adopted to parallelly integrate and package multiple chips. Currently, the packaging and integration technology of SiC devices still follows the packaging technology of traditional Si devices, which brings some problems. For example, the parasitic inductance introduced by the traditional bonding wire structure is relatively large, and the power loop is often limited to a planar loop, which leads to extremely severe voltage overshoot and oscillation when SiC devices are switched at high speed; another example is the traditional single-sided heat dissipation structure, where the chip can only dissipate heat from one side, which causes SiC devices to overheat severely due to limited heat dissipation capacity under high-frequency operating conditions. The above reasons prevent the advantages of fast switching speed and small switching loss of SiC devices from being truly realized, and have become a technical bottleneck restricting the development of the entire industry.

[0004] At present, some optimization design methods and strategies have been proposed for the problem of high parasitic inductance in SiC modules, including layout optimization of the main power loop, layout optimization of the drive loop, and adjustment of terminal structures, etc. However, since the bond wire structure is still not eliminated, the parasitic inductance of the improved module is reduced limitedly and remains between 10 nH and 20 nH. In addition, some solutions have also been proposed for the heat dissipation problem of SiC modules, such as using sintered silver to replace traditional solder, using substrates, potting materials with better thermal performance, and practical double-sided cooling heat dissipation structures, etc. Among them, the method of using materials with better thermal performance has the best effect, but it often depends to a large extent on the characteristics of the material itself, and it is difficult to find materials with comprehensive functions, so it has not been widely used. In contrast, the method of eliminating the bond wire structure has obvious improvement in problems such as thermal failure and welding failure, and is easy to implement. Summary of the Invention

[0005] Aiming at the problems existing in the prior art, the present invention provides a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance to reduce the parasitic inductance of the module, improve the heat dissipation ability, and have no additional requirements for new materials or complex process manufacturing methods.

[0006] A SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance includes a metal substrate, a positive power terminal, a negative power terminal, an AC terminal, an upper half-bridge silicon carbide MOS chip, a lower half-bridge silicon carbide MOS chip, a bottom layer chip, a top layer DBC substrate as the AC terminal lead-out layer, an intermediate layer DBC substrate, a bottom layer DBC substrate as the bottom layer of the half-bridge module, and a power loop metal column; copper layers are provided on the surfaces of the top layer DBC substrate, the intermediate layer DBC substrate, and the bottom layer DBC substrate;

[0007] The positive power terminal is connected to the copper layer on the upper surface of the bottom layer DBC substrate; the AC terminal is connected to the top layer DBC substrate;

[0008] The upper half-bridge silicon carbide MOS chip is fixed on the bottom layer DBC substrate and is equipped with an anti-parallel SBD diode. The source terminal of the upper half-bridge silicon carbide MOS chip is connected to the copper layer of the top layer DBC substrate through a power loop metal column;

[0009] The lower half-bridge silicon carbide MOS chip is fixed on the top layer DBC substrate and is equipped with an anti-parallel SBD diode. The source terminal of the lower half-bridge silicon carbide MOS chip is connected to the copper layer of the bottom layer DBC substrate through a power loop metal column;

[0010] The negative power terminal is connected to the copper layer on the upper surface of the intermediate layer DBC substrate, and a via hole structure for realizing a current path is provided between the intermediate layer DBC substrate and the bottom layer DBC substrate.

[0011] Preferably, both the upper half-bridge silicon carbide MOS chip and the lower half-bridge silicon carbide MOS chip include four parallel-connected silicon carbide MOS chips.

[0012] Preferably, the four parallel-connected silicon carbide MOS chips of each half-bridge are all connected in parallel with two anti-parallel SBD diodes.

[0013] Preferably, the positive power terminal and the negative power terminal are located on the same side.

[0014] Preferably, the AC terminal faces in the opposite direction to the positive power terminal.

[0015] Preferably, the top DBC substrate, the middle DBC substrate, and the bottom DBC substrate are all made of materials with a Cu-Al2O3-Cu structure.

[0016] Preferably, the AC terminal, the positive power terminal, the negative power terminal, and the metal substrate are all made of electrolytic copper materials.

[0017] Preferably, the power loop metal posts are made of metal copper or metal molybdenum.

[0018] Preferably, the internal voids of the module are potted with silicone gel.

[0019] Compared with the prior art, the present invention has at least the following beneficial effects:

[0020] The present invention adopts a multi-layer stacked double-sided structure, which is divided into three layers in total. Each layer is a DBC substrate with a Cu-Al2O3-Cu structure. The bottom layer is the upper half-bridge of the half-bridge module and is connected to the positive terminal. The bottom layer chips are interconnected with the top layer through metal posts. The top layer is the AC terminal lead-out layer. To achieve a double-sided heat dissipation structure, the lower half-bridge silicon carbide MOS chips are welded to the corresponding positions on the top layer and are interconnected with the bottom layer through metal posts. The middle layer is connected to the negative terminal, and a current path from the bottom layer to the middle layer is established using a through-hole structure to form a complete loop. Among them, the bottom layer and the middle layer are in a stacked structure with through-holes as connection paths. Considering requirements such as insulation and reliability, a certain distance is left between the top layer and the middle layer.

[0021] The present invention makes the commutation path a vertical commutation structure through the multi-layer stacked structure, which not only reduces the commutation loop area but also generates a good negative mutual inductance cancellation through the opposite current flow directions of each layer, optimizing the commutation path of the module.

[0022] The present invention integrates four chips in parallel, with each pair of chips paired with an anti-parallel SBD. The upper half-bridge silicon carbide MOS chips are soldered to the bottom DBC substrate. The metal column connection is used instead of the bonding wire structure to directly connect the upper surface of the chips to the top DBC copper layer. The lower half-bridge silicon carbide MOS chips are soldered to the top DBC substrate and connected to the copper layer of the bottom DBC substrate through metal columns. The metal column structure is adopted to increase the reliability of the module, and at the same time, both the upper and lower substrates can dissipate heat, greatly improving the heat dissipation performance of the module. Description of the Drawings

[0023] Figure 1 It is a schematic diagram of the overall structure of a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to the present invention;

[0024] Figure 2 It is an exploded view of the internal structure of a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to the present invention;

[0025] Figure 3 It is the layout of the top DBC substrate in a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to the present invention;

[0026] Figure 4 It is the layout of the middle DBC substrate in a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to the present invention;

[0027] Figure 5 It is the layout of the bottom DBC substrate in a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to the present invention;

[0028] Figure 6 It is a schematic diagram of the metal substrate in a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to the present invention.

[0029] The reference numerals are: 1, positive power terminal; 2, negative power terminal; 3, AC terminal; 4, silicon carbide MOS chip; 5, anti-parallel SBD diode; 6, power loop metal column; 7, drive loop metal column; 8, via structure; 9, metal substrate. Detailed Embodiments

[0030] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] The present invention discloses a SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance, which includes a metal substrate 9, a positive power terminal 1, a negative power terminal 2, an AC terminal 3, an upper half-bridge SiC MOS chip 4, a lower half-bridge SiC MOS chip 4, a bottom layer chip, a top layer DBC substrate serving as the lead-out layer of the AC terminal 3, an intermediate layer DBC substrate, a bottom layer DBC substrate serving as the upper half-bridge in the half-bridge module, and a power loop metal post 6; copper layers are provided on the surfaces of the top layer DBC substrate, the intermediate layer DBC substrate, and the bottom layer DBC substrate. In this embodiment, the top layer DBC substrate, the intermediate layer DBC substrate, and the bottom layer DBC substrate are all made of materials with a Cu-Al₂O₃-Cu structure, the thickness of the copper layer is 0.3 mm, and the thickness of the intermediate ceramic layer is 0.64 mm.

[0032] The positive power terminal is connected to the copper layer on the upper surface of the bottom layer DBC substrate; the AC terminal 3 is connected to the top layer DBC substrate, the negative power terminal is connected to the copper layer on the upper surface of the intermediate layer DBC substrate, and a via hole structure 8 for realizing the current path is provided between the intermediate layer DBC substrate and the bottom layer DBC substrate. Among them, the AC terminal 3, the positive power terminal 1, the negative power terminal 2, and the metal substrate 9 are all made of electrolytic copper materials. The positive power terminal 1 and the negative power terminal 2 are located on the same side, and the orientation of the AC terminal 3 is opposite to that of the positive power terminal 1.

[0033] The upper half-bridge SiC MOS chip 4 is fixed on the bottom layer DBC substrate and is equipped with an anti-parallel SBD diode 5. The source end of the upper half-bridge SiC MOS chip 4 is connected to the copper layer of the top layer DBC substrate through the power loop metal post 6; the lower half-bridge SiC MOS chip 4 is fixed on the top layer DBC substrate and is equipped with an anti-parallel SBD diode 5. The source end of the lower half-bridge SiC MOS chip 4 is connected to the copper layer of the bottom layer DBC substrate through the power loop metal post 6. Among them, both the upper half-bridge SiC MOS chip 4 and the lower half-bridge SiC MOS chip 4 include four parallel-connected SiC MOS chips 4, and the four parallel-connected SiC MOS chips 4 of each half-bridge are all connected in parallel with two anti-parallel SBD diodes 5. Among them, the power loop metal post 6 is prepared from metal copper or metal molybdenum.

[0034] Drive loop metal posts 7 are provided at the gate drive ends of the upper half-bridge SiC MOS chip 4 and the lower half-bridge SiC MOS chip 4 for realizing the connection of the drive loop.

[0035] Limited by the module volume, the module adopts a symmetric distribution; to ensure the reliability and insulation strength of the module, the internal gaps of the module are filled with silicone gel.

[0036] The overall current loop of the module flows from the bottom layer to the top layer and then back to the bottom layer. Finally, through the negative via structure 8, the current path from the bottom layer to the negative terminal of the middle layer is realized. The metal substrate 9 is interconnected with the bottom DBC substrate and the top DBC substrate to achieve a double-sided heat dissipation path.

[0037] Due to the adoption of the vertical commutation double-sided structure, the commutation loop path is optimized. Therefore, taking Cree's commercial 62mm package as an example, the overall size of the present invention is only 50% of the 62mm package. It can be known from MAXWELL simulation that when the upper half-bridge is conducting, the module can withstand a breakdown voltage of 3.3kV and a working current of 100A. The maximum surface field strength of the ceramic is 1.4×10 6 V·m -1 , and the maximum surface current density is only 4.3×10 6 A / m 2 . It can be known from Q3D simulation that the parasitic inductance of the overall power loop of the module is 1.4nH. In terms of heat dissipation, in order to achieve good heat dissipation effect, a radiator needs to be installed at the bottom of the metal substrate. It can be known from ICEPAK simulation that when the forced air cooling heat dissipation method is adopted, the fan speed is set to 6m / s, and under the condition that the average chip loss per piece is 70W, the overall heat dissipation effect of the module is good after adding the radiator.

[0038] The above are only the preferred embodiments of the present invention, and are not used to limit the technical solutions of the present invention. Those skilled in the art should understand that without departing from the spirit and principles of the present invention, the technical solutions can be modified and replaced simply in several ways, and these modifications and replacements also fall within the protection scope covered by the claims.

Claims

1. A SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance, characterized in that, It includes a metal substrate (9), a positive power terminal (1), a negative power terminal (2), an AC terminal (3), an upper half-bridge silicon carbide MOS chip (4), a lower half-bridge silicon carbide MOS chip (4), a bottom layer chip, a top layer DBC substrate as the lead-out layer of the AC terminal (3), a middle layer DBC substrate, a bottom layer DBC substrate as the bottom layer of the upper half-bridge in the half-bridge module, and a power loop metal column (6); copper layers are provided on the surfaces of the top layer DBC substrate, the middle layer DBC substrate, and the bottom layer DBC substrate. The positive power terminal is connected to the copper layer on the upper surface of the bottom layer DBC substrate; the AC terminal (3) is connected to the top layer DBC substrate. The upper half-bridge silicon carbide MOS chip (4) is fixed on the bottom layer DBC substrate and is equipped with an anti-parallel SBD diode (5). The source terminal of the upper half-bridge silicon carbide MOS chip (4) is connected to the copper layer of the top layer DBC substrate through the power loop metal column (6). The lower half-bridge silicon carbide MOS chip (4) is fixed on the top layer DBC substrate and is equipped with an anti-parallel SBD diode (5). The source terminal of the lower half-bridge silicon carbide MOS chip (4) is connected to the copper layer of the bottom layer DBC substrate through the power loop metal column (6). The negative power terminal is connected to the copper layer on the upper surface of the middle layer DBC substrate, and a via hole structure (8) for realizing the current path is provided between the middle layer DBC substrate and the bottom layer DBC substrate.

2. The SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to claim 1, characterized in that Both the upper half-bridge silicon carbide MOS chip (4) and the lower half-bridge silicon carbide MOS chip (4) include four parallel-connected silicon carbide MOS chips (4).

3. The SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to claim 2, characterized in that, The four parallel-connected silicon carbide MOS chips (4) of each half-bridge are all connected in parallel with two anti-parallel SBD diodes (5).

4. The SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to claim 1, wherein The positive power terminal (1) and the negative power terminal (2) are located on the same side.

5. The SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to claim 4, wherein, The AC terminal (3) is oriented in the opposite direction to the positive power terminal (1).

6. The SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to claim 1, characterized in that, The top layer DBC substrate, the middle layer DBC substrate, and the bottom layer DBC substrate are all made of materials with a Cu-Al₂O₃-Cu structure.

7. The SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to claim 1, wherein The AC terminal (3), the positive power terminal (1), the negative power terminal (2), and the metal substrate (9) are all made of red copper material.

8. The SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to claim 1, wherein The power loop metal column (6) is prepared from metal copper or metal molybdenum.

9. The SiC double-sided cooling module with low parasitic inductance and high heat dissipation performance according to claim 1, characterized in that, The internal voids of the module are potted with silicone gel.

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