Vertical silicon carbide device integrated with schottky diode and method of manufacture

Abstract

The present invention relates to a vertical silicon carbide device integrated with a Schottky diode and a method of manufacturing the same. The device includes a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide epitaxial layer, a first conductivity type current spreading layer, a second conductivity type base region, and a first conductivity type source region, which are sequentially arranged. The device further includes a trench gate electrode and a Schottky metal layer, which is located on a side of the first conductivity type current spreading layer away from the first conductivity type silicon carbide substrate, and a projection of the Schottky metal layer on the first conductivity type silicon carbide substrate is adjacent to a projection of the second conductivity type base region on the first conductivity type silicon carbide substrate. By integrating a Schottky diode structure inside a vertical silicon carbide device, the reverse recovery characteristics of the device are improved, and a smaller chip area can be achieved compared to an integrated structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power devices, and more specifically to a vertical silicon carbide device integrating a Schottky diode and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC), a third-generation semiconductor material, has a larger bandgap and a higher critical breakdown field strength than silicon. Compared to silicon power devices of the same voltage rating, SiC has a higher doping concentration and a smaller epitaxial layer thickness, thus significantly reducing forward on-resistance and power loss. Simultaneously, SiC possesses high thermal conductivity, high-temperature resistance, and a high electron saturation velocity, making it suitable for high-current, high-power applications. This reduces the requirements for heat dissipation equipment, shrinks device size, improves reliability, and lowers costs. Therefore, SiC is considered an important development direction for next-generation high-efficiency power electronic devices.

[0003] Unlike traditional silicon-based MOSFETs, silicon carbide MOSFETs offer superior temperature stability, low on-resistance, and fast switching speeds, making them ideal for high-frequency, high-temperature environments. This reduces switching losses, shortens switching transients, and increases operating frequency. Due to their excellent performance, silicon carbide power MOSFETs are widely used in new energy vehicles, high-power power supplies, and aerospace, and have become one of the most widely applied and promising power devices in the market.

[0004] However, traditional MOSFET structures have many problems. The parasitic diodes in the MOSFET have poor reverse recovery performance when the device is turned off, which limits its application in the high-frequency direction. Furthermore, connecting an external Schottky barrier diode (SBD) in reverse parallel will not only increase the circuit module area but also introduce additional parasitic effects. Summary of the Invention

[0005] In view of this, the present invention provides a vertical silicon carbide device with integrated Schottky diode and a method for manufacturing the same, with the aim of improving the reverse recovery characteristics of the device, while achieving a smaller chip area compared to the integrated structure.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A vertical silicon carbide device integrating a Schottky diode includes: a first conductivity type silicon carbide substrate, a first conductivity type silicon carbide epitaxial layer, and a first conductivity type current spreading layer sequentially stacked in a layered structure, wherein the first conductivity type silicon carbide epitaxial layer is located on one side of the first conductivity type silicon carbide substrate, and the first conductivity type current spreading layer is located on the side of the first conductivity type silicon carbide epitaxial layer away from the first conductivity type silicon carbide substrate.

[0008] The device further includes a second conductivity type base region located on the side of the first conductivity type current extension layer away from the first conductivity type silicon carbide substrate; and a first conductivity type source region located on the surface of the second conductivity type base region away from the first conductivity type silicon carbide substrate.

[0009] A trench gate electrode is located on the side of the first conductivity type current extension layer away from the first conductivity type silicon carbide substrate, and the projection of the trench gate electrode on the first conductivity type silicon carbide substrate does not overlap with the projection of the first conductivity type source region on the first conductivity type silicon carbide substrate.

[0010] A Schottky metal layer is located on the side of the first conductivity type current extension layer away from the first conductivity type silicon carbide substrate. The projection of the Schottky metal layer on the first conductivity type silicon carbide substrate is adjacent to the projection of the second conductivity type base region on the first conductivity type silicon carbide substrate, and the projection of the Schottky metal layer on the first conductivity type silicon carbide substrate does not overlap with the projection of the trench gate electrode on the first conductivity type silicon carbide substrate.

[0011] A first insulating layer covers at least the trench gate electrode and the Schottky metal layer on the surface of the silicon carbide substrate away from the first conductivity type, and at least partially exposes the source region of the first conductivity type and the base region of the second conductivity type. A first electrode layer and a second electrode layer are also present, wherein the first electrode layer is located on the side of the first insulating layer away from the silicon carbide substrate of the first conductivity type; and the second electrode layer is located on the surface of the silicon carbide substrate of the first conductivity type away from the silicon carbide epitaxial layer of the first conductivity type.

[0012] Furthermore, the device also includes a second conductivity type doped layer, which is located on the side surface of the first conductivity type current extension layer away from the first conductivity type silicon carbide substrate. The second conductivity type doped layer includes a first sub-part, the projection of the first sub-part onto the first conductivity type silicon carbide substrate at least partially overlapping the projection of the Schottky metal layer onto the first conductivity type silicon carbide substrate.

[0013] Furthermore, the projection of the first sub-part onto the first conductivity type silicon carbide substrate overlaps the projection of the Schottky metal layer onto the first conductivity type silicon carbide substrate.

[0014] Furthermore, the second conductivity type doped layer includes a second sub-section, the projection of the second sub-section onto the first conductivity type silicon carbide substrate at least partially overlapping the projection of the trench gate electrode onto the first conductivity type silicon carbide substrate.

[0015] Furthermore, the first sub-part and the second sub-part have the same doping concentration.

[0016] Furthermore, the device also includes a first groove and a second groove, the first groove and the second groove at least penetrating the first conductivity type source region, the second conductivity type base region and at least a portion of the first conductivity type current extension layer; the trench gate electrode is disposed in the first groove and the Schottky metal layer is disposed in the second groove.

[0017] Furthermore, the device also includes a gate oxide layer located within the first groove, and the projection of the gate oxide layer on the first conductivity type silicon carbide substrate covers the projection of the first groove on the first conductivity type silicon carbide substrate.

[0018] Furthermore, the second conductivity type base region includes a second conductivity type heavily doped portion, and the projection of the second conductivity type heavily doped portion on the first conductivity type silicon carbide substrate is adjacent to the projection of the Schottky metal layer on the first conductivity type silicon carbide substrate.

[0019] Furthermore, the second conductivity type base region also includes a second conductivity type channel portion adjacent to the second conductivity type heavily doped portion, the doping concentration of the second conductivity type heavily doped portion is higher than the doping concentration of the second conductivity type channel portion, and the length of the second conductivity type channel portion is 0.5-8μm along a first direction, wherein the first direction is the direction in which the second conductivity type heavily doped portion points to the trench gate electrode.

[0020] Furthermore, the first conductivity type is N-type, and the second conductivity type is P-type.

[0021] This invention reintegrates Schottky diodes in a vertical silicon carbide device. Compared to parasitic PIN diodes formed by the bulk P-type base region and N-type drift region in traditional devices, the Schottky diode structure does not have a conductivity modulation effect. It can quickly extract the non-equilibrium carriers stored in the device, reduce the reverse recovery charge of the device in the off state, and thus improve the reverse recovery capability of the device.

[0022] This invention further incorporates a second conductivity type doped layer below the trench gate electrode and below the Schottky metal layer. This second conductivity type doped layer acts as a cutoff for electric field lines, terminating the electric field lines in the region below the trench within the second sub-section. This prevents the electric field lines from entering the gate oxide layer, reducing the hot electron effect and its impact on the threshold voltage and transconductance. It also reduces the oxide electric field at the corners. Simultaneously, a JFET effect is formed between two adjacent second conductivity type doped layers, reducing gate oxide electric field spikes while protecting the Schottky junction formed between the Schottky metal and the first conductivity type current spreading layer.

[0023] This invention also discloses a method for manufacturing a vertical silicon carbide device with an integrated Schottky diode, comprising the following steps:

[0024] A silicon carbide substrate of the first conductivity type is provided.

[0025] A first-conductivity silicon carbide epitaxial layer and a first-conductivity current spreading layer structure are epitaxially formed on one side surface of the first-conductivity silicon carbide substrate.

[0026] A second conductivity type base region is formed on the surface of the first conductivity type current extension layer on the side away from the first conductivity type silicon carbide substrate.

[0027] A first conductivity type source region is formed by regional ion implantation on the surface of the second conductivity type base region away from the first conductivity type silicon carbide substrate.

[0028] The selected area is etched with trenches to form a first groove and a second groove, wherein the first groove and the second groove penetrate at least the first conductivity type source region, the second conductivity type base region and at least part of the first conductivity type current extension layer.

[0029] A gate oxide layer is grown by thermal oxidation on the side of the first groove away from the silicon carbide substrate of the first conductivity type.

[0030] A trench gate electrode is deposited on the side of the gate oxide layer away from the silicon carbide substrate of the first conductivity type.

[0031] A Schottky metal layer is deposited on the surface of the second groove on the side away from the first conductivity type silicon carbide substrate.

[0032] A first insulating layer is formed on the surface of the trench gate electrode and the Schottky metal layer away from the silicon carbide substrate of the first conductivity type. The first insulating layer at least covers the surface of the trench gate electrode and the Schottky metal layer away from the silicon carbide substrate of the first conductivity type, and at least partially exposes the source region of the first conductivity type and the base region of the second conductivity type.

[0033] A first electrode layer is formed on the side of the first insulating layer away from the first conductivity type silicon carbide substrate, and a second electrode layer is formed on the surface of the first conductivity type silicon carbide substrate away from the first conductivity type silicon carbide epitaxial layer.

[0034] Furthermore, after the steps of forming the first and second grooves, the following steps are also included:

[0035] A second conductivity type doped layer is regionally implanted within the first and second grooves, the second conductivity type doped layer being located on the side surface of the first conductivity type current extension layer away from the first conductivity type silicon carbide substrate.

[0036] The second conductivity type doped layer includes a first sub-part and a second sub-part, wherein the projection of the first sub-part on the first conductivity type silicon carbide substrate at least partially overlaps with the projection of the Schottky metal layer on the first conductivity type silicon carbide substrate; and the projection of the second sub-part on the first conductivity type silicon carbide substrate at least partially overlaps with the projection of the trench gate electrode on the first conductivity type silicon carbide substrate.

[0037] Furthermore, prior to the step of forming a first conductivity type source region on the surface of the second conductivity type base region away from the first conductivity type silicon carbide substrate by regional ion implantation, the method further includes a step of regional ion implantation of a second conductivity type heavily doped portion outside the second conductivity type base region.

[0038] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A schematic cross-sectional view of a vertical silicon carbide device 100 integrating a Schottky diode, provided in an embodiment of the present invention;

[0041] Figure 2 A schematic cross-sectional view of a vertical silicon carbide device 100 integrating a Schottky diode, provided in an embodiment of the present invention;

[0042] Figure 3 A schematic cross-sectional view of a vertical silicon carbide device 100 integrating a Schottky diode, provided in an embodiment of the present invention;

[0043] Figure 4 (a)-(g) are schematic diagrams illustrating the steps of a vertical silicon carbide device manufacturing method for an integrated Schottky diode according to the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] Figure 1 This is a schematic cross-sectional view of a vertical silicon carbide device 100 integrating a Schottky diode, provided in an embodiment of the present invention. Figure 1 As shown, this embodiment of the invention provides a vertical silicon carbide device 100 integrating a Schottky diode, comprising: a first conductivity type silicon carbide substrate 101, a first conductivity type silicon carbide epitaxial layer 102, and a first conductivity type current spreading layer 103 sequentially stacked in a layered structure, wherein the first conductivity type silicon carbide epitaxial layer 102 is located on one side of the first conductivity type silicon carbide substrate 101, and the first conductivity type current spreading layer 103 is located on the side of the first conductivity type silicon carbide epitaxial layer 102 away from the first conductivity type silicon carbide substrate 101.

[0046] As an optional implementation, the first conductivity type is N-type and the second conductivity type is P-type. If the first conductivity type is P-type, then the second conductivity type is N-type, and the corresponding device structure will be adjusted accordingly, which will not be elaborated here. The following embodiments are all illustrated using the first conductivity type as N-type and the second conductivity type as P-type.

[0047] As an optional implementation, the first conductivity type silicon carbide substrate 101 can be N... + The substrate, and the silicon carbide epitaxial layer 102 of the first conductivity type, can be lightly doped with N. - In the drift region, the first conductivity type current extension layer 103 can be N + Current spreading layer. Where N... - The doping concentration range can be 10 13 ~10 17 cm -3 N +The doping concentration range can be 10 15 ~10 20 cm -3 .

[0048] The device 100 further includes a second conductivity type base region 1041, which is located on the side of the first conductivity type current extension layer 103 away from the first conductivity type silicon carbide substrate 101; and a first conductivity type source region 1042, which is located on the side surface of the second conductivity type base region 1041 away from the first conductivity type silicon carbide substrate 101.

[0049] As an optional implementation, the second conductivity type base region 1041 is a P-type base region, and the first conductivity type source region 1042 is an N-type base region. + Source region.

[0050] A trench gate electrode 105 is located on the side of the first conductivity type current extension layer 103 away from the first conductivity type silicon carbide substrate 101, and the projection of the trench gate electrode 105 on the first conductivity type silicon carbide substrate 101 does not overlap with the projection of the first conductivity type source region 1042 on the first conductivity type silicon carbide substrate 101. The trench gate electrode 105 structure avoids the parasitic junction field-effect transistor (JFET) region below the channel in traditional vertical power MOSFET structures, thus reducing on-resistance.

[0051] A Schottky metal layer 106 is located on the side of the first conductivity type current extension layer 103 away from the first conductivity type silicon carbide substrate 101. The projection of the Schottky metal layer 106 onto the first conductivity type silicon carbide substrate 101 is adjacent to the projection of the second conductivity type base region 1041 onto the first conductivity type silicon carbide substrate 101. The projection of the Schottky metal layer 106 onto the first conductivity type silicon carbide substrate 101 is a first projection, the projection of the second conductivity type base region 1041 onto the first conductivity type silicon carbide substrate 101 is a second projection, and the projection of the trench gate electrode 105 onto the first conductivity type silicon carbide substrate 101 is a third projection. The first projection is located at the end of the second projection away from the third projection, and the first projection and the third projection do not overlap.

[0052] As an optional implementation, the Schottky metal layer 106 is made of a high-barrier Schottky metal selected from titanium (Ti), platinum (Pt), nickel (Ni), molybdenum (Mo), and mixtures thereof. Preferably, it can be selected from titanium (Ti), nickel (Ni), and mixtures thereof.

[0053] A first insulating layer 107 covers at least one side surface of the trench gate electrode 105 and the Schottky metal layer 106 away from the first conductivity type silicon carbide substrate 101, and at least partially exposes the first conductivity type source region 1042 and the second conductivity type base region 1041.

[0054] A first electrode layer 108 and a second electrode layer 109 are located on the side of the first insulating layer 107 away from the first conductive type silicon carbide substrate 101; the second electrode layer 109 is located on the surface of the first conductive type silicon carbide substrate 101 away from the first conductive type silicon carbide epitaxial layer 102.

[0055] By replacing the original ohmic contact with a Schottky contact, an integrated Schottky diode (SBD) structure is formed that is connected in reverse parallel with the traditional MOSFET device. Since the Schottky contact has the characteristic of low turn-on voltage, when a voltage is applied to the source, the SBD structure will conduct preferentially when the device is operating in reverse, thereby reducing the time for unbalanced carriers to be removed from the device and improving the reverse recovery capability of the device.

[0056] Furthermore, Figure 2 This is a schematic cross-sectional view of a vertical silicon carbide device 100 integrating a Schottky diode according to an embodiment of the present invention. As shown, the device 100 further includes a second conductivity type doped layer 110. As an optional embodiment, the second conductivity type doped layer 110 is P-type. + Heavily doped layers with doping concentrations ranging from 10 15 ~10 20 cm -3 The second conductivity type doped layer 110 is located on the side surface of the first conductivity type current extension layer 103 away from the first conductivity type silicon carbide substrate 101. The second conductivity type doped layer 110 includes a first sub-part 1101, the projection of the first sub-part 1101 on the first conductivity type silicon carbide substrate 101 at least partially overlapping the projection of the Schottky metal layer 106 on the first conductivity type silicon carbide substrate 101.

[0057] As an optional implementation, the projection of the first sub-part 1101 onto the first conductivity type silicon carbide substrate 101 covers the projection of the Schottky metal layer 106 onto the first conductivity type silicon carbide substrate 101.

[0058] Furthermore, the second conductivity type doped layer 110 includes a second sub-part 1102, the projection of the second sub-part 1102 on the first conductivity type silicon carbide substrate 101 at least partially overlapping the projection of the trench gate electrode 105 on the first conductivity type silicon carbide substrate 101.

[0059] As an optional implementation, the projection of the second sub-part 1102 onto the first conductivity type silicon carbide substrate 101 covers the projection of the trench gate electrode 105 onto the first conductivity type silicon carbide substrate 101.

[0060] As an optional implementation, to save on process steps, the first sub-part 1101 and the second sub-part 1102 can be fabricated in the same layer and with the same material, that is, with the same doping concentration, ranging from 10. 16 ~10 18 cm -3 .

[0061] Furthermore, the device 100 also includes a first groove and a second groove, the first groove and the second groove at least penetrating the first conductivity type source region 1042, the second conductivity type base region 1041 and at least a portion of the first conductivity type current extension layer 103; the trench gate electrode 105 is disposed in the first groove, and the Schottky metal layer 106 is disposed in the second groove.

[0062] As an optional implementation, the thickness of the first conductivity type current spreading layer 103 ranges from 3 to 20 μm. The depth of the first groove and / or the second groove is limited by the precision of the manufacturing process, and the groove depth is generally not less than 1 μm.

[0063] Because trench MOSFETs have lower reliability compared to planar MOSFETs, the sharp edges of the trenches in trench MOSFET devices will generate a spike electric field effect, introducing P near the source electrode. + The heavily doped second conductivity type doped layer 110 will effectively reduce the sharp electric field at the bottom of the trench structure.

[0064] Furthermore, such as Figure 1-2 As shown, the device 100 further includes a gate oxide layer 1051, which is located within the first groove, and the projection of the gate oxide layer 1051 on the first conductivity type silicon carbide substrate 101 covers the projection of the first groove on the first conductivity type silicon carbide substrate 101.

[0065] Furthermore, Figure 3 This is a schematic cross-sectional view of a vertical silicon carbide device 100 integrating a Schottky diode according to an embodiment of the present invention, as shown below. Figure 3As shown, the second conductivity type base region 1041 includes a second conductivity type heavily doped portion 1043, and the projection of the second conductivity type heavily doped portion 1043 on the first conductivity type silicon carbide substrate 101 is adjacent to the projection of the Schottky metal layer 106 on the first conductivity type silicon carbide substrate 101.

[0066] Furthermore, the second conductivity type base region 1041 also includes a second conductivity type channel portion 1044 adjacent to the second conductivity type heavily doped portion 1043. The doping concentration of the second conductivity type heavily doped portion 1043 is higher than that of the second conductivity type channel portion 1044. Along a first direction, the length of the second conductivity type channel portion 1044 is 0.5-8 μm, wherein the first direction is the direction in which the second conductivity type heavily doped portion 1043 points to the trench gate electrode 105.

[0067] This invention reintegrates Schottky diodes in a vertical silicon carbide device. Compared to parasitic PIN diodes formed by the bulk P-type base region and N-type drift region in traditional devices, the Schottky diode structure does not have a conductivity modulation effect. It can quickly extract the non-equilibrium carriers stored in the device, reduce the reverse recovery charge of the device in the off state, and thus improve the reverse recovery capability of the device.

[0068] This invention further incorporates a second conductivity type doped layer below the trench gate electrode and below the Schottky metal layer. This second conductivity type doped layer acts as a cutoff for electric field lines, terminating the electric field lines in the region below the trench within the second sub-section. This prevents the electric field lines from entering the gate oxide layer, reducing the hot electron effect and its impact on the threshold voltage and transconductance. It also reduces the oxide electric field at the corners. Simultaneously, a JFET effect is formed between two adjacent second conductivity type doped layers, reducing gate oxide electric field spikes while protecting the Schottky junction formed between the Schottky metal and the first conductivity type current spreading layer.

[0069] Figure 4 (a)-(g) are schematic diagrams illustrating the steps of a vertical silicon carbide device manufacturing method integrating a Schottky diode according to the present invention. The present invention also discloses a method for manufacturing a vertical silicon carbide device integrating a Schottky diode, such as... Figure 4 As shown, it includes the following steps:

[0070] like Figure 4 As shown in (a), a silicon carbide substrate 101 of a first conductivity type is provided.

[0071] A first conductivity type silicon carbide epitaxial layer 102 and a first conductivity type current spreading layer 103 are epitaxially formed on one side surface of the first conductivity type silicon carbide substrate 101.

[0072] like Figure 4 As shown in (b), a second conductivity type base region 1041 is formed on the surface of the first conductivity type current extension layer 103 away from the first conductivity type silicon carbide substrate 101.

[0073] A first conductivity type source region 1042 is formed on the side surface of the second conductivity type base region 1041 away from the first conductivity type silicon carbide substrate 101 by regional ion implantation.

[0074] like Figure 4 As shown in (c), trench etching is performed on the selected area to form a first groove 1031 and a second groove 1032. The first groove 1031 and the second groove 1032 penetrate at least the first conductivity type source region 1042, the second conductivity type base region 1041 and at least part of the first conductivity type current extension layer 103.

[0075] like Figure 4 As shown in (e), a gate oxide layer 1051 is thermally oxidized on the side of the first groove 1031 away from the silicon carbide substrate 101 of the first conductivity type.

[0076] A trench gate electrode 105 is deposited on the side of the gate oxide layer 1051 away from the silicon carbide substrate 101 of the first conductivity type.

[0077] like Figure 4 As shown in (f), a Schottky metal layer 106 is deposited on the surface of the second groove 1032 on the side away from the first conductivity type silicon carbide substrate 101.

[0078] A first insulating layer 107 is formed on the surface of the trench gate electrode 105 and the Schottky metal layer 106 away from the first conductivity type silicon carbide substrate 101. The first insulating layer 107 at least covers the surface of the trench gate electrode 105 and the Schottky metal layer 106 away from the first conductivity type silicon carbide substrate 101, and at least partially exposes the first conductivity type source region 1042 and the second conductivity type base region 1041.

[0079] like Figure 4 As shown in (g), a first electrode layer 108 is formed on the side of the first insulating layer 107 away from the first conductive type silicon carbide substrate 101, and a second electrode layer 109 is formed on the surface of the first conductive type silicon carbide substrate 101 away from the first conductive type silicon carbide epitaxial layer 102.

[0080] Furthermore, such as Figure 4 As shown in (d), after the step of forming the first groove 1031 and the second groove 1032, the following step is also included:

[0081] A second conductivity type doped layer 110 is regionally implanted within the first groove 1031 and the second groove 1032. The second conductivity type doped layer 110 is located on the side surface of the first conductivity type current extension layer 103 away from the first conductivity type silicon carbide substrate 101.

[0082] The second conductivity type doped layer 110 includes a first sub-part 1101 and a second sub-part 1102. The projection of the first sub-part 1101 onto the first conductivity type silicon carbide substrate 101 at least partially overlaps with the projection of the Schottky metal layer 106 onto the first conductivity type silicon carbide substrate 101. The projection of the second sub-part 1102 onto the first conductivity type silicon carbide substrate 101 at least partially overlaps with the projection of the trench gate electrode 105 onto the first conductivity type silicon carbide substrate 101.

[0083] Furthermore, such as Figure 4 As shown in (b), before the step of forming a first conductivity type source region 1042 on the side surface of the second conductivity type base region 1041 away from the first conductivity type silicon carbide substrate 101 by regional ion implantation, the step of regional ion implantation of a second conductivity type heavily doped portion 1043 on the outside of the second conductivity type base region 1041 is further included.

[0084] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated Schottky diode vertical silicon carbide device, characterized by, Comprising: a first conductivity type silicon carbide substrate; a first conductivity type silicon carbide epitaxial layer on a side of the first conductivity type silicon carbide substrate; a first conductivity type current spreading layer on a side of the first conductivity type silicon carbide epitaxial layer distal from the first conductivity type silicon carbide substrate; a second conductivity type base region on a side of the first conductivity type current spreading layer distal from the first conductivity type silicon carbide substrate; a first conductivity type source region on a side surface of the second conductivity type base region distal from the first conductivity type silicon carbide substrate; a trench gate electrode on a side of the first conductivity type current spreading layer distal from the first conductivity type silicon carbide substrate, a projection of the trench gate electrode on the first conductivity type silicon carbide substrate not overlapping a projection of the first conductivity type source region on the first conductivity type silicon carbide substrate; a Schottky metal layer on a side of the first conductivity type current spreading layer distal from the first conductivity type silicon carbide substrate, a projection of the Schottky metal layer on the first conductivity type silicon carbide substrate abutting a projection of the second conductivity type base region on the first conductivity type silicon carbide substrate, and a projection of the Schottky metal layer on the first conductivity type silicon carbide substrate not overlapping a projection of the trench gate electrode on the first conductivity type silicon carbide substrate; a first insulating layer covering at least a side surface of the trench gate electrode and the Schottky metal layer distal from the first conductivity type silicon carbide substrate, and at least partially exposing the first conductivity type source region and the second conductivity type base region; a first electrode layer on a side of the first insulating layer distal from the first conductivity type silicon carbide substrate; a second electrode layer on a side surface of the first conductivity type silicon carbide substrate distal from the first conductivity type silicon carbide epitaxial layer.

2. An integrated Schottky diode vertical silicon carbide device as set forth in claim 1, wherein, Further comprising: a second conductivity type doped layer on a side surface of the first conductivity type current spreading layer distal from the first conductivity type silicon carbide substrate, the second conductivity type doped layer including a first sub-portion, a projection of the first sub-portion on the first conductivity type silicon carbide substrate at least partially overlapping a projection of the Schottky metal layer on the first conductivity type silicon carbide substrate.

3. The integrated Schottky diode vertical silicon carbide device of Claim 2 wherein, the projection of the first sub-portion on the first conductivity type silicon carbide substrate covering the projection of the Schottky metal layer on the first conductivity type silicon carbide substrate.

4. The integrated Schottky diode vertical silicon carbide device of Claim 2 wherein, the second conductivity type doped layer including a second sub-portion, a projection of the second sub-portion on the first conductivity type silicon carbide substrate at least partially overlapping a projection of the trench gate electrode on the first conductivity type silicon carbide substrate.

5. An integrated Schottky diode vertical silicon carbide device as described in claim 4, wherein, the first sub-portion and the second sub-portion having a same doping concentration.

6. An integrated Schottky diode vertical silicon carbide device as described in claim 1, wherein, Comprising: a first recess and a second recess, the first recess and the second recess at least penetrating through the first conductive type source region, the second conductive type base region and at least part of the first conductive type current spreading layer; the trench gate electrode is disposed in the first recess, and the Schottky metal layer is disposed in the second recess.

7. An integrated Schottky diode vertical silicon carbide device as described in claim 6, wherein, Further comprising: a gate oxide layer, the gate oxide layer is located in the first recess, and a projection of the gate oxide layer on the first conductive type silicon carbide substrate covers a projection of the first recess on the first conductive type silicon carbide substrate.

8. The vertical silicon carbide device integrated with a Schottky diode according to claim 1, wherein the second conductive type base region comprises a second conductive type heavily doped portion, a projection of the second conductive type heavily doped portion on the first conductive type silicon carbide substrate is adjacent to a projection of the Schottky metal layer on the first conductive type silicon carbide substrate.

9. The integrated Schottky diode vertical silicon carbide device of Claim 8 wherein, the second conductive type base region further comprises a second conductive type channel portion adjacent to the second conductive type heavily doped portion, a doping concentration of the second conductive type heavily doped portion is higher than a doping concentration of the second conductive type channel portion, and a length of the second conductive type channel portion in a first direction is 0.5-8 μm, wherein the first direction is a direction in which the second conductive type heavily doped portion points to the trench gate electrode.

10. A method of fabricating an integrated Schottky diode vertical silicon carbide device, comprising: comprising the following steps: providing a first conductive type silicon carbide substrate; epitaxially growing a first conductive type silicon carbide epitaxial layer and a first conductive type current spreading layer structure on one side surface of the first conductive type silicon carbide substrate; forming a second conductive type base region on a side surface of the first conductive type current spreading layer away from the first conductive type silicon carbide substrate; forming a first conductive type source region on a side surface of the second conductive type base region away from the first conductive type silicon carbide substrate by means of regional ion implantation; performing trench etching on selected regions to form a first recess and a second recess, the first recess and the second recess at least penetrating through the first conductive type source region, the second conductive type base region and at least part of the first conductive type current spreading layer; thermally and oxidatively growing a gate oxide layer on a side surface of the first recess away from the first conductive type silicon carbide substrate; depositing a trench gate electrode on a side surface of the gate oxide layer away from the first conductive type silicon carbide substrate; depositing a Schottky metal layer on a side surface of the second recess away from the first conductive type silicon carbide substrate; forming a first insulating layer on a side surface of the trench gate electrode and the Schottky metal layer away from the first conductive type silicon carbide substrate, the first insulating layer at least covering the side surface of the trench gate electrode and the Schottky metal layer away from the first conductive type silicon carbide substrate, and at least partially exposing the first conductive type source region and the second conductive type base region; forming a first electrode layer on a side surface of the first insulating layer away from the first conductive type silicon carbide substrate, and forming a second electrode layer on a side surface of the first conductive type silicon carbide substrate away from the first conductive type silicon carbide epitaxial layer.

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