A method for manufacturing a two-dimensional material field effect transistor

Abstract

The application discloses a kind of two-dimensional material field effect transistor manufacturing method, belong to the field of semiconductor transistor, the method includes the following steps: directly growing two-dimensional material layer on substrate;Easy self-oxidizing metal layer is evaporated on the surface of two-dimensional material layer;Spin coating photoresist, exposure development, etching makes formation multiple array rectangular base two-dimensional material and metal structure, and photoresist is removed;Spin coating photoresist, source electrode and drain electrode are defined at rectangular edge by exposure development, obtain source electrode and drain electrode by deposition, remove photoresist;Spin coating channel photoresist, exposure and development, obtain channel pattern, make metal layer self-oxidize and obtain gate dielectric, deposit gate metal and etch off excess two-dimensional material layer;The application provides a kind of directly growing two-dimensional material layer on intrinsic silicon substrate, and two-dimensional material at channel is well protected, and clean two-dimensional material field effect transistor is obtained.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor transistors, and particularly relates to a manufacturing method of a two-dimensional material field effect transistor. BACKGROUND

[0002] In the past six decades, the research and development of micro-nano electronic devices has always followed Moore's Law. The continuous reduction in size has met the basic requirements of device driving force, power consumption, cost and clock effect. However, the development of Moore's Law has also made the traditional silicon-based devices gradually face the theoretical limits of power consumption and performance. Therefore, in order to effectively solve such problems, people have begun to conduct research on new materials, among which two-dimensional materials have received widespread attention in the field of micro-nano electronics research. However, the two-dimensional material field effect transistor process commonly used is to transfer a complete and high-quality two-dimensional material layer on a substrate, which is very challenging. It is very difficult to transfer the two-dimensional material grown on an intrinsic silicon substrate, and it is also extremely challenging to clean and smooth the transferred two-dimensional material. Therefore, it is necessary to develop a process for directly growing and preparing transistors on an intrinsic silicon substrate. SUMMARY

[0003] The application provides a manufacturing method of a two-dimensional material field effect transistor, which directly grows a two-dimensional material with high crystallinity on an intrinsic silicon substrate, and solves the deficiencies of the two-dimensional material transistor preparation process in the prior art.

[0004] In order to achieve the above-mentioned purpose, the application adopts the following technical scheme:

[0005] A manufacturing method of a two-dimensional material field effect transistor, comprising the following steps:

[0006] (1) directly growing a two-dimensional material layer on an intrinsic silicon substrate;

[0007] (2) depositing a layer of metal layer that is easy to self-oxidize on the surface of the two-dimensional material layer;

[0008] (3) spin-coating photoresist, exposing and developing, etching the exposed metal layer to form the actual required multi-array rectangular metal layer pattern, and removing the photoresist;

[0009] (4) spin-coating electrode photoresist, defining the specific positions of the source and drain through exposure on the edges of the rectangle, obtaining the source and drain through deposition, and removing the photoresist;

[0010] (5) spin-coating channel photoresist, exposing and developing to obtain the channel pattern, self-oxidizing the metal layer to obtain the gate dielectric, and depositing the gate metal to form the gate;

[0011] (6) etching away the excess two-dimensional material layer to form an array of two-dimensional material field effect transistors.

[0012] In the above steps, the growth method of the two-dimensional material layer in step (1) is chemical vapor deposition or physical vapor deposition; the deposition reaction temperature is 200-1500℃, and the deposition reaction time is 1-1000 minutes; the two-dimensional material layer is one or several of graphene, carbon nanotube, molybdenum disulfide, tungsten diselenide, vanadium selenide, phosphorene, tellurene, borophene, boron oxide, boron hydride, boron sulfide, boron phosphide, boron fluoride, molybdenum boride, iron boride, magnesium boride, boron carbonitride or organic boron compound;

[0013] In step (2), the metal is aluminum, nickel or titanium; the deposition method is thermal evaporation (TE), electron beam evaporation (EBE), atomic layer deposition (ALD) or magnetron sputtering; and the thickness of the metal is controlled to be 1-100 nm;

[0014] In step (3), the etching solution for etching the exposed metal aluminum and nickel is an iron chloride solution, and the etching solution for etching the exposed metal titanium is a hydrofluoric acid solution;

[0015] In step (4), the source electrode and the drain electrode are gold, silver, copper, platinum, nickel, cobalt, ruthenium, rhodium, palladium, osmium, iridium, chromium / gold, titanium / gold, titanium / silver, chromium / nickel, titanium / nickel, tantalum carbide, tungsten carbide or molybdenum carbide, and the thickness of the source electrode and the drain electrode is controlled to be 10-200 nm;

[0016] In step (5), the self-oxidation temperature of the metal layer is 20-100℃, and the time is 4-36 hours; the gate electrode is one or several alloys of gold, silver, copper, platinum, nickel, cobalt, ruthenium, rhodium, palladium, osmium and iridium, and the thickness of the gate electrode is controlled to be 60-600 nm;

[0017] In step (6), the method for etching the excess two-dimensional material is oxygen plasma etching or reactive ion etching; the etching treatment power is 50-500 W, and the treatment time is 5-30 minutes; and the flow rate of the oxygen plasma is 10-500 sccm;

[0018] The two-dimensional material field effect transistor prepared by the above method comprises a substrate, a two-dimensional material layer, a gate electrode, a source electrode, a drain electrode and a gate dielectric; the two-dimensional material layer is arrayed on the surface of the substrate, the gate dielectric is located on the surface of the two-dimensional material layer, the source electrode and the drain electrode are located at the edges of the gate dielectric, and the gate electrode is located on the surface of the gate dielectric;

[0019] The thickness of the two-dimensional material layer is 0.5-100 nm, the thickness of the source electrode and the drain electrode is controlled to be 10-200 nm, and the thickness of the gate dielectric layer is 1-100 nm;

[0020] The substrate material is intrinsic silicon or intrinsic silicon homogeneously epitaxially grown on the surface of P-type or N-type silicon.

[0021] Beneficial effects: This invention provides a method for manufacturing a two-dimensional material field-effect transistor, which directly grows a highly crystalline two-dimensional material on intrinsic silicon and fabricates a gate-controlled field-effect transistor. This not only effectively avoids contact with the solution during the transfer process, ensuring the thin film is not contaminated, but also guarantees an excellent interface between the two-dimensional semiconductor layer and the insulating dielectric, thus improving the transistor's performance. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of the aluminum / molybdenum disulfide / intrinsic silicon substrate after evaporation of metallic aluminum in Embodiment 1 of the present invention, wherein the left figure is a top view and the right figure is a side view;

[0023] Figure 2 This is a schematic diagram of the structure after etching the aluminum metal layer pattern in Embodiment 1 of the present invention, wherein the left figure is a top view and the right figure is a side view;

[0024] Figure 3 This is a schematic diagram of the source and drain electrodes prepared by deposition in Example 1 of the present invention, wherein the left figure is a top view and the right figure is a side view;

[0025] Figure 4 This is a schematic diagram of the channel structure after development in Embodiment 1 of the present invention, wherein the left figure is a top view and the right figure is a side view;

[0026] Figure 5 This is a schematic diagram of the structure of the gate dielectric formed by self-alumina in Embodiment 1 of the present invention, wherein the left figure is a top view and the right figure is a side view;

[0027] Figure 6 The schematic diagram of the structure after depositing gate metal in Embodiment 1 of the present invention is shown in the left figure as a top view and the right figure as a side view.

[0028] Figure 7 A schematic diagram of the transistor array structure after etching excess molybdenum disulfide in Embodiment 1 of the present invention, wherein the left figure is a top view and the right figure is a side view;

[0029] Figure 8 This is a schematic diagram of a single transistor structure in Embodiment 1 of the present invention. Detailed Implementation

[0030] The present application will now be described in detail with reference to specific embodiments and accompanying drawings:

[0031] Example 1

[0032] A method for fabricating a two-dimensional material field-effect transistor includes the following steps:

[0033] (1) A two-dimensional molybdenum disulfide material layer is directly grown on an intrinsic silicon substrate by chemical vapor deposition.

[0034] (2) A 100 nm thick layer of metallic aluminum is deposited on the surface of the molybdenum disulfide two-dimensional material layer to obtain an aluminum / molybdenum disulfide / intrinsic silicon substrate structure (e.g., Figure 1 (as shown);

[0035] (3) Spin-coat photoresist, expose and develop, etch exposed aluminum with sodium thiosulfate solution to expose molybdenum disulfide, forming a multi-array rectangular pattern of metallic aluminum, and remove the photoresist (e.g. Figure 2 (as shown);

[0036] (4) Spin-coating electrode photoresist: The specific positions of the source and drain electrodes are defined by exposure at the rectangular edge. A 100nm thick gold layer is deposited by electron beam evaporation to obtain the source and drain electrodes. The photoresist is then removed (e.g., ...). Figure 3 (as shown);

[0037] (5) Spin-coat the channel photoresist, expose and develop it to obtain the channel pattern (e.g., Figure 4 (as shown);

[0038] (6) Under air conditions, the aluminum metal at the channel is allowed to self-oxidize at 60°C for 12 hours to obtain the gate dielectric (aluminum oxide) (e.g. Figure 5 As shown), the gate electrode is obtained by electron beam deposition. The bottom layer of the gate electrode is a chromium layer with a thickness of 20 nm, and the top layer is a gold layer with a thickness of 100 nm (as shown). Figure 6 (as shown);

[0039] (7) Use oxygen plasma to etch the excess molybdenum disulfide to form a molybdenum disulfide field-effect transistor array (as shown in Example 7), and the structure of a single transistor is shown in Example 8.

[0040] Example 2

[0041] A method for fabricating a two-dimensional material field-effect transistor includes the following steps:

[0042] (1) A two-dimensional molybdenum boride material layer was directly grown on an intrinsic silicon substrate by physical vapor deposition.

[0043] (2) A layer of metallic nickel with a thickness of 20 nm was deposited on the surface of the molybdenum boride two-dimensional material layer to obtain a nickel / molybdenum boride / intrinsic silicon substrate structure;

[0044] (3) Spin-coat photoresist, expose and develop, etch exposed aluminum with ferric chloride solution to expose molybdenum boride, form a multi-array rectangular pattern of metallic nickel, and remove the photoresist.

[0045] (4) Spin-coating electrode photoresist: the specific positions of the source and drain are defined by exposure on the rectangular edge. Metal is deposited by vacuum evaporation, with a chromium layer at the bottom layer and a gold layer at the top layer, which is 20nm thick. The source and drain are obtained, and the photoresist is removed.

[0046] (5) Spin-coat the channel photoresist, expose and develop to obtain the channel pattern;

[0047] (6) Under air conditions, the metallic nickel at the channel is self-oxidized at 80°C for 10 hours to obtain the gate dielectric (nickel oxide). The gate electrode is obtained by electron beam deposition. The bottom layer of the gate electrode is a titanium layer with a thickness of 10 nm, and the top layer is a silver layer with a thickness of 50 nm to form the gate.

[0048] (7) Use reactive ion etching to etch excess molybdenum boride thin film to form molybdenum boride field effect transistor array.

[0049] Example 3

[0050] A method for fabricating a two-dimensional material field-effect transistor includes the following steps:

[0051] (1) Using chemical vapor deposition, a few layers of intrinsic silicon are homoepitaxially grown on the surface of P-type silicon, and then a two-dimensional phosphorene material layer is directly grown on the surface of intrinsic silicon.

[0052] (2) A layer of titanium metal with a thickness of 20 nm was deposited on the surface of the two-dimensional phosphorene material layer to obtain a titanium / phosphorene / intrinsic silicon substrate structure.

[0053] (3) Spin-coat photoresist, expose and develop, etch exposed titanium with hydrofluoric acid solution to expose phosphorusene, form a multi-array rectangular metallic titanium pattern, and remove photoresist.

[0054] (4) Spin-coating electrode photoresist: the specific positions of the source and drain are defined by exposure on the rectangular edge, and metal is deposited by vacuum evaporation. The bottom layer is a chromium layer with a thickness of 20nm and the top layer is a silver layer with a thickness of 100nm to obtain the source and drain. The photoresist is then removed.

[0055] (5) Spin-coat the channel photoresist, expose and develop to obtain the channel pattern;

[0056] (6) Under air conditions, the titanium metal in the channel is self-oxidized at 60°C for 10 hours to obtain the gate dielectric (titanium oxide). The gate electrode is obtained by electron beam deposition. The bottom layer of the gate electrode is a titanium layer with a thickness of 10 nm, and the top layer is a gold layer with a thickness of 50 nm to form the gate.

[0057] (7) Use oxygen plasma to etch the excess phosphorus film to form a phosphorus field-effect transistor array.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a two-dimensional material field-effect transistor, characterized in that, Includes the following steps: (1) Directly growing a two-dimensional material layer on an intrinsic silicon substrate; (2) Deposit a metal layer that is easily self-oxidized on the surface of the two-dimensional material layer; (3) Spin-coat photoresist, expose and develop, etch the exposed metal layer to form a multi-array rectangular metal layer pattern, and remove the photoresist; (4) Spin-coating electrode photoresist: the specific positions of the source and drain are defined by exposure at the edge of the rectangle, the source and drain are obtained by deposition, and the photoresist is removed. (5) Spin-coat the channel photoresist, expose and develop to obtain the channel pattern, allow the metal layer to self-oxidize to obtain the gate dielectric, and deposit the gate metal to form the gate. (6) Etch away the excess two-dimensional material layer to form a two-dimensional material field-effect transistor array.

2. The method for manufacturing a two-dimensional material field-effect transistor according to claim 1, characterized in that, The growth method of the two-dimensional material layer in step (1) is: chemical vapor deposition or physical vapor deposition, with a deposition reaction temperature of 200-1500℃ and a deposition reaction time of 1-1000 minutes.

3. The method for manufacturing a two-dimensional material field-effect transistor according to claim 1, characterized in that, The metal mentioned in step (2) is aluminum, nickel or titanium.

4. The method for manufacturing a two-dimensional material field-effect transistor according to claim 3, characterized in that, In step (3), the etchant used to etch the exposed aluminum and nickel is a ferric chloride solution, and the etchant used to etch the exposed titanium is a hydrofluoric acid solution.

5. The method for manufacturing a two-dimensional material field-effect transistor according to claim 1, characterized in that, The self-oxidation temperature of the metal layer in step (5) is 20-100℃, and the time is 4-36h.

6. The method for manufacturing a two-dimensional material field-effect transistor according to claim 1, characterized in that, The method for etching excess two-dimensional material in step (6) is: oxygen plasma etching or reactive ion etching, wherein the etching power is 50-500W and the processing time is 5-30 minutes.

7. A two-dimensional material field-effect transistor prepared by the method according to any one of claims 1-6, characterized in that, The transistor includes a substrate, a two-dimensional material layer, a gate, a source, a drain, and a gate dielectric; the two-dimensional material layer array is distributed on the surface of the substrate, the gate dielectric is located on the surface of the two-dimensional material layer, the source and drain are located at the edge of the gate dielectric, and the gate is located on the surface of the gate dielectric.

8. The two-dimensional material field-effect transistor according to claim 7, characterized in that, The thickness of the two-dimensional material layer is 0.5-100nm, the thickness of the source and drain electrodes is controlled between 10 and 200nm, the thickness of the gate dielectric layer is 1-100nm, and the thickness of the gate electrode is 60-600nm.

9. The two-dimensional material field-effect transistor according to claim 7 or 8, characterized in that, The two-dimensional material layer is one or more of graphene, carbon nanotubes, molybdenum disulfide, tungsten diselenide, vanadium selenide, phosphorene, tellurene, boronene, boron oxide, boron hydride, boron sulfide, boron phosphide, boron fluoride, molybdenum boride, iron boride, magnesium boride, boron carbon nitrogen, or organoboron compounds.

10. The two-dimensional material field-effect transistor according to claim 7, characterized in that, The substrate material is intrinsic silicon or intrinsic silicon homoepitaxially grown on the surface of P-type or N-type silicon.

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