A common-source common-gate type HEMT power device and a preparation method and chip thereof

Abstract

The application discloses a common-source common-gate type HEMT power device and a preparation method and a chip thereof. The buffer layer, the drift layer and the barrier layer are formed in a laminated mode on a semiconductor substrate, the barrier layer and the drift layer are isolated into multiple functional areas by a first electron gas isolation structure and a second electron gas isolation structure in contact with the buffer layer, the first source metal layer, the first drain metal layer, the first gate metal layer and the gate dielectric layer are formed in one of the functional areas, the second drain metal layer, the second source metal layer, the second Schottky metal layer and the cap layer are formed in another of the functional areas, and the cathode metal layer and the first Schottky metal layer are formed in a third of the functional areas. The integrated common-source common-gate type HEMT power device is formed by selectively connecting the metal layers, the parasitic capacitance and the parasitic inductance can be effectively reduced, the switching frequency of the device is improved, and the application scenarios of the HEMT power device are greatly expanded.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor device technology, and in particular relates to a common-source common-gate HEMT power device, a preparation method thereof, and a chip. Background Art

[0002] Gallium nitride high electron mobility transistors (GaN High Electron Mobility Transistors, GaNHEMTs) have very high switching frequencies and are suitable for high-frequency applications. However, in specific applications, when the switching frequency of power devices increases, the switching frequency of current silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) and GaN HEMT cascode power devices (Si MOS-GaN HEMT cascodes) is easily affected by parasitic capacitance, which greatly reduces the reverse recovery speed of the power devices. In addition, current GaN HEMTs lack parasitic diodes, which severely limits their application areas. Summary of the Invention

[0003] The present application provides a common-source and common-gate HEMT power device, a preparation method thereof, and a chip thereof, aiming to solve the technical problem that GaN HEMT cannot expand its application field due to device characteristic limitations.

[0004] In a first aspect, an embodiment of the present application provides a cascode HEMT power device, wherein the cascode HEMT power device comprises:

[0005] A semiconductor substrate, a buffer layer, a drift layer, and a barrier layer stacked in sequence;

[0006] a first electron gas isolation structure and a second electron gas isolation structure, formed in the barrier layer and the drift layer respectively, and contacting the buffer layer;

[0007] A cap layer and a gate dielectric layer are formed on the barrier layer respectively; wherein the gate dielectric layer and the cap layer are respectively located on both sides of the first electron gas isolation structure;

[0008] a first source metal layer, a first drain metal layer, and a first gate metal layer, wherein the first source metal layer and the first drain metal layer are respectively formed on both sides of the gate dielectric layer, and the first gate metal layer is formed on the gate dielectric layer;

[0009] A second drain metal layer and a second source metal layer are formed on both sides of the cap layer respectively;

[0010] A first Schottky metal layer is formed on the barrier layer; wherein the first Schottky metal layer and the second source metal layer are respectively located on both sides of the second electron gas isolation structure;

[0011] a cathode metal layer formed on the barrier layer and located adjacent to the first Schottky metal layer;

[0012] a second Schottky metal layer formed on the cap layer;

[0013] an insulating dielectric layer formed on the first gate metal layer, the first source metal layer, the first drain metal layer, the second source metal layer, the second drain metal layer, the cathode metal layer, and the barrier layer;

[0014] The first source metal layer, the second drain metal layer and the cathode metal layer are connected together through a first metal lead, and the first gate metal layer, the second source metal layer and the first Schottky metal layer are connected together through a second metal lead.

[0015] In one embodiment, the first source metal layer has an L-shaped structure; wherein a vertical portion of the first source metal layer contacts the barrier layer, and a dielectric material is filled between a horizontal portion of the first source metal layer and the first gate metal layer.

[0016] In one embodiment, the thickness of the first electron gas isolation structure and the second electron gas isolation structure is greater than or equal to the sum of the thickness of the barrier layer and the drift layer.

[0017] In one embodiment, the thickness of the first drain metal layer is greater than the thickness of the gate dielectric layer.

[0018] In one embodiment, the thickness of the second drain metal layer and the thickness of the second source metal layer are greater than the thickness of the capping layer.

[0019] In one embodiment, the first Schottky metal layer includes nickel and gold.

[0020] In one embodiment, the capping layer is made of P-type gallium nitride material; and / or

[0021] The barrier layer is made of gallium aluminum nitride material; and / or

[0022] The drift layer is made of gallium nitride material.

[0023] A second aspect of the present application further provides a method for preparing a cascode HEMT power device, the method comprising:

[0024] A buffer layer, a drift layer and a barrier layer are sequentially stacked on a semiconductor substrate;

[0025] forming a cap layer on the barrier layer, and forming a first isolation trench and a second isolation trench on both sides of the cap layer; wherein the first isolation trench and the second isolation trench extend deep into the buffer layer;

[0026] Filling the first isolation trench and the second isolation trench with an isolation material to form a first electron gas isolation structure and a second electron gas isolation structure in contact with the buffer layer;

[0027] forming a gate dielectric layer on the barrier layer; wherein the gate dielectric layer and the cap layer are respectively located on both sides of the first electron gas isolation structure;

[0028] forming an ohmic metal layer on the gate dielectric layer, the cap layer, and the barrier layer, and forming a first etched trench on the ohmic metal layer; wherein the first etched trench and the cap layer are respectively located on both sides of the second electron gas isolation structure;

[0029] Etching away the ohmic metal material above the capping layer to form a second etched trench, and filling the first etched trench and the second etched trench with a Schottky metal material to form a first Schottky metal layer in the first etched trench and a second Schottky metal layer in the second etched trench;

[0030] Performing patterned etching on the ohmic metal layer to form a first gate metal layer on the gate dielectric layer, forming a first source metal layer and a first drain metal layer on both sides of the gate dielectric layer, respectively, forming a second source metal layer and a second drain metal layer on both sides of the cap layer, and forming a cathode metal layer at a position adjacent to the first Schottky metal layer;

[0031] Filling a dielectric material on the first gate metal layer, the first source metal layer, the first drain metal layer, the second source metal layer, the second drain metal layer, the cathode metal layer and the barrier layer to form an insulating dielectric layer;

[0032] The first source metal layer, the second drain metal layer and the cathode metal layer are connected together using a first metal lead, and the first gate metal layer, the second source metal layer and the first Schottky metal layer are connected together using a second metal lead.

[0033] In one embodiment, the preparation method further comprises:

[0034] The first source metal layer is modified so that the first source metal layer has an L-shaped structure; wherein the vertical portion of the first source metal layer contacts the barrier layer, and a dielectric material is filled between the horizontal portion of the first source metal layer and the first gate metal layer.

[0035] A third aspect of the embodiments of the present application further provides a chip, comprising the cascode HEMT power device as described in any one of the above items; or comprising the cascode HEMT power device prepared by the preparation method described in any one of the above embodiments.

[0036] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0037] A buffer layer, a drift layer, and a barrier layer are stacked on a semiconductor substrate, and the barrier layer and the drift layer are isolated into multiple functional regions by a first electron gas isolation structure and a second electron gas isolation structure in contact with the buffer layer. A first source metal layer, a first drain metal layer, and a first gate metal layer are formed on the barrier layer in one of the functional regions, and a gate dielectric layer is provided between the first gate metal layer and the barrier layer, thereby forming a depletion mode high-voltage HEMT device. A second drain metal layer, a second source metal layer, and a second Schottky metal layer are formed in another functional region, and a cap layer is formed between the second Schottky metal layer and the barrier layer, thereby forming an enhancement mode low-voltage HEMT device. A cathode metal layer and a first Schottky metal layer are formed on the barrier layer in the energy region, thereby forming a Schottky diode structure. Finally, the first source metal layer, the second drain metal layer, and the cathode metal layer are connected together via a first metal lead, and the first gate metal layer, the second source metal layer, and the first Schottky metal layer are connected together via a second metal lead, thereby forming an integrated cascode HEMT power device. By controlling a depletion-mode high-voltage HEMT device with an enhanced-mode low-voltage HEMT device, parasitic capacitance and parasitic inductance can be effectively reduced, the switching frequency of the device can be increased, the reverse recovery speed can be improved, and the reverse recovery loss can be reduced, thereby greatly expanding the application scenarios of the HEMT power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic structural diagram of a cascode HEMT power device according to an embodiment of the present application;

[0039] Figure 2 A schematic structural diagram of a cascode HEMT power device according to another embodiment of the present application;

[0040] Figure 3 A schematic flow chart of a method for manufacturing a cascode HEMT power device according to an embodiment of the present application;

[0041] Figure 4 A schematic diagram of sequentially stacking a buffer layer 220 , a drift layer 310 , and a barrier layer 320 on a semiconductor substrate 210 according to an embodiment of the present application;

[0042] Figure 5 and Figure 6 A schematic diagram of forming a capping layer 820, a first isolation trench 401, and a second isolation trench 402 according to an embodiment of the present application;

[0043] Figure 7 A schematic diagram of forming a first electron gas isolation structure 710 and a second electron gas isolation structure 720 provided in an embodiment of the present application;

[0044] Figure 8 A schematic diagram of forming a gate dielectric layer 810 according to an embodiment of the present application;

[0045] Figure 9 A schematic diagram of forming a first etched trench 601 according to an embodiment of the present application;

[0046] Figure 10 and Figure 11 A schematic diagram of forming a first Schottky metal layer 610 and a second Schottky metal layer 520 according to an embodiment of the present application;

[0047] Figure 12 and Figure 13 A schematic diagram of forming a first source metal layer 410, a first drain metal layer 430, a second drain metal layer 530, a second source metal layer 510, and a cathode metal layer 620 according to an embodiment of the present application;

[0048] Figure 14 A schematic diagram of forming an insulating dielectric layer 830 according to an embodiment of the present application;

[0049] Figure 15 and Figure 16 A schematic diagram of a first source metal layer 410 forming an L-shaped structure according to an embodiment of the present application;

[0050] Figure 17 This is a schematic diagram of forming a first metal lead and a second metal lead according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0052] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0053] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0054] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0055] GaN HEMTs have very high switching frequencies and are suitable for high-frequency applications. However, in specific applications, when the switching frequency of power devices increases, the switching frequency of current silicon-based MOS devices and GaN HEMT cascode power devices is easily affected by parasitic capacitance, which greatly reduces the reverse recovery speed of the power devices. In addition, current GaN HEMTs do not have parasitic diodes, which severely limits their application areas.

[0056] In order to solve the above technical problems, the present invention provides a cascode HEMT power device. Figure 1 As shown, the cascode HEMT power device in this embodiment includes: a semiconductor substrate 210, a buffer layer 220, a drift layer 310, a barrier layer 320, a first electron gas isolation structure 710, a second electron gas isolation structure 720, a cap layer 820, a gate dielectric layer 810, a first source metal layer 410, a first drain metal layer 430, a first gate metal layer 420, a second drain metal layer 530, a second source metal layer 510, a first Schottky metal layer 610, a second Schottky metal layer 520, a cathode metal layer 620, and an insulating dielectric layer 830.

[0057] Specifically, the buffer layer 220, the drift layer 310 and the barrier layer 320 are sequentially stacked on the semiconductor substrate 210, and then the first electron gas isolation structure 710 and the second electron gas isolation structure 720 are respectively formed in the barrier layer 320 and the drift layer 310 by contacting the buffer layer 220, so as to isolate the barrier layer 320 and the drift layer 310 into a plurality of functional regions (for example, the functional region 110, the functional region 120 and the functional region 130 in FIG. 1). Figure 1 The cap layer 820 and the gate dielectric layer 810 are formed on the barrier layer 320 in two adjacent functional regions, wherein the gate dielectric layer 810 and the cap layer 820 are respectively located on two sides of the first electron gas isolation structure 710, as shown in FIG. 1. Figure 1 The gate dielectric layer 810 is located in the functional region 110, and the cap layer 820 is located in the functional region 120, and the functional region 110 and the functional region 120 are adjacent.

[0058] The first source metal layer 410 and the first drain metal layer 430 are respectively formed on two sides of the gate dielectric layer 810, and the first gate metal layer 420 is formed on the gate dielectric layer 810, so as to form a depletion mode high-voltage HEMT device (high-voltage d-mode HEMT) by the first source metal layer 410, the first drain metal layer 430, the first gate metal layer 420, the gate dielectric layer 810 and the barrier layer 320 and the drift layer 310 in the functional region. The second drain metal layer 530 and the second source metal layer 510 are formed on the barrier layer 320 in the functional region 120 where the cap layer 820 is located, the second drain metal layer 530 and the second source metal layer 510 are respectively formed on two sides of the cap layer 820, and the second Schottky metal layer 520 is formed on the cap layer 820, so as to form an enhancement mode low-voltage HEMT device (low-voltage e-mode HEMT) by the second drain metal layer 530, the second source metal layer 510, the second Schottky metal layer 520 and the barrier layer 320 and the drift layer 310 in the functional region. The first Schottky metal layer 610 and the cathode metal layer 620 are formed on the barrier layer 320 in the third functional region, wherein the first Schottky metal layer 610 and the second source metal layer 510 are respectively located on two sides of the second electron gas isolation structure 720, and the cathode metal layer 620 is located adjacent to the first Schottky metal layer 610. The insulating dielectric layer 830 is formed on the first gate metal layer 420, the first source metal layer 410, the first drain metal layer 430, the second source metal layer 510, the second drain metal layer 530, the cathode metal layer 620 and the barrier layer 320.

[0059] In the embodiment, as shown in FIG. 1, Figure 1As shown, by connecting the first source metal layer 410, the second drain metal layer 530, and the cathode metal layer 620 together through a first metal wire, and connecting the first gate metal layer 420, the second source metal layer 510, and the first Schottky metal layer 610 together through a second metal wire, the second Schottky metal layer 520 serves as the control terminal of the power device to receive the control signal, and the first drain metal layer 430 and the second source metal layer 510 serve as the two ends of the power device, thereby forming a cascode HEMT power device in which a low-voltage e-mode HEMT controls a high-voltage d-mode HEMT. This can effectively reduce parasitic capacitance and parasitic inductance, and greatly improve the switching frequency of the HEMT power device.

[0060] In a specific application embodiment, the first metal connection line and the second metal connection line can be formed in the insulating dielectric layer 830. Figure 1 The lines in the figure are only used to illustrate the connection relationship between the various metal layers. Similarly, the second Schottky metal layer 520 is connected to the control electrode outside the insulating dielectric layer 830 through a metal lead, and the first drain metal layer 430 and the second source metal layer 510 are respectively connected to the drain electrode and source electrode outside the insulating dielectric layer 830 through corresponding metal pins.

[0061] In specific applications, the cascode HEMT power device provided in the embodiments of the present application can be used in high-voltage control application scenarios. By integrating a Schottky diode structure, the reverse recovery speed of the device is improved and the reverse recovery loss is reduced. It can be applied to circuit topologies that require freewheeling scenarios.

[0062] In a specific application embodiment, a high-voltage d-mode HEMT, a low-voltage e-mode HEMT, and a Schottky diode structure can all be integrated on the same wafer.

[0063] See also Figure 2 As shown, the first source metal layer 410 is in an L-shaped structure.

[0064] In this embodiment, a vertical portion of the first source metal layer 410 contacts the barrier layer 320 , and a dielectric material is filled between a horizontal portion of the first source metal layer 410 and the first gate metal layer 420 .

[0065] In this embodiment, by providing the first source metal layer 410 with an L-shaped structure, a parasitic capacitor can be integrated between the source and gate of the high-voltage D-mode HEMT according to the requirements of the application scenario. The magnitude of the parasitic capacitor can be determined by the distance between the horizontal portion of the first source metal layer 410 and the first gate metal layer 420, as well as the dielectric constant of the dielectric material.

[0066] In one embodiment, the dielectric material filled between the horizontal portion of the first source metal layer 410 and the first gate metal layer 420 can be any one of silicon oxide, silicon nitride, silicon oxynitride.

[0067] In one embodiment, referring to Figure 1 As shown, the thickness of the first electron gas isolation structure 710 and the second electron gas isolation structure 720 is greater than or equal to the sum of the thickness of the barrier layer 320 and the drift layer 310.

[0068] In the present embodiment, the first electron gas isolation structure 710 and the second electron gas isolation structure 720 divide the barrier layer 320 and the drift layer 310 into three functional regions by being formed in the barrier layer 320 and the drift layer 310, wherein the bottom of the first electron gas isolation structure 710 and the second electron gas isolation structure 720 is in contact with the buffer layer 220, and the top of the first electron gas isolation structure 710 and the second electron gas isolation structure 720 can be flush with the upper surface of the barrier layer 320.

[0069] In one embodiment, if the thickness of the first electron gas isolation structure 710 and the second electron gas isolation structure 720 is greater than the sum of the thickness of the barrier layer 320 and the drift layer 310, the bottom of the first electron gas isolation structure 710 and the second electron gas isolation structure 720 extends into the buffer layer 220.

[0070] In one embodiment, referring to Figure 1 As shown, the thickness of the first drain metal layer 430 is greater than the thickness of the gate dielectric layer 810.

[0071] In the present embodiment, by setting the thickness of the first drain metal layer 430 to be greater than the thickness of the gate dielectric layer 810, the first gate metal layer 420 can be formed on the gate dielectric layer 810, so that the first gate metal layer 420 is opposite to the first drain metal layer 430.

[0072] In one embodiment, the thickness of the first drain metal layer 430 is the sum of the thickness of the gate dielectric layer 810 and the first gate metal layer 420.

[0073] In one embodiment, the distance between the first drain metal layer 430 and the first source metal layer 410 and the gate dielectric layer 810 is equal.

[0074] In one embodiment, the thickness of the second drain metal layer 530 and the thickness of the second source metal layer 510 are greater than the thickness of the cap layer 820.

[0075] In one embodiment, the gate dielectric layer 810 can be silicon oxide.

[0076] In one embodiment, the first source metal layer 410, the first drain metal layer 430, the first gate metal layer 420, the second drain metal layer 530, the second source metal layer 510, and the cathode metal layer 620 are ohmic metal materials.

[0077] In the present embodiment, ohmic contacts are formed between the first source metal layer 410, the first drain metal layer 430, and the barrier layer 320, between the second drain metal layer 530, the second source metal layer 510, and the barrier layer 320, and between the cathode metal layer 620 and the barrier layer 320.

[0078] In one embodiment, the first Schottky metal layer and the second Schottky metal layer comprise nickel and gold.

[0079] In one embodiment, the cap layer 820 is a P-type gallium nitride material.

[0080] In one embodiment, the barrier layer 320 is a gallium aluminum nitride material.

[0081] In one embodiment, the drift layer 310 is a gallium nitride material.

[0082] In one embodiment, the semiconductor substrate 210 can be a silicon-based wafer substrate.

[0083] The present application also provides a preparation method of a common-source common-gate type HEMT power device, as shown in Figure 3 The preparation method in the present embodiment includes steps S100 to S900.

[0084] In step S100, in combination with Figure 4 As shown, the buffer layer 220, the drift layer 310, and the barrier layer 320 are sequentially stacked on the semiconductor substrate 210.

[0085] In the present embodiment, the buffer layer 220, the drift layer 310, and the barrier layer 320 can be sequentially stacked on the semiconductor substrate 210.

[0086] The semiconductor substrate 210 can be a Si-based substrate, the drift layer 300 can be GaN, and the barrier layer 400 can be AlGaN.

[0087] In one specific application embodiment, the thickness of the Si-based substrate is 300-500 um.

[0088] In step S200, in combination with Figure 5 As shown, the cap layer 820 is formed on the barrier layer 320, and the first isolation trench 401 and the second isolation trench 402 are formed on both sides of the cap layer 820.

[0089] In this embodiment, combined with Figure 5 and Figure 6 As shown, a capping layer 820 can be formed on the barrier layer 400 through a P-type gallium nitride material growth process, and a portion of the capping layer 820 is etched away to retain the capping layer 820 in the central area of ​​the surface of the barrier layer 320. Then, a first isolation trench 401 and a second isolation trench 402 are formed on both sides of the capping layer 820 by etching the barrier layer 320 and the drift layer 310.

[0090] In a specific application embodiment, the first isolation trench 401 and the second isolation trench 402 penetrate into the buffer layer 200, thereby dividing the barrier layer 320 and the drift layer 310 into three non-contact parts, that is, the barrier layer 320 is divided into three non-contact barrier regions by the first isolation trench 401 and the second isolation trench 402, and the drift layer is divided into three non-contact drift regions by the first isolation trench 401 and the second isolation trench 402.

[0091] In a specific application embodiment, the cap layer 820 may be made of P-type GaN material.

[0092] In step S300, the first isolation trench 401 and the second isolation trench 402 are filled with an isolation material to form a first electron gas isolation structure 710 and a second electron gas isolation structure 720 in contact with the buffer layer 220. Figure 7 shown.

[0093] In this embodiment, combined with Figure 7 As shown, isolation material is filled in the first isolation trench 401 and the second isolation trench 402, and the isolation material above the barrier layer 320 is etched away, leaving only the isolation material of the isolation trench, thereby forming a first electron gas isolation structure 710 and a second electron gas isolation structure 720 in contact with the buffer layer 200 in the first isolation trench 401 and the second isolation trench 402, respectively.

[0094] In one embodiment, the isolation material may be silicon oxide or silicon nitride.

[0095] In step S 400 , a gate dielectric layer 810 is formed on the barrier layer 320 .

[0096] like Figure 8 As shown, the gate dielectric layer 810 is formed on the surface of the barrier layer 320 , and the gate dielectric layer 810 and the cap layer 820 are respectively located on both sides of the first electron gas isolation structure 710 .

[0097] In a specific application, a gate dielectric layer 810 can be formed on the surface of the barrier layer 320 by depositing a gate dielectric material, and then the formed gate dielectric layer 810 is etched to retain only a portion of the gate dielectric material on the surface of the barrier region adjacent to the barrier region where the cap layer 820 is located, so that the gate dielectric layer 810 is located on the other side of the first electron gas isolation structure 710.

[0098] In one embodiment, the gate dielectric layer 810 and the capping layer 820 are symmetrical with respect to the first electron gas isolation structure 710 .

[0099] In step S500, Figure 8 As shown, an ohmic metal layer 450 is formed on the gate dielectric layer 810, the cap layer 820 and the barrier layer 320, and a first etched trench 601 is formed on the ohmic metal layer 450, as shown in FIG. Figure 9 shown.

[0100] In this embodiment, combined with Figure 8 and Figure 9 As shown, the thickness of the ohmic metal layer 450 is greater than the thickness of the gate dielectric layer 810 and the cap layer 820 , and the first etched trench 601 and the cap layer 820 are respectively located on both sides of the second electron gas isolation structure 720 .

[0101] In a specific application embodiment, combined with Figure 9 As shown, a first etched groove 601 is formed in a designated area of ​​the ohmic metal layer 450 by etching the ohmic metal layer 450, the first etched groove 601 penetrates into the barrier layer 320, and the first etched groove 601 is located on the other side of the second electron gas isolation structure 720, so that it is opposite to the cap layer 820 based on the second electron gas isolation structure 720.

[0102] In step S600, Figure 10 and Figure 11 As shown, the ohmic metal material above the cap layer 820 is etched away to form a second etched trench 821, and the Schottky metal material is filled in the first etched trench 601 and the second etched trench 821 to form a first Schottky metal layer 610 in the first etched trench 601 and a second Schottky metal layer 520 in the second etched trench 821. Figure 12 In this embodiment, a mask may be used to cover portions other than the first etched trench 601 and the second etched trench 821, and then a Schottky metal layer may be formed in the exposed etched trench by depositing a Schottky metal material. The thickness of the first Schottky metal layer 610 is greater than that of the second Schottky metal layer 520, and a Schottky contact is formed between the first Schottky metal layer 610 and the barrier layer 320.

[0103] In step S700, Figure 12 and Figure 13 As shown, the ohmic metal layer 450 is patterned and etched to form a first gate metal layer 420 on the gate dielectric layer 810, a first source metal layer 410 and a first drain metal layer 430 are formed on both sides of the gate dielectric layer 810, a second source metal layer 510 and a second drain metal layer 530 are formed on both sides of the cap layer 820, and a cathode metal layer 620 is formed at a position adjacent to the first Schottky metal layer 610.

[0104] In this embodiment, an ohmic contact is formed between the first source metal layer 410 , the first drain metal layer 430 and the barrier layer 320 , an ohmic contact is formed between the second drain metal layer 530 , the second source metal layer 510 and the barrier layer 320 , and an ohmic contact is formed between the cathode metal layer 620 and the barrier layer 320 .

[0105] In step S800, Figure 14 As shown, a dielectric material is filled on the first gate metal layer 420 , the first source metal layer 410 , the first drain metal layer 430 , the second source metal layer 510 , the second drain metal layer 530 , the cathode metal layer 620 and the barrier layer 320 to form an insulating dielectric layer 830 .

[0106] In one embodiment, combined Figure 15 and Figure 16 As shown, the preparation method in this embodiment further includes: modifying the first source metal layer 410 so that the first source metal layer 410 has an L-shaped structure.

[0107] In this embodiment, by etching Figure 15 An insulating dielectric layer 830 is formed above the first source metal layer 410 in the insulating dielectric layer 830 to form an etched groove 411, and then an ohmic metal material is deposited, and the deposited ohmic metal material is etched and modified so that the first source metal layer 410 has an L-shaped structure, the vertical portion of the first source metal layer 410 is in contact with the barrier layer 320, and the horizontal portion of the first source metal layer 410 and the first gate metal layer 420 are filled with a dielectric material.

[0108] In this embodiment, by providing the first source metal layer 410 with an L-shaped structure, a parasitic capacitor can be integrated between the source and gate of the high-voltage D-mode HEMT according to the requirements of the application scenario. The magnitude of the parasitic capacitor can be determined by the distance between the horizontal portion of the first source metal layer 410 and the first gate metal layer 420, as well as the dielectric constant of the dielectric material.

[0109] In step S900, Figure 17As shown, a first metal lead is used to connect the first source metal layer 410, the second drain metal layer 530 and the cathode metal layer 620, and a second metal lead is used to connect the first gate metal layer 420, the second source metal layer 510 and the first Schottky metal layer 610.

[0110] In this embodiment, the first source metal layer 410, the second drain metal layer 530, and the cathode metal layer 620 are connected together via a first metal wire, and the first gate metal layer 420, the second source metal layer 510, and the first Schottky metal layer 610 are connected together via a second metal wire. In this case, the second Schottky metal layer 520 serves as the control terminal of the power device to receive the control signal, and the first drain metal layer 430 and the second source metal layer 510 serve as the two terminals of the power device. This forms a cascode HEMT power device in which a low-voltage e-mode HEMT controls a high-voltage d-mode HEMT. This effectively reduces parasitic capacitance and parasitic inductance, and significantly increases the switching frequency of the HEMT power device.

[0111] In a specific application embodiment, the first metal connection line and the second metal connection line can be formed in the insulating dielectric layer 830. Figure 1 The lines in the figure are only used to illustrate the connection relationship between the various metal layers. Similarly, the second Schottky metal layer 520 is connected to the control electrode outside the insulating dielectric layer 830 through a metal lead, and the first drain metal layer 430 and the second source metal layer 510 are respectively connected to the drain electrode and source electrode outside the insulating dielectric layer 830 through corresponding metal pins.

[0112] An embodiment of the present application further provides a chip, wherein the chip in this embodiment includes a cascode HEMT power device as described in any one of the above items.

[0113] In one embodiment, the chip in this embodiment includes a cascode HEMT power device prepared by the preparation method described in any of the above embodiments.

[0114] In a specific application embodiment, the chip in this embodiment may be a power chip, a driver chip, or an integrated chip obtained by combining multiple cascode HEMT power devices.

[0115] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0116] A buffer layer, a drift layer, and a barrier layer are stacked on a semiconductor substrate, and the barrier layer and the drift layer are isolated into multiple functional regions by a first electron gas isolation structure and a second electron gas isolation structure in contact with the buffer layer. A first source metal layer, a first drain metal layer, and a first gate metal layer are formed on the barrier layer in one of the functional regions, and a gate dielectric layer is provided between the first gate metal layer and the barrier layer, thereby forming a depletion mode high-voltage HEMT device. A second drain metal layer, a second source metal layer, and a second Schottky metal layer are formed in another functional region, and a cap layer is formed between the second Schottky metal layer and the barrier layer, thereby forming an enhancement mode low-voltage HEMT device. A cathode metal layer and a first Schottky metal layer are formed on the barrier layer in the energy region, thereby forming a Schottky diode structure. Finally, the first source metal layer, the second drain metal layer, and the cathode metal layer are connected together via a first metal lead, and the first gate metal layer, the second source metal layer, and the first Schottky metal layer are connected together via a second metal lead, thereby forming an integrated cascode HEMT power device. By controlling a depletion-mode high-voltage HEMT device with an enhanced-mode low-voltage HEMT device, parasitic capacitance and parasitic inductance can be effectively reduced, the switching frequency of the device can be increased, the reverse recovery speed can be improved, and the reverse recovery loss can be reduced, thereby greatly expanding the application scenarios of the HEMT power device.

[0117] Those skilled in the art will clearly understand that for the sake of convenience and brevity in description, only the division of the above-mentioned doping regions is used as an example. In actual applications, the above-mentioned functional areas can be allocated to different doping regions as needed, that is, the internal structure of the device can be divided into different doping regions to complete all or part of the functions described above.

[0118] The doping regions in the embodiment can be integrated into one functional region, or each doping region can exist physically separately, or two or more doping regions can be integrated into one functional region. The above-mentioned integrated functional regions can be implemented by using the same doping ion or by using multiple doping ions. In addition, the specific names of the doping regions are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application. The specific working process of the doping region in the preparation method of the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0119] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A cascode HEMT power device, characterized in that: The cascode HEMT power device comprises: A semiconductor substrate, a buffer layer, a drift layer, and a barrier layer stacked in sequence; a first electron gas isolation structure and a second electron gas isolation structure, formed in the barrier layer and the drift layer respectively, and contacting the buffer layer; A cap layer and a gate dielectric layer are formed on the barrier layer respectively; wherein the gate dielectric layer and the cap layer are respectively located on both sides of the first electron gas isolation structure; a first source metal layer, a first drain metal layer, and a first gate metal layer, wherein the first source metal layer and the first drain metal layer are respectively formed on both sides of the gate dielectric layer, and the first gate metal layer is formed on the gate dielectric layer; A second drain metal layer and a second source metal layer are formed on both sides of the cap layer respectively; A first Schottky metal layer is formed on the barrier layer; wherein the first Schottky metal layer and the second source metal layer are respectively located on both sides of the second electron gas isolation structure; a cathode metal layer formed on the barrier layer and located adjacent to the first Schottky metal layer; a second Schottky metal layer formed on the cap layer; an insulating dielectric layer formed on the first gate metal layer, the first source metal layer, the first drain metal layer, the second source metal layer, the second drain metal layer, the cathode metal layer, and the barrier layer; The first source metal layer, the second drain metal layer and the cathode metal layer are connected together through a first metal lead, and the first gate metal layer, the second source metal layer and the first Schottky metal layer are connected together through a second metal lead.

2. The cascode HEMT power device according to claim 1, wherein: The first source metal layer has an L-shaped structure; wherein the vertical portion of the first source metal layer contacts the barrier layer, and a dielectric material is filled between the horizontal portion of the first source metal layer and the first gate metal layer.

3. The cascode HEMT power device according to claim 1, wherein: The thickness of the first electron gas isolation structure and the second electron gas isolation structure is greater than or equal to the sum of the thickness of the barrier layer and the drift layer.

4. The cascode HEMT power device according to claim 1, wherein: The thickness of the first drain metal layer is greater than the thickness of the gate dielectric layer.

5. The cascode HEMT power device according to any one of claims 1 to 4, characterized in that: The thickness of the second drain metal layer and the thickness of the second source metal layer are greater than the thickness of the capping layer.

6. The cascode HEMT power device according to any one of claims 1 to 4, characterized in that: The first Schottky metal layer includes nickel and gold.

7. The cascode HEMT power device according to any one of claims 1 to 4, characterized in that: The capping layer is made of P-type gallium nitride material; and / or The barrier layer is made of gallium aluminum nitride material; and / or The drift layer is made of gallium nitride material.

8. A method for preparing a cascode HEMT power device, characterized in that: The preparation method comprises: A buffer layer, a drift layer and a barrier layer are sequentially stacked on a semiconductor substrate; forming a cap layer on the barrier layer, and forming a first isolation trench and a second isolation trench on both sides of the cap layer; wherein the first isolation trench and the second isolation trench extend deep into the buffer layer; Filling the first isolation trench and the second isolation trench with an isolation material to form a first electron gas isolation structure and a second electron gas isolation structure in contact with the buffer layer; forming a gate dielectric layer on the barrier layer; wherein the gate dielectric layer and the cap layer are respectively located on both sides of the first electron gas isolation structure; forming an ohmic metal layer on the gate dielectric layer, the cap layer, and the barrier layer, and forming a first etched trench on the ohmic metal layer; wherein the first etched trench and the cap layer are respectively located on both sides of the second electron gas isolation structure; Etching away the ohmic metal material above the capping layer to form a second etched trench, and filling the first etched trench and the second etched trench with a Schottky metal material to form a first Schottky metal layer in the first etched trench and a second Schottky metal layer in the second etched trench; Performing patterned etching on the ohmic metal layer to form a first gate metal layer on the gate dielectric layer, forming a first source metal layer and a first drain metal layer on both sides of the gate dielectric layer, respectively, forming a second source metal layer and a second drain metal layer on both sides of the cap layer, and forming a cathode metal layer at a position adjacent to the first Schottky metal layer; Filling a dielectric material on the first gate metal layer, the first source metal layer, the first drain metal layer, the second source metal layer, the second drain metal layer, the cathode metal layer and the barrier layer to form an insulating dielectric layer; The first source metal layer, the second drain metal layer and the cathode metal layer are connected together using a first metal lead, and the first gate metal layer, the second source metal layer and the first Schottky metal layer are connected together using a second metal lead.

9. The preparation method according to claim 8, characterized in that The preparation method further comprises: The first source metal layer is modified so that the first source metal layer has an L-shaped structure; wherein the vertical portion of the first source metal layer contacts the barrier layer, and a dielectric material is filled between the horizontal portion of the first source metal layer and the first gate metal layer.

10. A chip, characterized in that: The method comprises the cascode HEMT power device according to any one of claims 1 to 7; or the cascode HEMT power device prepared by the preparation method according to claim 8 or 9.

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