A high-density capacitor suitable for on-chip power supply filtering and its implementation method

Abstract

The present invention discloses a high-density capacitor suitable for on-chip power supply filtering and an implementation method thereof. The high-density on-chip capacitor involved in the present invention includes two parts: an active MOS capacitor and a passive MOM capacitor. Among them, the active MOS capacitor is implemented by a large-size MOS transistor, the gate of the MOS transistor is connected to a power supply metal plane, the source and drain of the MOS transistor are connected to a ground plane in parallel, and when a forward voltage is applied to the power supply metal plane, a significant large capacitance effect is formed between the gate of the MOS tube and its source and drain. The MOM capacitor is implemented by a cross-finger capacitor array of multi-layer metal vertical stacking. In terms of electrical connection, the active MOS capacitor and the passive MOM capacitor are connected in parallel to work together, and a very high capacitance density is achieved in a compact size, and the structure is compact, the occupied area is small, the manufacturing cost is low, it is compatible with a variety of semiconductor processes, and it is easy to integrate on a large scale.

Description

Technical Field

[0001] The invention belongs to the technical field of basic electrical components, and relates to a high-density capacitor suitable for on-chip power supply filtering and a realization method thereof, and is suitable for on-chip power supply filtering of an integrated circuit chip. Background Art

[0002] In integrated circuit systems, it is extremely important to suppress noise and interference. Among them, the noise from the power supply is an important source of interference in electronic systems, and the ripple on the power supply is the main source of noise. The introduction of these noises will cause the electronic system to generate phase noise or spurious signals in the frequency domain, which will appear as clock jitter in the time domain, thereby significantly deteriorating the performance of the circuit system. Therefore, effectively suppressing the noise interference of the power supply is an important technical means to improve the anti-interference performance of the circuit.

[0003] In order to suppress the noise interference from the external power supply, a large number of on-chip capacitors are usually used inside the integrated circuit for power filtering to obtain a pure power supply voltage. At present, there are mainly two types of on-chip capacitors commonly used, namely parallel plate (Metal-Insulator-Metal, MIM) capacitors and interdigital (Metal-Oxide-Metal, MOM) capacitors. Among them, MIM capacitors mainly use top metal and sub-top metal, and the medium between them to form capacitors, which have the advantages of small parasitics and high precision. And MOM capacitors are generally realized by forming a coplanar array with a cross-interlocked interdigital structure. With the advancement of process technology, metal wires can be closer, and more metal layers can be used to stack and use to achieve higher capacitance density, so MOM capacitors have the advantages of low parasitic effects, symmetrical planar structure, excellent RF characteristics, etc. However, the common disadvantages of their existence are low capacitance density, large size, and high cost. It can be seen that the traditional on-chip capacitor design method is difficult to obtain high capacitance density and small size at the same time, and it is difficult to meet the design requirements of integrated circuit chips for high-density and small-size power filter capacitors. Summary of the invention

[0004] The objective of the invention is to provide a kind of high-density capacitor applicable to on-chip power supply filtering that a kind of active MOS (Metal Oxide Semiconductor) capacitor and passive MOM capacitor merge, the structure greatly improves capacitance density under compact small size, and at the same time also solves DRC (Design Rule Check) density problem required by integrated circuit layout processing. The proposed structure is simple and compact, the principle is clear, the size is small, it is easy to process, and the manufacturing cost is low, and it has excellent scientific application value in integrated circuit design.

[0005] The present invention adopts the following technical solutions to achieve the above-mentioned invention objectives:

[0006] A high-density capacitor suitable for on-chip power supply filtering comprises an active MOS capacitor (10) and a passive MOM capacitor; the active MOS capacitor (10) is located below a power supply metal plane, the passive MOM capacitor is located above the power supply metal plane, the gate of the active MOS capacitor (10) and one end of the passive MOM capacitor are connected to the power supply metal plane, the source and drain of the active MOS capacitor (10) are shorted to a ground plane, and the other end of the passive MOM capacitor is shorted to the ground plane through a first metal through hole (6). The active MOS capacitor (10) and the passive MOM capacitor are connected in parallel to form a high-density on-chip capacitor standard unit.

[0007] Preferably, the passive MOM capacitor is a two-port reciprocal device, comprising a fifth metal layer (5), a fourth metal layer (4), a third metal layer (3), a fourth metal through hole (9) and a third metal through hole (8), wherein an oxide dielectric layer is present between the fifth metal layer (5), the fourth metal layer (4) and the third metal layer (3); the fourth metal through hole (9) and the third metal through hole (8) penetrate the oxide dielectric layer. The two ends of the fifth metal layer (5) and the fourth metal layer (4) are stacked and connected together through the fourth metal through hole (9), and the two ends of the fourth metal layer (4) and the third metal layer (3) are stacked and connected together through the third metal through hole (8), and the three metal layers are stacked and connected vertically in sequence.

[0008] More preferably, the fifth metal layer (5), the fourth metal layer (4) and the third metal layer (3) are etched into a cross-finger pattern; the capacitance value C of the passive MOM capacitor is 1 It is directly related to the effective length a of the fork, the width b of the fork, the thickness t of the fork, the spacing d between the forks, and the number n of the forks, and is estimated according to the following formula:

[0009]

[0010] Where ε represents the dielectric constant of the manufacturing process.

[0011] The first metal layer (1) is equivalent to a ground plane; the second metal layer (2) is equivalent to a power supply metal plane; wherein the first metal layer (1), the second metal layer (2), the third metal layer (3), the fourth metal layer (4), and the fifth metal layer (5) are stacked vertically in sequence from bottom to top;

[0012] More preferably, the first metal layer (1) is composed of 4 identical units A distributed in a 2*2 matrix array, each unit A is etched with a rectangular notch in the center, and the ratio of the area of ​​the rectangular notch to the area of ​​the unit A is less than or equal to 75%; the second metal layer (2) is composed of 4 identical units B distributed in a 2*2 matrix array, and the units B correspond to the units A in the upper and lower parts; each unit B is in the shape of a cross, and is composed of a central square metal, a first rectangular metal, a second rectangular metal, a third rectangular metal, and a fourth rectangular metal, the central square metal has the same size as the rectangular notch of the unit A, the first rectangular metal, the second rectangular metal, the third rectangular metal, and the fourth rectangular metal are respectively located on the four sides of the central square metal, and the lengths of the first rectangular metal, the second rectangular metal, the third rectangular metal, and the fourth rectangular metal are the same as the lengths of the sides of the central square metal to which they are connected;

[0013] Preferably, the active MOS capacitor (10) adopts a large-size MOS transistor, the gate (G) of the active MOS capacitor (10) is vertically connected to the second metal layer (2), and the source (S) and drain (D) of the active MOS capacitor (10) are vertically connected to the first metal layer (1); the first metal layer (1) and the third metal layer (3) at one end of the passive MOM capacitor are vertically connected through a first metal through hole (6); the second metal layer (2) and the third metal layer (3) at the other end of the passive MOM capacitor are vertically connected through a second metal through hole (7), and there is no electrical connection between the second metal layer (2) and the first metal layer (1); when a forward voltage is applied to the gate of the active MOS capacitor (10), a conductive channel is formed between the source and drain of the active MOS capacitor (10), and a strong capacitance effect exists, so that a high-density MOS capacitor is formed, and the capacitance value C of the active MOS capacitor (10) is 1. 2 It is directly related to its gate length L and gate width W, and can be estimated according to the following formula:

[0014]

[0015] In the formula, C ox and C ov They are the gate oxide capacitance per unit area and the overlap capacitance per unit width. These two parameter values ​​are directly related to the manufacturing process parameters and can generally be obtained by referring to the technical manual of the process manufacturer.

[0016] The second object of the present invention is to provide a method for implementing a high-density capacitor suitable for on-chip power supply filtering, specifically:

[0017] When a forward voltage (described forward voltage is greater than threshold voltage) is applied to the grid of active MOS capacitor (10), a conductive channel can be formed between the source and drain of active MOS capacitor (10), and the gate oxide dielectric layer between the grid of active MOS capacitor (10) and the conductive channel can be equivalent to an insulating medium, and the grid acts as an upper plate, and the upper plate is usually connected to the power supply metal plane, and the source and drain are short-circuited together as a lower plate, and the lower plate is usually connected to the ground plane. And passive MOM capacitors are realized by forming a coplanar interdigitated finger structure through a cross-interlocked interdigitated finger capacitor array. Within a certain operating frequency range, the electrical connection mode of active MOS capacitor (10) and passive MOM capacitor is to connect in parallel to act together, thereby obtaining a larger capacitance density.

[0018] Preferably, the capacitance value of the active MOS capacitor (10) is directly proportional to the gate length and gate width of the active MOS capacitor (10) and the voltage applied to the gate. By changing the gate width and gate length of the active MOS capacitor (10), the positive voltage applied to the gate is changed, and the capacitance value of the MOS capacitor is controlled. All of these enable the implementation of the MOS capacitor to obtain additional design freedom.

[0019] Preferably, the size of the interdigital metal wires and the number of interdigital fingers of the passive MOM capacitor are directly related to the capacitance value. Depending on the manufacturing process, the capacitance value can be changed by changing the size and number of metal wire spacing. Depending on the needs, multiple metal layers can be stacked to form a multi-layer interdigital structure, further improving the capacitance density and obtaining additional design freedom.

[0020] The present invention adopts the above technical solution and has the following beneficial effects:

[0021] (1) The present invention realizes a high-density on-chip capacitor by combining an active MOS capacitor and a passive MOM capacitor, which has a compact structure, a small footprint, simple manufacturing, compatibility with a variety of semiconductor processes, and is easy to integrate on a large scale. A larger capacitance value can be obtained in a very compact size, and the capacitance density is extremely high compared to traditional on-chip capacitors.

[0022] (2) The high-density on-chip capacitor realized by the present invention through MOS capacitors and MOM capacitors is a three-dimensional structure, which uses the active layer, polysilicon layer, and metal layer involved in the integrated circuit manufacturing process. The overall structure is very compact and well solves the problem of insufficient DRC density required for integrated circuit layout processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the high-density on-chip capacitor of the present invention.

[0024] FIG2(a) is a three-dimensional stereogram of the metal layer structure of the high-density on-chip capacitor of the present invention, FIG2(b) is a three-dimensional stereogram obtained by rotating FIG2(a) 90° clockwise, FIG2(c) is a three-dimensional top view of the metal layer structure of the high-density on-chip capacitor of the present invention, and FIG2(d) is a three-dimensional rear view of the metal layer structure of the high-density on-chip capacitor of the present invention;

[0025] Figure 3 (a)-(c) are schematic diagrams of the etching patterns of the first metal layer, the second metal layer, and the third to fifth metal layers involved in the high-density on-chip capacitor of the present invention, respectively. Figure (d) is a schematic diagram of the size after enlarging Figure (c).

[0026] Figure 4 It is the capacitance simulation result of the high-density on-chip capacitor in the embodiment of the present invention.

[0027] Markings in the figure: first metal layer 1, second metal layer 2, third metal layer 3, fourth metal layer 4, fifth metal layer 5, first metal through hole 6, second metal through hole 7, third metal through hole 8, fourth metal through hole 9, active MOS capacitor 10. DETAILED DESCRIPTION

[0028] The technical solution of the invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the described embodiments are only used to explain the invention but not to limit the invention. After reading the application documents of the present invention, various equivalent modifications made to the present invention by those skilled in the art all fall within the scope defined by the claims of the present application.

[0029] In the description of the present invention, it should be noted that, unless otherwise specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection, or it can be the internal communication of two elements, it can be directly connected, or it can be indirectly connected through an intermediate medium. For ordinary technicians in the relevant fields, the specific meanings of the above terms can be understood according to specific circumstances. In addition, the present invention provides examples of various specific processes and materials, but ordinary technicians in this field can be aware of the applicability of other processes and / or the use of other materials.

[0030] Example 1

[0031] The high-density on-chip capacitor involved in this embodiment is illustrated by using a silicon-based semiconductor 55nm CMOS process as an example of the process material to be implemented. Figure 1As shown, comprise active MOS capacitor 10 and passive MOM capacitor; Active MOS capacitor 10 is positioned at the below of power supply metal plane, passive MOM capacitor is positioned at the top of power supply metal plane, the gate of active MOS capacitor 10 and one end of passive MOM capacitor are connected to power supply metal plane together, the source and drain of active MOS capacitor 10 are shorted to ground plane, and the other end of passive MOM capacitor is shorted to ground plane by first metal via 6.Within certain operating frequency range, the electrical connection mode of active MOS capacitor 10 and passive MOM capacitor is to connect and act together in parallel mode, thereby can obtain bigger capacitance density.

[0032] Figure 2 (a), Figure 2 (b), Figure 2 (c), Figure 2 (d) give a three-dimensional view of the metal structure of the high-density on-chip capacitor involved; the first metal layer 1, the second metal layer 2, the third metal layer 3, the fourth metal layer 4, and the fifth metal layer 5 are stacked vertically from bottom to top in sequence; the first metal layer 1 is equivalent to the ground plane; the second metal layer 2 is equivalent to the power supply metal plane; the fifth metal layer 5, the fourth metal layer 4, the third metal layer 3, the fourth metal through hole 9 and the third metal through hole 8 together constitute a passive MOM capacitor, and the passive MOM capacitor is a two-port reciprocal device, wherein the fifth metal layer 5, the fourth metal layer 4, and the third metal layer 3 have an oxide dielectric layer; the fourth metal through hole 9 and the third metal through hole 8 run through the oxide dielectric layer. The two ends of the fifth metal layer 5 and the fourth metal layer 4 are stacked and connected together through the fourth metal through hole 9, and the two ends of the fourth metal layer 4 and the third metal layer 3 are stacked and connected together through the third metal through hole 8, and the three metal layers are stacked and connected vertically in sequence.

[0033] The fifth metal layer 5, the fourth metal layer 4 and the third metal layer 3 are etched into Figure 3 (c) The cross-finger pattern shown; the capacitive effect of the passive MOM capacitor is achieved by utilizing the fringe electromagnetic field effect between the interpolation fingers. The length and width of the interpolation, the number of interpolation fingers, and the spacing between the interpolation fingers can be customized according to the capacitance value required by the actual design. In the present embodiment, the length and width of the interpolation are 9 μm and 0.1 μm, respectively, the spacing between the interpolation fingers is 0.1 μm, and the number of interpolation fingers is 50.

[0034] The active MOS capacitor 10 adopts a large-size MOS transistor, the gate (G) of the active MOS capacitor 10 is vertically connected to the second metal layer 2, and the source (S) and drain (D) of the active MOS capacitor 10 are vertically connected to the first metal layer 1; the first metal layer 1 and the third metal layer 3 at one end of the passive MOM capacitor are vertically connected through the first metal through hole 6; the second metal layer 2 and the third metal layer 3 at the other end of the passive MOM capacitor are vertically connected through the second metal through hole 7, and there is no electrical connection between the second metal layer 2 and the first metal layer 1;

[0035] The first metal layer 1 is equivalent to Figure 1 The ground plane and the power plane metal layer 2 are etched into Figure 3 The patterns of (a)-(b) can be etched into other regular shapes according to the processing density requirements of the process. The sizes of the first metal layer 1 and the second metal layer 2 are standard units of 10μm×10μm respectively. According to the actual design requirements, they can also be designed into other sizes. The MOS capacitor involved in the present invention is realized by a large-size MOS transistor with a gate length of 8μm and a gate width of 6μm. The gate (G) of the active MOS capacitor 10 is vertically connected to the power supply plane. The source (S) and drain (D) of the active MOS capacitor 10 are vertically connected to the first metal layer 1 of the equivalent ground plane. When a positive voltage is applied to the gate of the active MOS capacitor 10, a conductive channel will be formed between the source and drain of the active MOS capacitor 10. At this time, a high-density MOS capacitor will be formed. The width-to-length ratio of the active MOS capacitor 10 is directly related to the capacitance value, and can also be designed into other parameters according to the actual design requirements.

[0036] Due to the three-dimensional structure that combines active MOS capacitors and passive MOM capacitors, a high-density capacitance value of 7.67fF / μm is achieved in a compact size. 2 .like Figure 4 As shown, the high-density on-chip capacitor of the present invention can achieve a capacitance value of 767fF to 723fF in an ultra-wideband operating frequency range of 0.1 to 20GHz when the operating voltage is 1.2V. Figure 4 It can be found that, under the same size, compared with MOS capacitors and MOM capacitors, the capacitance of the three-dimensional high-density capacitor designed by the present invention is greatly improved.

[0037] Although the specific embodiments of the present invention are described above in conjunction with the accompanying drawings, it should be understood by those skilled in the art that these are only examples, and that various variations or modifications may be made to these embodiments without departing from the principles and essence of the present invention. The scope of the present invention is limited only by the appended claims.

Claims

1. A high-density capacitor suitable for on-chip power supply filtering, characterized in that The invention is composed of an active MOS capacitor (10) and a passive MOM capacitor; the active MOS capacitor (10) is located below a power supply metal plane, the passive MOM capacitor is located above the power supply metal plane, the gate of the active MOS capacitor (10) and one end of the passive MOM capacitor are commonly connected to the power supply metal plane, the source and drain of the active MOS capacitor (10) are short-connected to a ground plane, and the other end of the passive MOM capacitor is short-connected to the ground plane via a first metal through hole (6); the active MOS capacitor (10) and the passive MOM capacitor are connected in parallel; The passive MOM capacitor is a two-port reciprocal device, which is composed of a fifth metal layer (5), a fourth metal layer (4), a third metal layer (3), a fourth metal through hole (9) and a third metal through hole (8), wherein an oxide dielectric layer exists between the fifth metal layer (5), the fourth metal layer (4) and the third metal layer (3); the fourth metal through hole (9) and the third metal through hole (8) penetrate the oxide dielectric layer; the two ends of the fifth metal layer (5) and the fourth metal layer (4) are stacked and connected together through the fourth metal through hole (9), and the two ends of the fourth metal layer (4) and the third metal layer (3) are stacked and connected together through the third metal through hole (8), and the three metal layers are stacked and connected in sequence vertically; The fifth metal layer (5), the fourth metal layer (4) and the third metal layer (3) are etched into a cross-finger pattern; the capacitance value C1 of the passive MOM capacitor is regulated according to the following formula: Where ε represents the dielectric constant of the manufacturing process, a represents the effective length of the interdigital finger, b represents the width of the interdigital finger, t represents the thickness of the interdigital finger, d represents the spacing between the interdigital fingers, and n represents the number of interdigital fingers; When a positive voltage is applied to the gate of the active MOS capacitor (10), a conductive channel is formed between the source and drain of the active MOS capacitor (10), and a strong capacitance effect exists. At this time, a high-density MOS capacitor is formed. The capacitance value C2 of the active MOS capacitor (10) is adjusted according to the following formula: In the formula, C ox and C ov They are the gate oxide capacitance per unit area and the overlap capacitance per unit width, L represents the gate length, and W represents the gate width.

2. A high-density capacitor suitable for on-chip power supply filtering according to claim 1, characterized in that The first metal layer (1) is equivalent to a ground plane; the second metal layer (2) is equivalent to a power supply metal plane; wherein the first metal layer (1), the second metal layer (2), the third metal layer (3), the fourth metal layer (4), and the fifth metal layer (5) are stacked vertically from bottom to top in sequence.

3. A high-density capacitor suitable for on-chip power supply filtering according to claim 2, characterized in that The first metal layer (1) is composed of four identical units A distributed in a 2*2 matrix array, and a rectangular notch is etched at the center of each unit A.

4. A high-density capacitor suitable for on-chip power supply filtering according to claim 3, characterized in that The ratio of the area of ​​the rectangular notch of the first metal layer (1) to the area of ​​the unit A is less than or equal to 75%.

5. A high-density capacitor suitable for on-chip power supply filtering according to claim 3, characterized in that The second metal layer (2) is composed of 4 identical units B distributed in a 2*2 matrix array, and the units B correspond to the units A in upper and lower directions; each unit B is in a cross shape, and is composed of a central square metal, a first rectangular metal, a second rectangular metal, a third rectangular metal, and a fourth rectangular metal; the central square metal has the same rectangular notch size as that of the unit A; the first rectangular metal, the second rectangular metal, the third rectangular metal, and the fourth rectangular metal are respectively located on the four sides of the central square metal; and the lengths of the first rectangular metal, the second rectangular metal, the third rectangular metal, and the fourth rectangular metal are the same as the lengths of the sides of the central square metal to which they are connected.

6. A high-density capacitor suitable for on-chip power supply filtering according to claim 2, characterized in that The active MOS capacitor (10) adopts a large-size MOS transistor, the gate (G) of the active MOS capacitor (10) is vertically connected to the second metal layer (2), and the source (S) and drain (D) of the active MOS capacitor (10) are vertically connected to the first metal layer (1); the first metal layer (1) and the third metal layer (3) at one end of the passive MOM capacitor are vertically connected through a first metal through hole (6); the second metal layer (2) and the third metal layer (3) at the other end of the passive MOM capacitor are vertically connected through a second metal through hole (7), and there is no electrical connection between the second metal layer (2) and the first metal layer (1).

7. A method for realizing a high-density capacitor suitable for on-chip power supply filtering as claimed in any one of claims 1 to 6, characterized in that Specifically: When a forward voltage is applied to the gate of the active MOS capacitor (10), a conductive channel is formed between the source and drain of the active MOS capacitor (10). At this time, the gate oxide dielectric layer between the gate of the active MOS capacitor (10) and the conductive channel can be equivalent to an insulating medium. At this time, the gate acts as an upper plate, which is usually connected to a power supply metal plane. The source and drain are short-circuited together to act as a lower plate, which is usually connected to a ground plane. The passive MOM capacitor is realized by forming a coplanar interdigitated finger capacitor array through a cross-interlocked interdigitated finger structure. Within a certain operating frequency range, the active MOS capacitor (10) and the passive MOM capacitor are electrically connected in parallel to work together, thereby obtaining a greater capacitance density.

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