An over-temperature protection circuit for a GaN device with an embedded temperature monitoring unit

Abstract

The present invention belongs to the field of GaN power electronic technology, and specifically relates to an over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit. The present invention is based on an over-temperature protection design of a GaN power device with an internally embedded distributed temperature monitoring unit, so it is structurally different from other circuits, and there is no need to design a junction temperature monitoring branch specifically around the GaN power device, which is simpler in design structure. Secondly, since the internal temperature monitoring unit is directly integrated near the hot spot of the heat source of the GaN device (the gate drain side of the drift region), the temperature monitoring unit directly reflects the temperature information of the hot spot. Compared with designing a temperature monitoring and protection circuit outside the GaN device, the temperature monitoring accuracy of the designed circuit is higher. At the same time, the monolithic integrated circuit can reduce the parasitic effects caused by the interconnection in the circuit and give full play to the high-frequency and high-speed performance of the GaN device.

Description

Technical Field

[0001] The invention belongs to the technical field of GaN power electronics, and in particular relates to an over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit. Background Art

[0002] With the advancement of science and technology and the development of the times, high efficiency, high power density, high reliability, low cost and lightweight miniaturization have become the main development trends of power integrated circuits. With the increasing development of semiconductor technology, the performance of silicon-based power devices has gradually approached the material limitation boundary. Wide Band-Gap (WBG) semiconductor materials such as Silicon Carbide (SiC) and Gallium Nitride (GaN) are the third-generation semiconductor materials that have emerged in the past two decades. Compared with traditional semiconductor materials Si, the third-generation semiconductor materials have larger bandgap width, higher breakdown field strength, higher electron saturation speed and other advantages. Power electronic devices made of third-generation semiconductor materials have received widespread attention in the field of power electronics. After years of development, GaN power devices are becoming more and more widely used, from automotive Lidar systems to chargers for consumer electronics.

[0003] As the size of devices becomes smaller and smaller and the integration becomes higher and higher, when the devices operate at higher voltages and higher frequencies to obtain higher power density, this will inevitably lead to greater power dissipation, causing heat to accumulate rapidly inside the device, resulting in a significant increase in the temperature inside the device. The high temperature and high field generated inside the device will cause serious reliability problems for GaN devices, such as dynamic on-resistance degradation, threshold voltage drift, current collapse, etc., and accelerate device failure. In worse cases, the entire device may even be burned out. Summary of the invention

[0004] The present invention proposes an over-temperature protection circuit for a GaN device with an embedded temperature monitoring unit, which is used to accurately detect the temperature inside the device and the heat distribution at different locations, reducing the complexity of circuit design and the difficulty of implementation. Through the design of a fully enhanced GaN gate circuit, the circuit adopts a fully GaN monolithic integrated comparator and inverter circuit, and outputs V OTP The signal is fed back to the previous driving circuit, and the temperature threshold of the trigger protection circuit is adjusted by controlling Vref. Introducing the silicon-based GaN over-temperature protection circuit proposed in the present invention into the GaN power driving system can make the GaN power device work intelligently under high voltage and high temperature without serious reliability problems.

[0005] The technical solution of the present invention is:

[0006] An over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit, characterized in that it includes a GaN power device (such as a GaN power device embedded with a temperature monitoring unit) Figure 2 ), a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor, a comparator, a first inverter INV1, a second inverter INV2, a third inverter INV3 and an AND gate circuit;

[0007] One end of the first resistor R1 is connected to the working voltage, the other end of the first resistor R1 is connected to a metal electrode of a temperature monitoring unit embedded in the GaN power device and the positive input end of the comparator circuit, and the other metal electrode of the temperature monitoring unit is grounded;

[0008] One end of the second resistor R2 is connected to the high level VDD, the other end of the second resistor R2 is simultaneously connected to one end of the third resistor R3 and the inverting input end of the comparator, the other end of the third resistor R3 is simultaneously connected to one end of the fourth resistor R4 and the drain of the first transistor, and the other end of the fourth resistor R4 and the source of the first transistor are grounded;

[0009] The output end of the comparator is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is the output end of the over-temperature protection circuit; the input end of the third inverter INV3 and the gate of the first transistor E1 are connected to the output end of the over-temperature protection circuit; the output end of the third inverter INV3 is connected to one of the input ends of the AND gate circuit, the other input end of the AND gate circuit is connected to the external driving signal, the output end of the AND gate circuit is connected to the gate of the GaN power device, the drain of the GaN power device is connected to the external circuit, and the source of the GaN power device is grounded.

[0010] Further, the comparator includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a second transistor, a third transistor, a fourth transistor and a fifth transistor; the first inverter INV1 includes an eighth resistor R8 and a sixth transistor; the second inverter INV2 includes a ninth resistor R9 and a seventh transistor;

[0011] One end of the fifth resistor R5, one end of the sixth resistor R6, one end of the seventh resistor R7, one end of the eighth resistor R8, and one end of the ninth resistor R9 are all connected to the high level VDD, and the other end of the fifth resistor R5 is simultaneously connected to the gate and drain of the second transistor and the gate of the third transistor; the other end of the sixth resistor R6 is connected to the drain of the fourth transistor, and the source of the fourth transistor is simultaneously connected to the drain of the third transistor and the source of the fifth transistor; the other end of the seventh resistor R7 is simultaneously connected to the drain of the fifth transistor and the gate of the sixth transistor; the other end of the eighth resistor R8 is simultaneously connected to the drain of the sixth transistor and the gate of the seventh transistor; the other end of the ninth resistor R9 is connected to the drain of the seventh transistor and is also the output end of the over-temperature protection circuit; the source of the second transistor, the source of the third transistor, the source of the sixth transistor, and the source of the seventh transistor are all grounded; the gate of the fourth transistor is the positive input end of the comparator, and the gate of the fifth transistor is the reverse input end of the comparator.

[0012] Furthermore, the third inverter INV3 includes a tenth resistor R10 and an eighth transistor; one end of the tenth resistor R10 is connected to the high level VDD, and the other end of the tenth resistor R10 is connected to the drain of the eighth transistor, and the connection point is the output end of the third inverter INV3; the gate of the eighth transistor is the input end of the third inverter INV3, and the source of the eighth transistor is grounded.

[0013] Furthermore, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all enhancement-mode GaN transistors.

[0014] Further, such as Figure 3As shown, the cell structure of the GaN power device includes a substrate 01, a buffer layer 02 located on the upper surface of the substrate 01, a GaN channel layer 03 located on the upper surface of the buffer layer 02, an AlGaN barrier layer 04 located on the upper surface of the GaN channel layer 03, a source ohmic metal 08 and a drain ohmic metal 09; the GaN channel layer 03 and the AlGaN barrier layer 04 form a heterojunction; a passivation layer 07 is covered on the upper surface of the AlGaN barrier layer 04; the AlGaN barrier layer 04 and the passivation layer 07 are located between the source ohmic metal 08 and the drain ohmic metal 09. The source ohmic metal 08 and the drain ohmic metal 09 are respectively located at the two ends of the upper surface of the GaN channel layer 03; a source field plate 10 is provided on the upper surface of the source ohmic metal 08, and the portion of the source field plate 10 located above the source field plate 10 is defined as a first vertical field plate; the top of the first vertical field plate extends along the lateral direction of the device toward the side close to the drain ohmic metal 09 to the middle of the device, and the extension portion is defined as a first lateral field plate; the end of the first lateral field plate extends along the vertical direction of the device toward the side close to the passivation layer 07, and the extension portion is defined as a second vertical field plate. The first lateral field plate, the second vertical field plate and the second lateral field plate form a zigzag structure; a P-GaN cap layer 05 is provided below the first lateral field plate, and the P-GaN cap layer 05 penetrates the passivation layer 07 in the vertical direction and directly contacts the AlGaN barrier layer 04; a gate metal 06 is provided on the upper surface of the P-GaN cap layer 05; a passivation layer between the P-GaN cap layer 05 and the drain ohmic metal 09 07 has a temperature monitoring unit 11 on its upper surface, and the second lateral field plate is located above the passivation layer 07 between the P-GaN cap layer 05 and the temperature monitoring unit 11; an isolation layer 12 is filled between the P-GaN cap layer 05 and the gate metal 06 and the first vertical field plate, the first lateral field plate, the second vertical field plate and the second lateral field plate, the isolation layer 12 also covers the drain ohmic metal 09, the temperature monitoring unit 11 and the upper surface of the passivation layer 07, and the height of the isolation layer 12 is flush with the first lateral field plate to completely wrap the second vertical field plate and the second lateral field plate.

[0015] Furthermore, the material of the temperature monitoring unit 11 is any one of Ni / Au, Ti / Au, Pd / Au and Ni / Au / Ni.

[0016] Furthermore, the lateral length of the temperature monitoring unit 11 is 1-5 um.

[0017] Furthermore, the thickness of the P-GaN cap layer 05 is 50-80 nm.

[0018] Furthermore, the doping concentration of the P-GaN cap layer 05 is 1×10 17 cm-3 ~5x10 20 cm -3 .

[0019] The beneficial effects of the present invention are:

[0020] First, since the circuit is designed for over-temperature protection based on GaN power devices with internally embedded distributed temperature monitoring units, it is structurally different from other circuits. There is no need to design a junction temperature monitoring branch specifically around the GaN power device, and the design structure is simpler. Secondly, since the internal temperature monitoring unit is directly integrated near the hot spot of the GaN device heat source (the gate drain side of the drift region), the temperature monitoring unit directly reflects the temperature information of the hot spot. Compared with the temperature monitoring and protection circuit designed outside the GaN device, the temperature monitoring accuracy of the designed circuit is higher. At the same time, the monolithic integrated circuit can reduce the parasitic effects caused by the interconnection in the circuit and give full play to the high-frequency and high-speed performance of the GaN device. Therefore, the over-temperature protection (OTP) circuit implemented based on the P-GaN gate GaN power device with an internally embedded distributed temperature monitoring unit can work intelligently under the harsh conditions of high temperature and high field, thereby solving the reliability problems caused by the device working at high temperature and high field, and laying a foundation for improving the application potential of commercial devices based on P-GaN gate GaN HEMT and further increasing the market share. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The topological structure diagram of a GaN over-temperature protection (OTP) circuit based on a GaN device with an embedded temperature monitoring unit applied to a GaN power system.

[0022] Figure 2 The schematic diagram of the circuit symbol of the GaN device with an embedded distributed temperature monitoring unit proposed in the present invention is shown in FIG. T express.

[0023] Figure 3 Schematic diagram of the cell structure of a P-GaN gate GaN HEMT device with an embedded temperature monitoring unit.

[0024] Figure 4 It is a schematic diagram of the structure of the comparator and the first, second and third inverter circuits in the GaN over-temperature protection (OTP) circuit.

[0025] Figure 5 V in the GaN over-temperature protection (OTP) circuit OTP Signal and Vref signal with V T 's change curve graph. DETAILED DESCRIPTION

[0026] The principle of the present invention is described below with reference to the accompanying drawings.

[0027] like Figure 1 As shown, the over-temperature protection circuit of the GaN device with an embedded temperature monitoring unit of the present invention includes, in addition to the GaN power device with an embedded distributed temperature monitoring unit, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a first transistor E1 consisting of a V T The specific circuit structure has been described in detail in the content of the invention, and will not be repeated here.

[0028] The working principle and process of the silicon-based GaN over-temperature protection circuit implemented by the present invention are described in detail below in conjunction with the accompanying drawings:

[0029] like Figure 4 As shown, comparators COMP, INV1, INV2 and INV3 include six transistors E2, E3, E4, E5, E6, E7 and E8, and five resistors R5, R6, R7, R8, R9 and R10. Among them, R5, E2 and E3 form a current mirror structure to provide bias current for the comparator tail tube E3. R6, R7, E3, E4 and E5 form the differential comparison input stage of the comparator COMP, among which R6 and R7 are load resistors, and E4 and E5 are differential input tubes. R8 and E6 form the first inverter, and R9 and E7 form the second inverter, that is, the output stage. The output of the two-stage inverter has a large output high and low level flip rate, so that V OTP The signal is stable and the high and low levels are obvious, thus avoiding V OTP The signal is fed back to the previous stage driver to cause an erroneous start operation. R10 and E8 form the third inverter, which is used to obtain V OTP The counter signal.

[0030] like Figure 1 As shown, V T The value is determined by the resistor R1 and the internal distributed temperature monitoring unit R T Vref is determined by the voltage division of resistors R2, R3 and R4. When the temperature of the GaN power device rises sharply, the distributed temperature monitoring unit R T The value increases. Under the condition that the external voltage makes the current constant to obtain the constant current source Isource, V T Increase, when V T When it is greater than Vref1, it outputs a high level V through COMP, INV1 and INV2 circuits. OTP_HThe high level is converted into a low level through INV3 and fed back to the front-end driver stage. Since the low level signal and the driving signal output by the driver circuit Driver simultaneously control the GaN device switch, the GaN power device is turned off; at the same time, the high level V OTP_H The signal acts on the gate of transistor E1, turning it on. At this time, resistor R4 is short-circuited. As long as the values ​​of R2, R3 and R4 are reasonably designed, the Vref1 value will decrease to Vref2 (Vref1>Vref2) as R4 is short-circuited. This is the triggering process of the over-temperature protection circuit. When the GaN power device is turned off and the temperature cools down, R T The value of V T Decrease, when V T When it is less than Vref2, the COMP, INV1 and INV2 circuits output a low level V OTP_L Signal, V OTP_L The signal is converted into a high level through INV3 and fed back to the front-end driver stage. Together with the drive signal output by the driver circuit Driver, it controls the GaN device switch to turn on. At the same time, the low level V OTP_L The signal turns off E1, and the value of Vref2 increases to the value of Vref1. This is the process in which the over-temperature protection circuit is not triggered, and this goes back and forth. The temperature threshold is determined by resistors R2, R3 and R4. Figure 5 The figure shows the V in the proposed GaN on Si over-temperature protection (OTP) circuit. OTP Signal and Vref signal with V T 's change curve graph.

Claims

1. An over-temperature protection circuit for a GaN device having an embedded temperature monitoring unit, characterized in that: A GaN power device including an embedded temperature monitoring unit, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor, a comparator, a first inverter INV1, a second inverter INV2, a third inverter INV3 and an AND gate circuit; One end of the first resistor R1 is connected to the working voltage, the other end of the first resistor R1 is connected to a metal electrode of a temperature monitoring unit embedded in the GaN power device and the positive input end of the comparator circuit, and the other metal electrode of the temperature monitoring unit is grounded; One end of the second resistor R2 is connected to the high level VDD, the other end of the second resistor R2 is simultaneously connected to one end of the third resistor R3 and the inverting input end of the comparator, the other end of the third resistor R3 is simultaneously connected to one end of the fourth resistor R4 and the drain of the first transistor, and the other end of the fourth resistor R4 and the source of the first transistor are grounded; The output end of the comparator is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is the output end of the over-temperature protection circuit; The input end of the third inverter INV3 and the gate of the first transistor E1 are connected to the output end of the over-temperature protection circuit; The output end of the third inverter INV3 is connected to one of the input ends of the AND gate circuit, the other input end of the AND gate circuit is connected to the external driving signal, the output end of the AND gate circuit is connected to the gate of the GaN power device, the drain of the GaN power device is connected to the external circuit, and the source of the GaN power device is grounded; The cell structure of the GaN power device comprises a substrate (01), a buffer layer (02) located on the upper surface of the substrate (01), a GaN channel layer (03) located on the upper surface of the buffer layer (02), an AlGaN barrier layer (04) located on the upper surface of the GaN channel layer (03), a source ohmic metal (08) and a drain ohmic metal (09); the GaN channel layer (03) and the AlGaN barrier layer (04) form a heterojunction; the upper surface of the AlGaN barrier layer (04) is covered with a passivation layer (07); the AlGaN barrier layer (04) and the passivation layer (07) are located on the source ohmic metal (08) and a drain ohmic metal (09), the source ohmic metal (08) and the drain ohmic metal (09) are respectively located at two ends of the upper surface of the GaN channel layer (03); a source field plate (10) is provided on the upper surface of the source ohmic metal (08), and the portion of the source field plate (10) located above the source field plate (10) is defined as a first vertical field plate; the top of the first vertical field plate extends along the lateral direction of the device toward the side close to the drain ohmic metal (09) to the middle of the device, and the extension portion is defined as a first lateral field plate; the end of the first lateral field plate extends along the vertical direction of the device toward the side close to the passivation layer (07), and the extension portion is defined as a second vertical field plate; the end of the second vertical field plate extends along the lateral direction of the device toward the side close to the drain ohmic metal (09), and the extension portion is defined as the second lateral field plate; the first lateral field plate, the second vertical field plate and the second lateral field plate form a zigzag structure; a P-GaN cap layer (05) is provided below the first lateral field plate, and the P-GaN cap layer (05) penetrates the passivation layer (07) along the vertical direction and directly contacts the AlGaN barrier layer (04); a gate metal (06) is provided on the upper surface of the P-GaN cap layer (05); a passivation layer (07) between the P-GaN cap layer (05) and the drain ohmic metal (09) 7) A temperature monitoring unit (11) is provided on the upper surface, and the second lateral field plate is located above the passivation layer (07) between the P-GaN cap layer (05) and the temperature monitoring unit (11); an isolation layer (12) is filled between the P-GaN cap layer (05) and the gate metal (06) and the first vertical field plate, the first lateral field plate, the second vertical field plate and the second lateral field plate, the isolation layer (12) also covers the drain ohmic metal (09), the temperature monitoring unit (11) and the upper surface of the passivation layer (07), and the height of the isolation layer (12) is flush with the first lateral field plate to completely wrap the second vertical field plate and the second lateral field plate.

2. An over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit according to claim 1, characterized in that: The comparator includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a second transistor, a third transistor, a fourth transistor and a fifth transistor; the first inverter INV1 includes an eighth resistor R8 and a sixth transistor; The second inverter INV2 includes a ninth resistor R9 and a seventh transistor; One end of the fifth resistor R5, one end of the sixth resistor R6, one end of the seventh resistor R7, one end of the eighth resistor R8, and one end of the ninth resistor R9 are all connected to the high level VDD, and the other end of the fifth resistor R5 is simultaneously connected to the gate and drain of the second transistor and the gate of the third transistor; the other end of the sixth resistor R6 is connected to the drain of the fourth transistor, and the source of the fourth transistor is simultaneously connected to the drain of the third transistor and the source of the fifth transistor; the other end of the seventh resistor R7 is simultaneously connected to the drain of the fifth transistor and the gate of the sixth transistor; the other end of the eighth resistor R8 is simultaneously connected to the drain of the sixth transistor and the gate of the seventh transistor; the other end of the ninth resistor R9 is connected to the drain of the seventh transistor and is also the output end of the over-temperature protection circuit; the source of the second transistor, the source of the third transistor, the source of the sixth transistor, and the source of the seventh transistor are all grounded; the gate of the fourth transistor is the positive input end of the comparator, and the gate of the fifth transistor is the reverse input end of the comparator.

3. The over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit according to claim 2, characterized in that: The third inverter INV3 includes a tenth resistor R10 and an eighth transistor; one end of the tenth resistor R10 is connected to the high level VDD, and the other end of the tenth resistor R10 is connected to the drain of the eighth transistor, and the connection point is the output end of the third inverter INV3; the gate of the eighth transistor is the input end of the third inverter INV3, and the source of the eighth transistor is grounded.

4. The over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit according to claim 3, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are all enhancement-mode GaN transistors.

5. The over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit according to claim 1, characterized in that: The material of the temperature monitoring unit (11) is any one of Ni / Au, Ti / Au, Pd / Au and Ni / Au / Ni.

6. The over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit according to claim 1, characterized in that: The lateral length of the temperature monitoring unit (11) is 1 to 5 um.

7. The over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit according to claim 1, characterized in that: The thickness of the P-GaN cap layer (05) is 50-80 nm.

8. The over-temperature protection circuit of a GaN device with an embedded temperature monitoring unit according to claim 1, characterized in that: The doping concentration of the P-GaN cap layer (05) is 1×10 17 cm -3 ~5x10 20 cm -3 .

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