Electrostatic discharge protection circuit with stable discharge mechanism

Abstract

An electrostatic discharge protection circuit with stable discharging mechanism. A voltage input end generates a detection signal according to a voltage input end, and a first inverter outputs an inverted detection signal. A first P-type and N-type transistor circuit of a voltage lifting circuit is connected in series between the voltage input end and a ground end through a first end, and a second P-type and N-type transistor circuit is connected in series between the voltage input end and the ground end through a second end. Control ends of the first and second P-type transistors are electrically connected to the second end and the first end, respectively, and control ends of the first and second N-type transistors receive the inverted detection signal and the detection signal, respectively. A second inverter receives an inverted lifting detection signal from the second end and outputs a lifting detection signal. An electrostatic discharge transistor is controlled by the lifting detection signal to discharge the voltage input end when turned on.

Description

Technical Field

[0001] This invention relates to electrostatic discharge protection technology, and more particularly to an electrostatic discharge protection circuit with a stable discharge mechanism. Background Technology

[0002] Electrostatic discharge (ESD) can cause permanent damage to electronic components and instruments, thereby affecting the circuit function of integrated circuits and making products unable to work properly.

[0003] Electrostatic discharge (ESD) can occur during chip manufacturing, packaging, testing, storage, or handling. To reproduce and prevent ESD, integrated circuit products can be enhanced with ESD-protected components or circuits, along with testing, to improve ESD protection capabilities and thus increase the yield of electronic products. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide an electrostatic discharge protection circuit with a stable discharge mechanism to improve the prior art.

[0005] This invention includes an electrostatic discharge protection circuit with a stable discharge mechanism, comprising: a voltage divider circuit, a first inverter, a voltage boosting circuit, a second inverter, and an electrostatic discharge transistor. The voltage divider circuit is electrically coupled to a voltage input terminal configured to receive a power supply signal, generating a detection signal at the voltage divider terminal. The first inverter is configured to receive the detection signal and invert its output as an inverted detection signal. The voltage boosting circuit includes: a first P-type transistor circuit, a first N-type transistor circuit, a second P-type transistor circuit, and a second N-type transistor circuit. The first P-type transistor circuit and the first N-type transistor circuit are connected in series between the voltage input terminal and a ground terminal via a first terminal, each having a first P-type transistor control terminal electrically coupled to a second terminal and a first N-type transistor control terminal configured to receive the inverted detection signal. The second P-type transistor circuit and the second N-type transistor circuit are connected in series between the voltage input terminal and a ground terminal via a second terminal, each having a second P-type transistor control terminal electrically coupled to a first terminal and a second N-type transistor control terminal configured to receive the detection signal. The second inverter is electrically coupled between the voltage input terminal and the ground terminal, configured to receive an inverted rise detection signal from the second terminal and output it as a rise detection signal. The electrostatic discharge transistor is electrically coupled between the voltage input terminal and the ground terminal, configured to be controlled by the rise detection signal to discharge the voltage input terminal when turned on.

[0006] Regarding the features, practices, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Attached Figure Description

[0007] Figure 1This diagram illustrates a circuit diagram of an electrostatic discharge protection circuit with a stable discharge mechanism, according to one embodiment of the present invention; and

[0008] Figure 2 This invention shows a circuit diagram of an electrostatic discharge protection circuit with a stable discharge mechanism, according to another embodiment of the invention. Detailed Implementation

[0009] One objective of this invention is to provide an electrostatic discharge (ESD) protection circuit with a stable discharge mechanism. By using a voltage divider circuit, it directly detects voltage changes caused by electrostatic input without being limited by conventional capacitive-resistive circuits. The ESD protection circuit can react quickly and maintain a sufficiently long discharge time, thereby stabilizing the discharge of the discharge transistor.

[0010] Please refer to Figure 1 . Figure 1 This diagram shows a circuit diagram of an electrostatic discharge protection circuit 100 with a stable discharge mechanism according to one embodiment of the present invention. The electrostatic discharge protection circuit 100 includes: a voltage divider circuit 110, a first inverter 120, a voltage boosting circuit 130, a second inverter 140, and an electrostatic discharge transistor 150.

[0011] Voltage divider circuit 110 is electrically coupled to voltage input terminal IO configured to receive power signal PS, so as to generate detection signal DS at voltage divider terminal DT.

[0012] In one embodiment, the voltage divider circuit 110 includes a first resistive circuit 115A and a second resistive circuit 115B, which are connected in series between the voltage input terminal IO and the ground terminal GND through the voltage divider terminal DT.

[0013] The first resistive circuit 115A includes a resistor, a diode, a diode-connected transistor, or a combination thereof. The number of these components can be one or more, and when there are multiple components, they can be connected in series. Figure 1 In the diagram, the first resistive circuit 115A is exemplary shown as a plurality of diode-connected P-type transistors, and the second resistive circuit 115B is exemplary shown as a single resistor. In other embodiments, it may also be implemented by the other elements described above, diode-connected N-type transistors, or combinations of various of the above elements. The invention is not limited thereto.

[0014] In one embodiment, the electrostatic discharge protection circuit 100 may be disposed in an electronic device (not shown), and when the electronic device is operating, it receives a power signal PS through the voltage input terminal IO, and generates a detection signal DS at the voltage divider terminal DT according to the resistance ratio between the first resistive circuit 115A and the second resistive circuit 115B.

[0015] The first inverter 120 operates according to a first voltage VDD1. The voltage boost circuit 130, the second inverter 140, and the electrostatic discharge transistor 150 operate according to a second voltage VDD2. The first voltage VDD1 is less than the second voltage VDD2. In one embodiment, the first voltage VDD1 is, for example, but not limited to, 0.9, 1.2, or 1.8 volts. The second voltage VDD2 is, for example, but not limited to, 3.3 volts.

[0016] In this embodiment, the second voltage VDD2 is generated based on the power supply signal PS. More specifically, in one embodiment, the voltage boost circuit 130, the second inverter 140, and the electrostatic discharge transistor 150 are electrically coupled to the voltage input terminal IO to receive the power supply signal PS. Furthermore, other circuit elements may be included between the aforementioned components and the voltage input terminal IO without affecting the overall functionality of the electrostatic discharge protection circuit 100.

[0017] In different embodiments, the first voltage VDD1 may be selectively generated by a separate power supply signal (not shown), or by a voltage divider based on the power supply signal PS.

[0018] Therefore, the internal components (e.g., transistors) of the first inverter 120 have relatively low threshold voltages, while the internal components (e.g., transistors) of the voltage boost circuit 130, the second inverter 140, and the electrostatic discharge transistor 150 have relatively high threshold voltages. The first inverter 120 has a higher response speed than the voltage boost circuit 130, the second inverter 140, and the electrostatic discharge transistor 150.

[0019] The first inverter 120 is configured to receive the detection signal DS and invert it to output an inverted detection signal IDS.

[0020] The voltage boost circuit 130 is configured to generate an inverted boost detection signal IBDS based on the detection signal DS and the inverted detection signal IDS. In one embodiment, the voltage boost circuit 130 includes: a first P-type transistor circuit 160A, a first N-type transistor circuit 160B, a second P-type transistor circuit 170A, and a second N-type transistor circuit 170B.

[0021] exist Figure 1 In the embodiments, the first P-type transistor circuit 160A includes a P-type transistor MP1, the first N-type transistor circuit 160B includes two first N-type transistors MN1 and a second N-type transistor MN2 connected in series, the second P-type transistor circuit 170A includes a P-type transistor MP2, and the second N-type transistor circuit 170B includes two first N-type transistors MN3 and a second N-type transistor MN4 connected in series.

[0022] The first P-type transistor circuit 160A and the first N-type transistor circuit 160B are connected in series between the voltage input terminal IO and the ground terminal GND through the first terminal T1, and each has a first P-type transistor control terminal electrically coupled to the second terminal T2 and a first N-type transistor control terminal configured to receive the inverted detection signal IDS.

[0023] More specifically, in Figure 1 In this embodiment, the source of the P-type transistor MP1 is electrically coupled to the voltage input terminal IO, the drain is electrically coupled to the first terminal T1, and the gate is electrically coupled to the second terminal T2 as the control terminal of the first P-type transistor. The drain of the first N-type transistor MN1 is electrically coupled to the first terminal T1, and the source is electrically coupled to the drain of the N-type transistor MN2. The drain of the second N-type transistor MN2 is electrically coupled to the source of the N-type transistor MN1, and the source is electrically coupled to the ground terminal GND. The gates of the first N-type transistor MN1 and the second N-type transistor MN2 are electrically coupled to each other and serve as the control terminal of the first N-type transistor to receive the inverted detection signal IDS.

[0024] The second P-type transistor circuit 170A and the second N-type transistor circuit 170B are connected in series between the voltage input terminal IO and the ground terminal GND through the second terminal T2. They each have a second P-type transistor control terminal electrically coupled to the first terminal T1 and a second N-type transistor control terminal configured to receive the detection signal DS.

[0025] To be more specific, in Figure 1 In this embodiment, the source of P-type transistor MP2 is electrically coupled to the voltage input terminal IO, the drain is electrically coupled to the second terminal T2, and the gate is electrically coupled to the first terminal T1 as the control terminal of the second P-type transistor. The drain of N-type transistor MN3 is electrically coupled to the second terminal T2, and the source is electrically coupled to the drain of N-type transistor MN4. The drain of N-type transistor MN4 is electrically coupled to the source of N-type transistor MN3, and the source is electrically coupled to the ground terminal GND. The gates of N-type transistors MN3 and MN4 are electrically coupled and serve as the control terminal of the second N-type transistor to receive the detection signal DS.

[0026] In one embodiment, the first N-type transistors MN1 and MN3 are input / output devices (I / O devices) with higher voltage ratings (e.g., 3.3 volts), while the second N-type transistors MN2 and MN4 are core devices with lower voltage ratings (0.9, 1.2, or 1.8 volts). This configuration provides better reliability for both the first N-type transistor circuit 160B and the second N-type transistor circuit 170B.

[0027] In one embodiment, the first N-type transistor circuit 160B may be selectively configured with an N-type transistor (not shown) connected in series with the first N-type transistor MN1 and the second N-type transistor MN2, and controlled by another control signal. This ensures that, when the sources of the aforementioned first voltage VDD1 and second voltage VDD2 are different, the first voltage VDD1 and second voltage VDD2 are both powered on before the circuit is enabled by this control signal, preventing the first N-type transistor circuit 160B from experiencing unknown signal states due to the order of power-on. Similarly, the second N-type transistor circuit 170B may also have the same configuration, which will not be described further here.

[0028] The second inverter 140 is electrically coupled between the voltage input terminal IO and the ground terminal GND, and is configured to receive the inverted boost detection signal IBDS from the second terminal T2 and output it as the boost detection signal BDS.

[0029] An electrostatic discharge transistor 150 is electrically coupled between the voltage input terminal IO and the ground terminal GND, and is configured to be controlled by a rise detection signal BDS to discharge the voltage input terminal IO when turned on. In this embodiment, the electrostatic discharge transistor 150 is an N-type transistor. In other embodiments, the electrostatic protection circuit 100 may also additionally provide another inverter between the electrostatic discharge transistor 150 and the second inverter 140, and implement the electrostatic discharge transistor 150 as a P-type transistor. The present invention is not limited thereto.

[0030] The following will explain the normal operation mode and discharge mode of the electrostatic discharge protection circuit 100, depending on the voltage magnitude of the voltage input terminal IO. Figure 1 In this context, the logic level of the voltage is used to indicate the high state level with "1" and the low state level with "0". The logic levels of the normal operation mode and the discharge mode are marked sequentially at each circuit node.

[0031] When the voltage at the voltage input terminal IO does not exceed the preset level, for example, when only the power signal PS is received and no static electricity input ES is received, such as from actual static electricity generation or electrical overshoot (EOS), the electrostatic discharge protection circuit 100 operates in normal operating mode. At this time, the detection signal DS generated by the voltage divider circuit 110 at the voltage divider terminal DT will be at a low level (0), while the inverting detection signal IDS will be at a high level (1) due to the operation of the first inverter 120.

[0032] Based on the inverted detection signal IDS at the high level and the detection signal DS at the low level, the second P-type transistor circuit 170A and the first N-type transistor circuit 160B will be turned on, and the first P-type transistor circuit 160A and the second N-type transistor circuit 170B will be turned off.

[0033] More specifically, in the first N-type transistor circuit 160B, the first N-type transistor MN1 and the second N-type transistor MN2 will be turned on due to the inverted detection signal IDS at a high level, drawing current from the first terminal T1 and causing the voltage of the first terminal T1 to drop to a low level (0), thereby turning on the P-type transistor MP2 in the second P-type transistor circuit 170A. Meanwhile, in the second N-type transistor circuit 170B, the first N-type transistor MN3 and the second N-type transistor MN4 will be turned off due to the detection signal DS at a low level, causing the second terminal T2 to receive current from the P-type transistor MP2 and causing the voltage of the second terminal T2 to rise to a high level (1), thereby turning off the P-type transistor MP1 in the first P-type transistor circuit 160A.

[0034] The inverted boost detection signal IBDS generated by the second terminal T2 is therefore at a high level (1). The boost detection signal BDS is at a low level (0) due to the operation of the second inverter 140, thereby turning off the electrostatic discharge transistor 150.

[0035] On the other hand, when the voltage at the voltage input terminal IO exceeds a preset level, for example, when a power signal PS is received at the same time as an electrostatic input ES with a momentary large voltage, the electrostatic discharge protection circuit 100 operates in discharge mode. At this time, the detection signal DS generated by the voltage divider circuit 110 at the voltage divider terminal DT will be at a high level (1), while the inverting detection signal IDS will be at a low level (0) due to the operation of the first inverter 120.

[0036] Based on the inverted detection signal IDS at the low level and the detection signal DS at the high level, the second P-type transistor circuit 170A and the first N-type transistor circuit 160B will be turned off, and the first P-type transistor circuit 160A and the second N-type transistor circuit 170B will be turned on.

[0037] More specifically, in the second N-type transistor circuit 170B, the first N-type transistor MN3 and the second N-type transistor MN4 will be turned on due to the detection signal DS at a high level, drawing current from the second terminal T2 and causing the voltage of the second terminal T2 to drop to a low level (0), thereby turning on the P-type transistor MP1 in the first P-type transistor circuit 160A. Meanwhile, in the first N-type transistor circuit 160B, the first N-type transistor MN1 and the second N-type transistor MN2 will be turned off due to the inverted detection signal IDS at a low level, causing the first terminal T1 to receive current from the P-type transistor MP1 and causing the voltage of the first terminal T1 to rise to a high level (1), thereby turning off the P-type transistor MP2 in the second P-type transistor circuit 170A.

[0038] The inverting boost detection signal IBDS generated by the second terminal T2 is therefore at a low level (0). The boost detection signal BDS is at a high level (1) due to the operation of the second inverter 140, which in turn turns on the electrostatic discharge transistor 150 and discharges the voltage input terminal IO.

[0039] It should be noted that when the electrostatic discharge transistor 150 discharges the voltage input terminal IO for a period of time, causing the voltage of the voltage input terminal IO to drop and the detection signal DS generated by the voltage divider to return to the low level (0), the electrostatic protection circuit 100 will also return to normal operation mode.

[0040] In some technologies, the electrostatic discharge (ESD) protection circuit uses a capacitive-resistive circuit connected to the ESD input terminal to control the inverter and determine whether to activate the discharge transistor. The capacitive-resistive circuit is configured based on the frequency of the ESD input to determine whether to activate the ESD discharge mechanism. If the ESD input is insufficient in duration or energy, a fully charged capacitive-resistive circuit will cause the inverter to react slowly, resulting in a later start-up time and an inability to maintain the discharge mechanism for a sufficient duration. Furthermore, under such conditions, the discharge transistor often relies on a breakdown mechanism to operate, leading to uneven conduction.

[0041] Therefore, the electrostatic discharge (ESD) protection circuit of the present invention can directly detect voltage changes caused by electrostatic input through the setting of a voltage divider circuit, without being limited by conventional capacitive-resistive circuits. The ESD protection circuit can react quickly and maintain a sufficiently long discharge time, thereby stabilizing the discharge of the discharge transistor.

[0042] It should be noted that the number of transistors included in the first P-type transistor circuit 160A, the first N-type transistor circuit 160B, the second P-type transistor circuit 170A, and the second N-type transistor circuit 170B described above is merely an example. In other embodiments, the number of transistors included in the above circuits can be adjusted according to actual needs, and the present invention is not limited thereto.

[0043] Please refer to Figure 2 . Figure 2 This diagram shows a circuit diagram of an electrostatic discharge protection circuit 200 with a stable discharge mechanism, according to another embodiment of the present invention.

[0044] Similar to Figure 1 Electrostatic discharge protection circuit 100, Figure 2The electrostatic discharge (ESD) protection circuit 200 includes: a voltage divider circuit 110, a first inverter 120, a voltage boosting circuit 130, a second inverter 140, and an ESD transistor 150. Furthermore, the voltage boosting circuit 130 also includes: a first P-type transistor circuit 160A, a first N-type transistor circuit 160B, a second P-type transistor circuit 170A, and a second N-type transistor circuit 170B. Therefore, components with the same structure and operation will not be described in detail here.

[0045] In this embodiment, the second P-type transistor circuit 170A includes two P-type transistors MP2 and MP3 connected in series. Furthermore, the voltage boosting circuit 130 also includes an N-type transistor MN5. The N-type transistor MN5 is electrically coupled between the first terminal T1 and the ground terminal GND, and has a third N-type transistor control terminal electrically coupled to the second terminal T2.

[0046] As mentioned earlier, when the electrostatic discharge protection circuit 100 operates in discharge mode, the second P-type transistor circuit 170A is turned off by the voltage of the first terminal T1 being at a high level. This causes the conducting second N-type transistor circuit 170B to draw current from the second terminal T2, resulting in a voltage drop at the second terminal T2. The voltage is then inverted by the second inverter 140 based on the low-level inverted rise detection signal IBDS, and output as a high-level rise detection signal BDS, thereby controlling the electrostatic discharge transistor 150 to turn on.

[0047] When the voltage at the electrostatic input terminal IO is too high, the source-gate voltage difference of the P-type transistor MP2 may become too high and cause it to conduct, thereby charging the second terminal T2. This causes the second terminal T2, which should be at a low level (0), to become unstable due to the pull between the second P-type transistor circuit 170A and the second N-type transistor circuit 170B. Therefore, by adding the P-type transistor MP3, the second P-type transistor circuit 170A can have a higher resistance to the voltage at the electrostatic input terminal IO and is less likely to conduct due to high voltage.

[0048] On the other hand, when the electrostatic discharge protection circuit 100 is operating in normal mode, the N-type transistor MN5 can keep the P-type transistors MP2 and MP3 of the second P-type transistor circuit 170A conducting more stably, thereby charging the second terminal T2 and causing the voltage of the second terminal T2 to rise. The second inverter 140 inverts the high-level inverted rise detection signal IBDS to output the low-level rise detection signal BDS, thus stably controlling the shutdown of the electrostatic discharge transistor 150.

[0049] exist Figure 2The following description uses a second P-type transistor circuit 170A comprising two P-type transistors connected in series as an example. In other embodiments, more than two P-type transistors may be provided in the second P-type transistor circuit 170A as needed to enhance the resistance to high voltages at the electrostatic input terminal IO. The present invention is not limited thereto.

[0050] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention.

[0051] In summary, the electrostatic discharge protection circuit with a stable discharge mechanism in this invention can directly detect voltage changes caused by electrostatic input through the setting of a voltage divider circuit, without being limited by conventional capacitive-resistive circuits. The electrostatic discharge protection circuit can react quickly and maintain a sufficiently long discharge time, thereby stabilizing the discharge of the discharge transistor.

[0052] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0053] [Symbol Explanation]

[0054] 100: Electrostatic discharge protection circuit

[0055] 110: Voltage divider circuit

[0056] 115A: First resistive circuit

[0057] 115B: Second Resistive Circuit

[0058] 120: First inverter

[0059] 130: Voltage boosting circuit

[0060] 140: Second inverter

[0061] 150: Electrostatic Discharge Transistor

[0062] 160A: First P-type transistor circuit

[0063] 160B: First N-type transistor circuit

[0064] 170A: Second P-type transistor circuit

[0065] 170B: Second N-type transistor circuit

[0066] 200: Electrostatic Discharge Protection Circuit

[0067] BDS: Lift Detection Signal

[0068] DS: Detection signal

[0069] DT: Voltage divider terminal

[0070] GND: Ground terminal

[0071] IBDS: Inverted Lift Detection Signal

[0072] IDS: Inverted detection signal

[0073] IO: Voltage input terminal

[0074] MN1, MN3: First N-type transistors

[0075] MN2, MN4: Second N-type transistors

[0076] MN5: N-type transistor

[0077] MP1, MP2, MP3: P-type transistor

[0078] PS: Power signal

[0079] T1: First end

[0080] T2: Second end

[0081] VDD1: First voltage

[0082] VDD2: Second voltage.

Claims

1. An electrostatic discharge protection circuit with a stable discharge mechanism, comprising: A voltage divider circuit is electrically coupled to a voltage input terminal configured to receive a power supply signal, so as to generate a detection signal at a voltage divider terminal; A first inverter is configured to receive the detection signal and invert the detection signal to output an inverted detection signal. A voltage boosting circuit, comprising: A first P-type transistor circuit and a first N-type transistor circuit are connected in series between the voltage input terminal and a ground terminal via a first terminal. The first P-type transistor circuit has a first P-type transistor control terminal electrically coupled to a second terminal, and the first N-type transistor circuit has a first N-type transistor control terminal configured to receive the inverted detection signal. A second P-type transistor circuit and a second N-type transistor circuit are connected in series between the voltage input terminal and the ground terminal through the second terminal. The second P-type transistor circuit has a second P-type transistor control terminal electrically coupled to the first terminal, and the second N-type transistor circuit has a second N-type transistor control terminal configured to receive the detection signal. A second inverter, electrically coupled between the voltage input terminal and the ground terminal, is configured to receive an inverted boost detection signal from the second terminal and invert the inverted boost detection signal to output a boost detection signal; and An electrostatic discharge transistor, electrically coupled between the voltage input terminal and the ground terminal, is configured to be controlled by the rise detection signal to discharge the voltage input terminal when turned on. The second P-type transistor circuit includes multiple P-type transistors connected in series. The voltage boosting circuit also includes an N-type transistor electrically coupled between the first terminal and the ground terminal, and has a third N-type transistor control terminal electrically coupled to the second terminal.

2. The electrostatic discharge protection circuit according to claim 1, wherein the first inverter operates according to a first voltage, the voltage boosting circuit, the second inverter, and the electrostatic discharge transistor operate according to a second voltage generated by the power supply signal, wherein the first voltage is less than the second voltage, and the first voltage is 0.9 volts, 1.2 volts, or 1.8 volts, and the second voltage is 3.3 volts.

3. The electrostatic discharge protection circuit according to claim 1, wherein the voltage divider circuit includes a first resistive circuit and a second resistive circuit, which are connected in series between the voltage input terminal and the ground terminal through the voltage divider terminal, wherein each of the first resistive circuit and the second resistive circuit includes a resistor, a diode, a diode-connected transistor, or a combination of the resistor, the diode, and the diode-connected transistor.

4. The electrostatic discharge protection circuit according to claim 1, wherein in a normal operating mode where the voltage at the voltage input terminal does not exceed a preset level, the detection signal is at a low level, the inverting detection signal is at a high level, the second P-type transistor circuit and the first N-type transistor circuit are turned on and the first P-type transistor circuit and the second N-type transistor circuit are turned off, the inverting rise detection signal is at the high level, and the rise detection signal is at the low level, thereby turning off the electrostatic discharge transistor.

5. The electrostatic discharge protection circuit according to claim 1, wherein in a discharge mode where the voltage at the voltage input terminal exceeds a preset level due to receiving an electrostatic input, the detection signal is at a high level, the inverted detection signal is at a low level, the second P-type transistor circuit and the first N-type transistor circuit are turned off and the first P-type transistor circuit and the second N-type transistor circuit are turned on, the inverted rise detection signal is at the low level, and the rise detection signal is at the high level, thereby turning on the electrostatic discharge transistor.

6. The electrostatic discharge protection circuit according to claim 1, wherein each of the first N-type transistor circuit and the second N-type transistor circuit comprises a first N-type transistor and a second N-type transistor connected in series, wherein the first N-type transistor is an input / output device and the second N-type transistor is a core device.

7. The electrostatic discharge protection circuit according to claim 1, wherein the second voltage is generated by the power supply signal, and the first voltage is generated by another independent voltage source signal.

8. The electrostatic discharge protection circuit according to claim 1, wherein the second voltage is generated by the power supply signal, and the first voltage is generated by voltage division of the power supply signal.

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