A soft-start circuit for power switching and its control method

Abstract

This invention provides a soft-start circuit for power switching, including a first transistor controlling a first power input system device, a second transistor controlling a second power input system device, and a plug-in / plug-out detection circuit. The plug-in / plug-out detection circuit outputs a plug-in / plug-out status signal to a control circuit. The control circuit includes a first soft-start control circuit, a second soft-start control circuit, and an inverting circuit. The first soft-start control circuit receives the plug-in / plug-out status signal through the inverting circuit and controls the first transistor to turn off or slowly turn on. The second soft-start circuit receives the plug-in / plug-out status signal and controls the second transistor to turn off or slowly turn on. This invention, through the design of a symmetrical soft-start control circuit, enables stable and reliable smooth power switching, thereby ensuring the safety and reliability of power supply to system devices. Furthermore, the circuit structure is simple and easy to integrate, which is beneficial for improving production efficiency and expanding application prospects.

Description

Technical Field

[0001] This invention relates to the field of power switching technology, and more specifically to a soft-start circuit and its control method for power switching. Background Technology

[0002] In multi-power supply products, power switching is an essential function. For example, in an emergency power server, when the main power supply circuit experiences an abnormal power outage, it will immediately switch to the backup power supply to ensure that the server's power supply is not interrupted. Furthermore, in portable power banks, when the adapter is plugged in, the input power supplies the system devices and can charge the battery; when the adapter is unplugged, the system devices will be powered by the battery.

[0003] like Figure 1 As shown, Figure 1 A power switching circuit includes a transistor MP200 for controlling an input power input system device 300, a transistor MP300 for controlling a backup power input system device 300, and a plug-in / plug-out detection circuit 200. The plug-in / plug-out detection circuit 200 is used to detect whether the input power can supply power normally and outputs a signal PINOUT1 to a buffer BUF0 and an inverter INV0. The buffer BUF0 outputs a signal PGATE3 to the transistor MP200, and the inverter INV0 outputs a signal PGATE4 to the transistor MP300.

[0004] When an adapter is plugged into the input power supply, the plug-in / plug-out detection circuit 200 detects the plugging. At this time, the signal PINOUT1 changes from high to low. After passing through the inverter INV0, the signal PGATE4 becomes high, and the transistor MP300 is turned off, thus quickly disconnecting the backup power supply. After passing through the buffer BUF0, the signal PGATE3 becomes low, and the transistor MP200 turns on. At this time, the input voltage VOUT1 of the system device 300 will rapidly rise from the backup power supply voltage BAT1 to the input power supply voltage VIN1.

[0005] When the input power adapter is unplugged, the plug-in / plug-out detection circuit 200 detects the unplugging. At this time, signal PINOUT1 changes from low to high, signal PGATE3 becomes high, transistor MP200 is turned off, and the backup input power supply is quickly disconnected. Signal PGATE4 becomes low, and the system device 300 input voltage VOUT1 quickly drops from the input power supply voltage VIN1 to the backup power supply voltage BAT1.

[0006] like Figure 2 As shown, Figure 2The waveform diagram of the power switching circuit above shows that the greater the difference between the input power supply voltage VIN1 and the backup power supply voltage BAT1, the greater the transient change of the input voltage VOUT1 of the system device 300, and the greater the impact of the power switching circuit on the system device 300.

[0007] Because the voltages of different power supplies are not the same, a direct switch between power supplies will cause a momentary change in the power supply. In some systems and devices that are sensitive to power transients, this change can cause abnormal operation of the system and devices, such as data loss or system shutdown. In severe cases, it can lead to damage, restart, crash, or even burnout of the system and devices.

[0008] Disadvantages of existing technology:

[0009] 1. The existing power switching circuit has a high risk of use. The existing power switching circuit adopts direct switching, which makes the transient changes of the input power of the system equipment increase with the increase of the voltage difference of the switching power supply, which greatly increases the risk of abnormal operation or even damage to the system equipment.

[0010] 2. Existing power switching circuits have poor applicability and cannot be used in systems and equipment that are sensitive to power transient changes;

[0011] 3. Existing power switching circuits reduce the reliability of the power supply.

[0012] Therefore, there is an urgent need for a soft-turn-on circuit for power switching to enable smooth power switching, thereby improving power reliability and the applicability of power switching circuits, and avoiding excessive power transient changes that could affect the operation of system equipment. Summary of the Invention

[0013] The present invention provides a soft-start circuit and its control method for power switching, which is mainly used to solve the problems of excessive transient changes during power switching affecting the operation of system equipment, reducing the applicability of the switching circuit and the reliability of the power supply. The invention achieves smooth power switching to avoid excessive transient changes during power switching and improves the applicability of the switching circuit and the reliability of the power supply.

[0014] The present invention achieves the above objectives through the following technical solutions:

[0015] A soft-turn-on circuit for power switching includes a first transistor controlling a first power input to a system device, a second transistor controlling a second power input to the system device, and a plug-in / plug-out detection circuit. The plug-in / plug-out detection circuit is connected to the first power supply and outputs a plug-in / plug-out status signal to a control circuit. The control circuit controls the operating states of the first transistor and the second transistor to switch the system device's input to the first power supply or the second power supply. The control circuit includes a first soft-turn-on control circuit, a second soft-turn-on control circuit, and an inverting circuit. The first soft-turn-on control circuit receives the plug-in / plug-out status signal through the inverting circuit. The input terminal of the first soft-turn-on control circuit is connected to the first power supply and the system device. The power control circuit outputs a first switch control signal to the first transistor. The second soft-start control circuit is connected to the insertion / removal status signal. The input terminal of the second soft-start control circuit is connected to the second power supply and the system device. The second soft-start control circuit outputs a second switch control signal to the second transistor. When the second switch control signal turns off the second transistor, the first switch control signal slowly turns on the first transistor until the input power value of the system device slowly reaches the first power value. When the first switch control signal turns off the first transistor, the second switch control signal slowly turns on the second transistor until the input power value of the system device slowly reaches the second power value.

[0016] A further embodiment is that the source of the first transistor is connected to the first power supply, an output capacitor is provided on the connection path between its drain and the system device, and its gate is connected to the first switch control signal.

[0017] A further embodiment is that the drain of the second transistor is connected to the second power supply, its source is connected to the system device, and its gate is connected to the second switch control signal.

[0018] A further embodiment is that the first soft-turn-on control circuit and the second soft-turn-on control circuit have the same circuit structure, including an operational amplifier circuit, a differential voltage detection circuit, a sampling timing control circuit, a soft-turn-on voltage circuit, and a first bias current circuit. The enable terminal of the operational amplifier circuit is connected to the insertion / removal status signal, and the operational amplifier circuit outputs a switch control signal, which is either a first switch control signal or a second switch control signal. The differential voltage detection circuit is connected to the input power supply and the switching power supply of the system device, which is either a first power supply or a second power supply. The differential voltage detection circuit connects the input power supply of the system device to the switching power supply. The voltage difference of the switching power supply is converted into a differential voltage signal and output to the second input terminal of the operational amplifier circuit. The sampling timing control circuit receives the insertion / removal status signal and outputs a low-level sampling pulse signal to the soft-turn-on voltage circuit according to the rising edge of the insertion / removal status signal. The soft-turn-on voltage circuit receives the differential voltage signal and samples the maximum value of the differential voltage signal according to the low-level sampling pulse signal. The soft-turn-on voltage circuit outputs a soft-turn-on voltage to the first input terminal of the operational amplifier circuit. The first bias current circuit receives a first bias current, and its output terminal is connected to the soft-turn-on voltage circuit.

[0019] A further embodiment is that the differential pressure detection circuit includes a feedback calculation circuit, a first current mirror circuit, a second current mirror circuit, and a second bias current circuit. The feedback calculation circuit is connected to the input power supply and the switching power supply of the system device. The output terminal of the feedback calculation circuit is connected to the input terminal of the first current mirror circuit. The output terminal of the first current mirror circuit is connected to the input terminal of the second current mirror circuit, and their common terminal is connected to a first potential. The output terminal of the second current mirror circuit outputs the differential voltage signal, and its common terminal is connected to a second potential.

[0020] A further embodiment is that the feedback operation circuit includes an operational amplifier, a fourth transistor, and a first resistor. The inverting input of the operational amplifier is connected to the input power supply of the system device, and its non-inverting input is connected to the switching power supply through the first resistor and shorted to the drain of the fourth transistor. The output of the operational amplifier is connected to the gate of the fourth transistor, and the source of the fourth transistor is connected to the input of the first current mirror circuit.

[0021] A further embodiment is that the sampling timing control circuit includes a delay module, a second inverter, and a second NAND gate. The delay module is connected to the insertion / removal status signal, and the output of the delay module is connected to the first input of the second NAND gate through the second inverter. The second input of the second NAND gate is connected to the insertion / removal status signal.

[0022] A further embodiment is that the soft-turn-on voltage circuit includes a second P-type transistor, a third N-type transistor, and a bypass capacitor. The gates of both the second P-type transistor and the third N-type transistor are connected to the low-level sampling pulse signal, the source of the second P-type transistor is connected to the differential-mode voltage signal, the source of the third N-type transistor is connected to the output terminal of the first bias current circuit, and the drains of both the second P-type transistor and the third N-type transistor are connected to the first potential through the bypass capacitor. The soft-turn-on voltage is output from the drains of the second P-type transistor and the third N-type transistor.

[0023] A further embodiment is that the first bias current circuit includes a third current mirror circuit, the third current mirror circuit is connected to the first bias current, its output terminal is connected to the source of the third N-type transistor, and its common terminal is connected to the first potential.

[0024] A control method for a soft-start circuit for power switching, applied to the aforementioned soft-start circuit for power switching, includes the following steps: When a plug-in / plug-out detection circuit detects the insertion of a first power source, the plug-in / plug-out status signal level changes from high to low. At this time, the output level of a second soft-start control circuit rapidly increases, causing a second transistor to rapidly turn off. The plug-in / plug-out status signal is then converted to a high level by an inverting circuit and input to the first soft-start control circuit. The output level of the first soft-start control circuit slowly decreases, causing the first transistor to slowly turn on until the input power value of the system device slowly reaches the first power value. When the plug-in / plug-out detection circuit detects the removal of the first power source, the plug-in / plug-out status signal level changes from low to high. At this time, the plug-in / plug-out status signal is converted to a low level by the inverting circuit and input to the first soft-start control circuit. The output level of the first soft-start control circuit rapidly increases, causing the first transistor to rapidly turn off. The output level of the second soft-start control circuit slowly decreases, causing the second transistor to slowly turn on until the input power value of the system device slowly reaches the second power value, thereby realizing the switching of the system device's input power from the first power source to the second power source.

[0025] Therefore, the present invention has the following beneficial effects:

[0026] 1. The soft-start circuit for power switching of the present invention enables smooth power switching, has good stability and high reliability, and ensures safe and reliable power supply for system equipment.

[0027] 2. The soft-start circuit for power switching of the present invention enables smooth power switching and is also applicable to system equipment that is sensitive to power transient changes, thus having high applicability.

[0028] 3. This invention designs two soft-turn-on control circuits with identical circuit structures, which makes the circuit structure simple and symmetrical, simplifies circuit analysis and production process, and improves production efficiency.

[0029] 4. The soft-start circuit for power switching of the present invention is easy to integrate, has low production cost, and has high utilization value and broad application prospects.

[0030] Therefore, the present invention provides a soft-start circuit and its control method for power switching. By designing a soft-start control circuit with a consistent circuit structure, the power supply can be switched smoothly and reliably. The circuit structure is simple and easy to integrate, thereby achieving the effect of ensuring the safety and reliability of power supply to system equipment, while having good circuit applicability, high production efficiency and broad application prospects.

[0031] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a power switching circuit in the existing technology.

[0033] Figure 2 This is a waveform diagram of a power switching circuit in existing technology.

[0034] Figure 3 This is a schematic diagram of a soft-start circuit for power switching according to the present invention.

[0035] Figure 4 This is a waveform diagram of a soft-start circuit for power switching according to the present invention.

[0036] Figure 5 This is a schematic diagram of the first soft-start control circuit or the second soft-start control circuit of the present invention.

[0037] Figure 6 This is a waveform diagram of the first soft-start control circuit or the second soft-start control circuit of the present invention.

[0038] Figure 7 This is a schematic diagram of the differential pressure detection circuit of the present invention.

[0039] Figure 8 This is a schematic diagram of the sampling timing control circuit of the present invention.

[0040] Figure 9 This is a waveform diagram of the sampling timing control circuit of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0042] An embodiment of a soft-turn-on circuit for power switching

[0043] See Figure 3-9 The present invention relates to a soft-start circuit for power switching, comprising a first transistor MP0 controlling the input of a first power supply 101 to a system device 103, a second transistor MP1 controlling the input of a second power supply 102 to the system device 103, and a plug-in / plug-out detection circuit 104. The plug-in / plug-out detection circuit 104 is connected to the first power supply 101 and outputs a plug-in / plug-out status signal PINOUT to a control circuit 100. The control circuit 100 controls the operating states of the first transistor MP0 and the second transistor MP1 to switch the system device 103 input to either the first power supply 101 or the second power supply 102. The control circuit 100 includes a first soft-start control circuit 10, a second soft-start control circuit 20, and an inverting circuit 30. The first soft-start control circuit 10 is connected to the plug-in / plug-out status signal PINOUT through the inverting circuit 30. The input terminal of the first soft-start control circuit 10 is connected to the first power supply 101 and the system device 103. Control circuit 10 outputs a first switch control signal PGATE0 to the first transistor MP0. The second soft-start control circuit 20 is connected to the insertion / removal status signal PINOUT. The input terminal of the second soft-start control circuit 20 is connected to the second power supply 102 and the system device 103. The second soft-start control circuit 20 outputs a second switch control signal PGATE1 to the second transistor MP1. When the second switch control signal PGATE1 turns off the second transistor MP1, the first switch control signal PGATE0 slowly turns on the first transistor MP0 until the input power supply value VOUT of the system device 103 slowly reaches the value VIN of the first power supply 101. When the first switch control signal PGATE0 turns off the first transistor MP0, the second switch control signal PGATE1 slowly turns on the second transistor MP1 until the input power supply value VOUT of the system device 103 slowly reaches the value BAT of the second power supply 102.

[0044] Specifically, in this embodiment, the value VIN of the first power supply 101 is greater than the value BAT of the second power supply 102.

[0045] Specifically, in this embodiment, both the first soft-turn-on control circuit 10 and the second soft-turn-on control circuit 20 are provided with a non-inverting input terminal VP, an inverting input terminal VN, and an enable input terminal CTL. The non-inverting input terminal VP of the first soft-turn-on control circuit 10 is connected to the first power supply 101, and the inverting input terminal VN of the first soft-turn-on control circuit 10 is connected to the system device 103.

[0046] In this circuit, the enable input terminal CTL of the second soft-start control circuit 20 is directly connected to the insertion / removal status signal PINOUT, the non-inverting input terminal VP of the second soft-start control circuit 20 is connected to the system device 103, and the inverting input terminal VN of the second soft-start control circuit 20 is connected to the second power supply 102.

[0047] Specifically, in this embodiment, the inverter circuit 30 includes a first inverter INV1, which inverts the phase of the insertion / removal status signal PINOUT by 180 degrees and outputs it to the enable input terminal CTL of the first soft-turn-on control circuit 10.

[0048] In this embodiment, the source of the first transistor MP0 is connected to the first power supply 101, the drain of the first transistor MP0 is connected to the system device 103 via an output capacitor C0, and the gate of the first transistor MP0 is connected to the first switch control signal PGATE0.

[0049] In this embodiment, the drain of the second transistor MP1 is connected to the second power supply 102, its source is connected to the system device 103, and its gate is connected to the second switch control signal PGATE1.

[0050] Specifically, in this embodiment, both the first transistor MP0 and the second transistor MP1 are PMOS transistors.

[0051] In this embodiment, the first soft-turn-on control circuit 10 and the second soft-turn-on control circuit 20 have the same circuit structure, including an operational amplifier circuit 21, a differential voltage detection circuit 22, a sampling timing control circuit 23, a soft-turn-on voltage circuit 24, and a first bias current circuit 25. The enable terminal of the operational amplifier circuit 21 is connected to the insertion / removal status signal PINOUT, and the operational amplifier circuit 21 outputs a switch control signal PGATE, which is either the first switch control signal PGATE0 or the second switch control signal PGATE1. The differential voltage detection circuit 22 is connected to the input power supply and the switching power supply of the system device 103, wherein the switching power supply is either the first power supply 101 or the second power supply 102. The differential voltage detection circuit 22 connects the input power supply of the system device 103 to the switching power supply of the system device 103. The voltage difference of the switching power supply is converted into a differential voltage signal VDIFF and output to the second input terminal of the operational amplifier circuit 21. The sampling timing control circuit 23 receives the insertion / removal status signal PINOUT and outputs a low-level sampling pulse signal SENCLK to the soft-turn-on voltage circuit 24 according to the rising edge of the insertion / removal status signal PINOUT. The soft-turn-on voltage circuit 24 receives the differential voltage signal VDIFF and samples the maximum value of the differential voltage signal VDIFF according to the low-level sampling pulse signal SENCLK. The soft-turn-on voltage circuit 24 outputs the soft-turn-on voltage SS_VREF to the first input terminal of the operational amplifier circuit 21. The first bias current circuit 25 receives the first bias current IB and its output terminal is connected to the soft-turn-on voltage circuit 24.

[0052] Specifically, in this embodiment, the operational amplifier circuit 21 includes an operational amplifier OP1 with an enable signal. The enable terminal of the operational amplifier OP1 is connected to the insertion / removal status signal PINOUT. When the level of the insertion / removal status signal PINOUT changes from high to low, the operational amplifier OP1 is turned off and the switch control signal PAGTE becomes high. When the level of the insertion / removal status signal PINOUT changes from low to high, the operational amplifier OP1 is enabled.

[0053] Specifically, in this embodiment, during the soft-start process, the first soft-start control circuit 10 or the second soft-start control circuit 20 forms a negative feedback loop with the differential voltage signal VDIFF, the soft-start voltage SS_VREF, the operational amplifier OP1, and the transistors (first transistor MP0 or second transistor MP1) of the input power supply voltage VOUT of the control system device 103, so that the differential voltage signal VDIFF follows the change of the soft-start voltage SS_VREF.

[0054] Specifically, the soft-start time T of the first soft-start control circuit 10 or the second soft-start control circuit 20 in this embodiment is:

[0055]

[0056] Among them, VDIFF (max)The sampling time difference voltage signal VDIFF is the maximum value, IB is the first bias current, and C1 is the value of the bypass capacitor C1 in the soft-turn-on voltage circuit 24.

[0057] In this embodiment, the differential pressure detection circuit 22 includes a feedback calculation circuit 221, a first current mirror circuit 222, a second current mirror circuit 223, and a second bias current circuit 224. The feedback calculation circuit 221 is connected to the input power supply of the system device 103 and the switching power supply. The output terminal of the feedback calculation circuit 221 is connected to the input terminal of the first current mirror circuit 222. The output terminal of the first current mirror circuit 222 is connected to the input terminal of the second current mirror circuit 223. Their common terminal is connected to a first potential. The output terminal of the second current mirror circuit 223 outputs a differential mode voltage signal VDIFF. Its common terminal is connected to a second potential.

[0058] Specifically, in this embodiment, the second bias current circuit 224 includes a DC bias current source I0 and a second resistor R2. The DC bias current source I0 is connected in parallel to the common terminal and the output terminal of the second current mirror circuit 223, and is connected to the first potential through the second resistor R2.

[0059] Specifically, in this embodiment, the first current mirror circuit 222 includes a fifth N-type transistor MN5 and a sixth N-type transistor MN6, which are common-gate and common-source transistors. The common-source terminals of the fifth N-type transistor MN5 and the sixth N-type transistor MN6 are connected to the first potential. The drain of the fifth N-type transistor MN5 is shorted to its gate, and its drain is connected to the output terminal of the feedback operation circuit 221. The drain of the sixth N-type transistor MN6 is connected to the input terminal of the second current mirror circuit 223.

[0060] Specifically, in this embodiment, the second current mirror circuit 223 includes a third P-type transistor MP3 and a fourth P-type transistor MP4 with common gate and common source. The common source terminals of the third P-type transistor MP3 and the fourth P-type transistor MP4 are connected to the second potential. The drain of the third P-type transistor MP3 is shorted to its gate, and its drain is connected to the drain of the sixth N-type transistor MN6. The drain of the fourth P-type transistor MP4 is connected to the first potential through the second resistor R2.

[0061] Specifically, in this embodiment, the first potential is the ground potential, and the second potential is the high potential.

[0062] Specifically, in this embodiment, it is assumed that the fifth N-type transistor MN5 and the sixth N-type transistor MN6 have the same size, and the third P-type transistor MP3 and the fourth P-type transistor MP4 have the same size. Then, the voltage of the differential mode voltage signal VDIFF is:

[0063]

[0064] Wherein, VP is the input voltage value of the non-inverting input terminal VP, VN is the input voltage value of the inverting input terminal VN, R2 is the resistance value of the second resistor R2, and I0 is the current of the DC bias current source I0.

[0065] Substituting formula (2) into formula (1), we can obtain the soft-start time T of the first soft-start control circuit 10 or the second soft-start control circuit 20 as:

[0066]

[0067] Specifically, in this embodiment, it can be derived from formula (2) that when the soft turn-on ends, VP = VN, and at this time VDIFF = I0*R2, that is, the differential voltage signal VDIFF has a DC potential.

[0068] The DC potential of the differential voltage signal VDIFF causes the switching control signal PGATE output by the operational amplifier OP1 to be completely pulled down to ground potential, so as to ensure that the transistor (first transistor MP0 or second transistor MP1) of the input power supply voltage VOUT of the control system device 103 is fully turned on.

[0069] In this embodiment, the feedback operation circuit 221 includes an operational amplifier, a fourth transistor MN4, and a first resistor R1. The inverting input terminal VN of the operational amplifier OP2 is connected to the input power supply of the system device 103, and its non-inverting input terminal VP is connected to the switching power supply through the first resistor R1 and shorted to the drain of the fourth transistor MN4. The output terminal of the operational amplifier OP2 is connected to the gate of the fourth transistor MN4, and the source of the fourth transistor MN4 is connected to the input terminal of the first current mirror circuit 222.

[0070] Specifically, in this embodiment, operational amplifier OP2, the fourth transistor MN4, and the first resistor R1 form a feedback loop, making the voltage VM at the non-inverting input terminal of operational amplifier OP2 equal to the voltage VN at the inverting input terminal of operational amplifier OP2.

[0071] The current I through the fourth transistor MN4 is:

[0072]

[0073] Where VP is the input voltage value at the non-inverting input terminal of operational amplifier OP2, VN is the input voltage value at the inverting input terminal of operational amplifier OP2, and R1 is the resistance value of the first resistor R1.

[0074] In this embodiment, the sampling timing control circuit 23 includes a delay module 231, a second inverter INV2, and a second NAND gate ND2. The delay module 231 is connected to the insertion / removal status signal PINOUT. The output terminal of the delay module 231 is connected to the first input terminal of the second NAND gate ND2 through the second inverter INV2. The second input terminal of the second NAND gate ND2 is connected to the insertion / removal status signal PINOUT.

[0075] Specifically, in this embodiment, the sampling timing control circuit 23 generates a low-level sampling pulse signal SENCLK starting from the rising edge of the insertion / removal status signal PINOUT.

[0076] See Figure 9 When the PINOUT insertion / removal status signal changes from low to high, due to the delay effect of the delay module 231, the output of the delay module 231 remains low for a period of time, while the output of the second inverter INV2 is high. After passing through the second NAND gate ND2, the resulting low-level sampling pulse signal SENCLK is low. After a delay, the output of the delay module 231 becomes high, the output of the second inverter INV2 becomes low, and after passing through the second NAND gate ND2, the resulting low-level sampling pulse signal SENCLK becomes high. When the PINOUT insertion / removal status signal changes from high to low, due to the logic control of the second NAND gate ND2 at this time, its output low-level sampling pulse signal SENCLK remains high.

[0077] In this embodiment, the soft-turn-on voltage circuit 24 includes a second P-type transistor MP2, a third N-type transistor MN3, and a bypass capacitor C1. The gates of the second P-type transistor MP2 and the third N-type transistor MN3 are both connected to a low-level sampling pulse signal SENCLK. The source of the second P-type transistor MP2 is connected to a differential-mode voltage signal VDIFF. The source of the third N-type transistor MN3 is connected to the output terminal of the first bias current circuit 25. The drains of the second P-type transistor MP2 and the third N-type transistor MN3 are both connected to the first potential through the bypass capacitor C1. The soft-turn-on voltage is output from the drains of the second P-type transistor MP2 and the third N-type transistor MN3.

[0078] Specifically, in this embodiment, the voltage of the bypass capacitor C1 is the soft-turn-on voltage SS_VREF.

[0079] In this embodiment, the first bias current circuit 25 includes a third current mirror circuit. The third current mirror circuit is connected to the first bias current IB, and its output terminal is connected to the source of the third N-type transistor MN3. Its common terminal is connected to the first potential.

[0080] Specifically, the third current mirror circuit in this embodiment includes a first N-type transistor MN1 and a second N-type transistor MN2 with common gate and common source. The common source terminals of the first N-type transistor MN1 and the second N-type transistor MN2 are connected to the first potential. The drain of the first N-type transistor MN1 is shorted to the gate, and its drain is connected to the first bias current IB. The drain of the second N-type transistor MN2 is connected to the source of the third N-type transistor MN3.

[0081] For details, see Figure 6 In this embodiment, when the low-level sampling pulse signal SENCLK is a low-level pulse, the second P-type transistor MP2 is turned on and the third N-type transistor MN3 is turned off. At this time, the soft-turn-on voltage SS_VREF will quickly rise to the maximum value of the differential mode voltage signal VDIFF.

[0082] When the low-level sampling pulse signal SENCLK is a high-level pulse, the second P-type transistor MP2 is turned off, and the third N-type transistor MN3 is turned on. Since the second N-type transistor MN2 has a first bias current IB mirrored by the first N-type transistor MN1, the soft-turn-on voltage SS_VREF will slowly decrease from the maximum value of the differential voltage signal VDIFF. The soft-turn-on voltage SS_VREF is:

[0083]

[0084] Among them, VDIFF (max) The sampling time difference voltage signal VDIFF is the maximum value, IB is the first bias current, and t is the fall time of the soft-turn-on voltage SS_VREF.

[0085] An embodiment of a control method for a soft-turn-on circuit for power switching

[0086] A control method for a soft-turn-on circuit for power switching, applied to the aforementioned soft-turn-on circuit for power switching, includes the following steps: When the insertion / removal detection circuit 104 detects the insertion of the first power supply 101, the insertion / removal status signal PINOUT changes from high to low. At this time, the output level of the second soft-turn-on control circuit 20 rapidly increases, causing the second transistor MP1 to rapidly turn off. The insertion / removal status signal PINOUT is then changed to a high level through the inverting circuit 30 and input to the first soft-turn-on control circuit 10. The output level of the first soft-turn-on control circuit 10 slowly decreases, causing the first transistor MP0 to slowly turn on, until the input power value of the system device 103 slowly reaches the threshold value. The first power supply 101 value is determined by the insertion / removal detection circuit 104. When the insertion / removal detection circuit 104 detects that the first power supply 101 has been removed, the insertion / removal status signal PINOUT changes from low to high. At this time, the insertion / removal status signal PINOUT is changed to a low level through the inverting circuit 30 and input to the first soft-turn-on control circuit 10. The output level of the first soft-turn-on control circuit 10 is quickly pulled up, causing the first transistor MP0 to be quickly turned off. The output level of the second soft-turn-on control circuit 20 slowly decreases, causing the second transistor MP1 to be slowly turned on, until the input power supply value of the system device 103 slowly reaches the value of the second power supply 102, thereby realizing the switching of the system device 103 to the input of the first power supply 101 and the second power supply 102.

[0087] Specifically, in this embodiment, when the output level of the first soft-turn-on control circuit 10 slowly decreases, the input power supply voltage VOUT of the system device 103 gradually rises from the voltage value BAT of the second power supply 102 to the voltage value VIN of the first power supply 101 after the soft-turn-on time T1 of the first soft-turn-on control circuit 10. At this time, the output level of the first soft-turn-on control circuit 10 is completely pulled low, and the first transistor MP0 is fully turned on.

[0088] Specifically, when the output level of the second soft-turn-on control circuit 20 in this embodiment slowly decreases, the input power supply voltage VOUT of the system device 103 gradually decreases from the voltage value VIN of the first power supply 101 to the voltage value BAT of the second power supply 102 after the soft-turn-on time T2 of the second soft-turn-on control circuit 20. At this time, the output level of the second soft-turn-on control circuit 20 is completely pulled low, and the second transistor MP1 is fully turned on.

[0089] The soft-on time T1 of the first soft-on control circuit 10 and the soft-on time T2 of the second soft-on control circuit 20 are calculated by formula (3).

[0090] Specifically, in this embodiment, when the insertion / removal status signal PINOUT changes from low to high, the sampling timing control circuit 23 generates a low-level sampling pulse signal SENCLK, which samples the maximum value VDIFF(max) of the differential voltage signal VDIFF at this time onto the bypass capacitor C1. At this time, the soft-turn-on voltage SS_VREF is equal to the maximum value VDIFF(max) of the differential voltage signal VDIFF.

[0091] Specifically, in this embodiment, after sampling VDIFF(max) ends, the soft-turn-on voltage SS_VREF gradually decreases. Due to the negative feedback effect, the voltage of the output switch control signal PGATE of operational amplifier OP1 gradually decreases accordingly. At this time, the voltage difference between the non-inverting input terminal VP and the inverting input terminal VN of operational amplifier OP2 also decreases. Until after the soft-turn-on time T, the soft-turn-on voltage SS_VREF is zero, and the voltage difference between the non-inverting input terminal VP and the inverting input terminal VN of operational amplifier OP2 also drops to zero. At this time, the differential voltage signal VDIFF has only a very small DC potential to ensure that the output switch control signal PGATE of operational amplifier OP1 is completely pulled low, that is, the transistor (first transistor MP0 or second transistor MP1) of the input power supply voltage VOUT of the control system device 103 is fully turned on.

[0092] During the decrease of the soft-turn-on voltage SS_VREF, when the differential-mode voltage signal VDIFF is greater than SS_VREF, the switch control signal PGATE after passing through operational amplifier OP1 will decrease. At this time, the transistor (first transistor MP0 or second transistor MP1) of the input power supply voltage VOUT of the control system device 103 will slowly turn on, and the on-resistance of the transistor (first transistor MP0 or second transistor MP1) will decrease accordingly, causing the differential-mode voltage signal VDIFF to gradually decrease. When the differential-mode voltage signal VDIFF decreases to less than the soft-turn-on voltage SS_VREF, the output switch control signal PGATE of operational amplifier OP1 will rise again. At this time, the on-resistance of the transistor (first transistor MP0 or second transistor MP1) of the input power supply voltage VOUT of the control system device 103 will increase, and the differential-mode voltage signal VDIFF will increase. When the differential voltage signal VDIFF is greater than the soft-turn-on voltage SS_VREF, the output switch control signal PGATE of operational amplifier OP1 will decrease again. At this time, the on-resistance of the transistor (first transistor MP0 or second transistor MP1) that controls the input power supply voltage VOUT of the control system device 103 decreases, and the differential voltage signal VDIFF will gradually decrease. The above process is repeated until the soft-turn-on voltage SS_VREF is completely discharged to zero.

[0093] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A soft-start circuit for power switching, comprising a first transistor (MP0) controlling a first power supply (101) to input into a system device (103), a second transistor (MP1) controlling a second power supply (102) to input into the system device (103), and a plug-in / plug-out detection circuit (104), wherein the plug-in / plug-out detection circuit (104) is connected to the first power supply (101) and outputs a plug-in / plug-out status signal (PINOUT) to a control circuit (100), wherein the control circuit (100) controls the operating states of the first transistor (MP0) and the second transistor (MP1) to switch the system device (103) to input either the first power supply (101) or the second power supply (102), characterized in that, The control circuit (100) includes: The system comprises a first soft-turn-on control circuit (10), a second soft-turn-on control circuit (20), and an inverting circuit (30). The first soft-turn-on control circuit (10) is connected to the insertion / removal status signal (PINOUT) via the inverting circuit (30). The input terminal of the first soft-turn-on control circuit (10) is connected to the first power supply (101) and the system device (103). The first soft-turn-on control circuit (10) outputs a first switch control signal (PGATE0) to the first transistor (MP0). The second soft-turn-on control circuit (20) is connected to the insertion / removal status signal (PINOUT). The input terminal of the second soft-turn-on control circuit (20) is connected to the second power supply (102) and the system device (103). The two soft-on control circuits (20) output a second switch control signal (PGATE1) to the second transistor (MP1). When the second switch control signal (PGATE1) turns off the second transistor (MP1), the first switch control signal (PGATE0) turns on the first transistor (MP0) slowly until the input power value of the system device (103) slowly reaches the first power value (101). When the first switch control signal (PGATE0) turns off the first transistor (MP0), the second switch control signal (PGATE1) turns on the second transistor (MP1) slowly until the input power value of the system device (103) slowly reaches the second power value (102).

2. The soft-start circuit for power switching according to claim 1, characterized in that: The source of the first transistor (MP0) is connected to the first power supply (101), and an output capacitor (C0) is provided on the connection path between its drain and the system device (103). Its gate is connected to the first switch control signal (PGATE0).

3. The soft-start circuit for power switching according to claim 1, characterized in that: The drain of the second transistor (MP1) is connected to the second power supply (102), its source is connected to the system device (103), and its gate is connected to the second switch control signal (PGATE1).

4. The soft-start circuit for power switching according to claim 1, characterized in that: The first soft-turn-on control circuit (10) and the second soft-turn-on control circuit (20) have the same circuit structure, including an operational amplifier circuit (21), a differential voltage detection circuit (22), a sampling timing control circuit (23), a soft-turn-on voltage circuit (24), and a first bias current circuit (25). The enable terminal of the operational amplifier circuit (21) is connected to the insertion / removal status signal (PINOUT). The operational amplifier circuit (21) outputs a switch control signal (PGATE), which is either a first switch control signal (PGATE0) or a second switch control signal (PGATE1). The differential voltage detection circuit (22) is connected to the input power supply and the switching power supply of the system device (103). The switching power supply is either a first power supply (101) or a second power supply (102). The differential voltage detection circuit (22) connects the input power supply of the system device (103) to the switching power supply. The voltage difference of the power supply is converted into a differential voltage signal (VDIFF) and output to the second input terminal of the operational amplifier circuit (21). The sampling timing control circuit (23) is connected to the insertion / removal status signal (PINOUT) and outputs a low-level sampling pulse signal (SENCLK) to the soft-turn-on voltage circuit (24) according to the rising edge of the insertion / removal status signal (PINOUT). The soft-turn-on voltage circuit (24) is connected to the differential voltage signal (VDIFF) and samples the maximum value of the differential voltage signal (VDIFF) according to the low-level sampling pulse signal (SENCLK). The soft-turn-on voltage circuit (24) outputs a soft-turn-on voltage (SS_VREF) to the first input terminal of the operational amplifier circuit (21). The first bias current circuit (25) is connected to the first bias current (IB), and its output terminal is connected to the soft-turn-on voltage circuit (24).

5. The soft-start circuit for power switching according to claim 4, characterized in that: The differential pressure detection circuit (22) includes a feedback operation circuit (221), a first current mirror circuit (222), a second current mirror circuit (223), and a second bias current circuit (224). The feedback operation circuit (221) is connected to the input power supply of the system device (103) and the switching power supply. The output terminal of the feedback operation circuit (221) is connected to the input terminal of the first current mirror circuit (222). The output terminal of the first current mirror circuit (222) is connected to the input terminal of the second current mirror circuit (223). Their common terminal is connected to the first potential. The output terminal of the second current mirror circuit (223) outputs the differential voltage signal (VDIFF). Its common terminal is connected to the second potential.

6. The soft-start circuit for power switching according to claim 5, characterized in that: The feedback operation circuit (221) includes an operational amplifier (OP2), a fourth transistor (MN4), and a first resistor (R1). The inverting input of the operational amplifier (OP2) is connected to the input power supply of the system device (103), and its non-inverting input is connected to the switching power supply through the first resistor (R1) and shorted to the drain of the fourth transistor (MN4). The output of the operational amplifier (OP2) is connected to the gate of the fourth transistor (MN4), and the source of the fourth transistor (MN4) is connected to the input of the first current mirror circuit (222).

7. The soft-start circuit for power switching according to claim 4, characterized in that: The sampling timing control circuit (23) includes a delay module (231), a second inverter (INV2), and a second NAND gate (ND2). The delay module (231) is connected to the insertion / removal status signal (PINOUT). The output of the delay module (231) is connected to the first input of the second NAND gate (ND2) through the second inverter (INV2). The second input of the second NAND gate (ND2) is connected to the insertion / removal status signal (PINOUT).

8. The soft-start circuit for power switching according to claim 5, characterized in that: The soft-turn-on voltage circuit (24) includes a second P-type transistor (MP2), a third N-type transistor (MN3), and a bypass capacitor (C1). The gates of the second P-type transistor (MP2) and the third N-type transistor (MN3) are connected to the low-level sampling pulse signal (SENCLK). The source of the second P-type transistor (MP2) is connected to the differential voltage signal (VDIFF). The source of the third N-type transistor (MN3) is connected to the output terminal of the first bias current circuit (25). The drains of the second P-type transistor (MP2) and the third N-type transistor (MN3) are connected to the first potential through the bypass capacitor (C1). The drains of the second P-type transistor (MP2) and the third N-type transistor (MN3) output the soft-turn-on voltage (SS_VREF).

9. The soft-start circuit for power switching according to claim 8, characterized in that: The first bias current circuit (25) includes a third current mirror circuit, which is connected to the first bias current (IB), and its output terminal is connected to the source of the third N-type transistor (MN3), and its common terminal is connected to the first potential.

10. A control method for a soft-start circuit for power switching, characterized in that, An application to a soft-start circuit for power switching as described in any one of claims 1 to 9, comprising: When the insertion / removal detection circuit (104) detects the insertion of the first power supply (101), the insertion / removal status signal (PINOUT) changes from high to low. At this time, the output level of the second soft-turn-on control circuit (20) quickly rises, and the second transistor (MP1) quickly turns off. The insertion / removal status signal (PINOUT) is then input to the first soft-turn-on control circuit (10) after being changed to a high level through the inverting circuit (30). The output level of the first soft-turn-on control circuit (10) slowly decreases, causing the first transistor (MP0) to slowly turn on until the input power value of the system device (103) slowly reaches the value of the first power supply (101). When the insertion / removal detection circuit (104) detects the removal of the first power supply (101), the insertion / removal status signal (PINOUT) changes from high to low. When the plug-in / plug-out status signal (PINOUT) changes from low to high, the plug-in / plug-out status signal (PINOUT) is then input to the first soft-turn-on control circuit (10) after being changed to low level by the inverting circuit (30). The output level of the first soft-turn-on control circuit (10) is quickly pulled up, causing the first transistor (MP0) to be quickly turned off. The output level of the second soft-turn-on control circuit (20) slowly decreases, causing the second transistor (MP1) to be slowly turned on, until the input power value of the system device (103) slowly reaches the value of the second power supply (102), thereby realizing the switching of the system device (103) to the input of the first power supply (101) and the second power supply (102).

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