Slope Compensation Circuit and Related Control Circuit and Method

Abstract

The present disclosure provides a slope compensation circuit, a control circuit and a method. The slope compensation circuit includes a first filter circuit, a second filter circuit, a third filter circuit and a difference amplification circuit. The first filter circuit filters the voltage at the common node of the upper and lower switches of the switching converter to generate a first filtered signal. The second filter circuit filters the first filtered signal to generate a second filtered signal. The third filter circuit filters the second filtered signal to generate a third filtered signal. The difference amplification circuit subtracts the first filtered signal from the second filtered signal and amplifies the difference by k times to generate a slope signal, where the value of k is determined by the value of the third filtered signal. The slope signal generated by the harmonic compensation circuit can change with the change of the output voltage, so that the ratio of the slope signal to the ripple signal of the feedback voltage is constant, and it can ensure that the system can achieve the optimal dynamic response at different output voltages.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and more particularly, to a ramp compensation circuit and related control circuits and methods in a switching converter. Background Art

[0002] With the rapid development of the consumer electronics market, switching converters have also been widely used. At the same time, the requirements for the output voltage range and load transient characteristics are getting higher and higher. It is necessary to achieve a fast dynamic load change response at different output voltages to maintain the stability of the output voltage.

[0003] For example, in a COT control circuit, the external voltage feedback signal and the reference voltage are directly input to a comparator for comparison to control the on and off of the power switch. In this way, the duty cycle of the power switch can be quickly changed during a load jump, so as to achieve a fast load transient response. However, due to the certain delay of the external voltage feedback signal, it has a great impact on the loop stability in a negative feedback system. To ensure the stability of the loop, a virtual current ripple also needs to be added internally in the COT control circuit to compensate the external voltage feedback signal to avoid system oscillation. However, the ripple of the voltage feedback signal changes with the change of the output voltage, and the compensated current ripple is determined by the internal compensation circuit and is difficult to change. This results in a great change in the transient response of the circuit at different output voltages, and it is impossible to achieve the optimal dynamic response function at the same time. Summary of the Invention

[0004] The object of the present invention is to solve the problems existing in the above-mentioned prior art, and a ramp compensation circuit and related control circuits and methods for a switching converter are proposed. The compensation circuit proposed by this disclosure can solve the above-mentioned problems. The ramp signal generated by this ramp compensation circuit can change according to the change of the output voltage. Even at different output voltages, it can ensure that the ratio of the ramp signal to the ripple signal of the feedback voltage is constant to achieve the optimal dynamic response function.

[0005] According to one aspect of the present invention, a ramp compensation circuit for a switching converter is provided. The switching converter has an upper transistor and a lower transistor. The ramp compensation circuit includes: a first filter circuit having an input terminal and an output terminal. The input terminal of the first filter circuit is coupled to the common node of the upper transistor and the lower transistor. The first filter circuit filters the voltage of the common node to generate a first filtered signal at the output terminal of the first filter circuit; a second filter circuit having an input terminal and an output terminal. The input terminal of the second filter circuit receives the first filtered signal. The second filter circuit filters the first filtered signal to generate a second filtered signal at the output terminal of the second filter circuit; a third filter circuit having an input terminal and an output terminal. The input terminal of the third filter circuit receives the second filtered signal. The third filter circuit filters the second filtered signal to generate a third filtered signal at the output terminal of the third filter circuit; and a difference amplifier circuit that receives the first filtered signal, the second filtered signal, and the third filtered signal, subtracts the first filtered signal from the second filtered signal, and amplifies the difference between the first filtered signal and the second filtered signal by k times to generate a ramp signal, where the value of k is determined by the value of the third filtered signal.

[0006] According to another aspect of the present invention, a control circuit for a switching converter is provided. The switching converter includes an upper transistor and a lower transistor, and converts an input voltage into an output voltage by controlling the conduction and cutoff of the upper transistor and the lower transistor. The control circuit includes: the ramp compensation circuit as described above for generating a ramp signal; a comparison circuit having a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparison circuit receives the sum of a voltage feedback signal and the ramp signal. The second input terminal of the comparison circuit receives a reference voltage signal. The comparison circuit compares the sum of the voltage feedback signal and the ramp signal with the reference voltage signal to generate a comparison signal, where the voltage feedback signal represents the output voltage; and a logic circuit that receives the comparison signal and generates a control signal according to the comparison signal to control the upper transistor and the lower transistor of the switching converter.

[0007] According to still another aspect of the present invention, a method for generating a ramp signal for a switching converter is provided. The switching converter has an upper transistor and a lower transistor. The method for generating a ramp signal includes: filtering the voltage on the common node of the upper transistor and the lower transistor to generate a first filtered signal; filtering the first filtered signal to generate a second filtered signal; filtering the second filtered signal to generate a third filtered signal; and amplifying the difference between the first filtered signal and the second filtered signal by k times to generate a ramp signal, where the value of k is determined by the value of the third filtered signal. Description of the Drawings

[0008] Figure 1 The circuit schematic diagram of a switching converter with a ramp compensation circuit according to an embodiment of the present invention is shown;

[0009] Figure 2Circuit schematic diagram of a slope compensation circuit according to an embodiment of the present invention;

[0010] Figure 3 Circuit schematic diagram of a slope compensation circuit according to another embodiment of the present invention;

[0011] Figure 4 Circuit schematic diagram of an error amplifier 1041 according to an embodiment of the present invention;

[0012] Figure 5 Flow schematic diagram of a method for generating a slope signal for a switching converter according to an embodiment of the present invention.

[0013] As shown in the accompanying drawings, in all different views, the same reference numerals refer to the same parts. The accompanying drawings provided here are all for the purpose of illustrating embodiments, principles, concepts, etc., and are not drawn to scale. Detailed implementation manners

[0014] Next, specific embodiments of the present invention will be described non - restrictively with reference to the accompanying drawings. References to "an embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the present invention. Thus, the phrases "in an embodiment" or "in an embodiment" that appear throughout the specification do not necessarily all refer to the same embodiment. The verbs "comprise" and "have" are used herein as open limitations, which neither exclude nor require the existence of unrecited features. Unless otherwise expressly stated, the features recited in the dependent claims can be freely combined with each other. The words "a" or "an" are used throughout the document

[0015] Elements defined by "a" or "an" (i.e., the singular form) do not exclude the possibility of a plurality of such elements. Further, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connected" is used to specify a direct electrical connection between circuit elements, while the term "coupled" is used to specify an electrical connection between circuit elements that may be direct or may be via one or more other elements. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intervening element. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between that node and a reference potential (usually ground). Further, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is considered to refer to the reference potential. The voltage and potential of a given node or given terminal will further be designated by the same reference numeral. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals in the same electronic circuit may be different. In particular, the high and low states of a logic signal may correspond to voltages or currents that may not be completely constant in the high or low state.

[0016] Figure 1 Shown is a circuit schematic of a switching converter having a ramp compensation circuit according to an embodiment of the present invention. In Figure 1 the embodiment shown, the switching converter includes a switch circuit 10, a capacitor Cout, a power transmission voltage feedback circuit 20, and a control circuit. The ramp compensation circuit is included in the control circuit to ensure the stability of the entire switching converter and to achieve an optimal dynamic response function of the switching converter.

[0017] The input terminal of the switch circuit 10 receives an input voltage signal Vin; the output terminal of the switch circuit 10 is coupled to the output terminal of the switching converter. The capacitor Cout is coupled between the output terminal of the switching converter and the reference ground to provide an output voltage signal Vout. In one embodiment, the switch circuit 10 includes at least one controllable switch tube. The switch circuit 10 receives a control signal, and the control signal controls the conduction and off switching of the controllable switch in the switch circuit 10, thereby converting the input voltage signal Vin into the output voltage signal Vout.

[0018] In Figure 1In the illustrated embodiment, the switching circuit 10 is shown as a switching circuit of a BUCK topology. Hereinafter, the circuit principle will be described by taking the BUCK topology as an example. Those of ordinary skill in the art can understand that in other embodiments, the switching circuit 10 can be shown as other suitable isolated or non-isolated topology types, such as BOOST topology, BUCK-BOOST topology, Z-type topology, CUK topology, FLYBACK topology, and so on.

[0019] As Figure 1 shown, the high-side transistor HS and the low-side transistor LS in the BUCK topology are serially coupled between the input terminal of the switching circuit 10 and the reference ground. The common node of the high-side transistor HS and the low-side transistor LS is marked as the switching node SW. The inductor L is coupled between the switching node SW and the output terminal of the switching circuit 10. The control signals include the control signal CTL and the inverted signal of the control signal CTL wherein, the control signal CTL is used to control the on and off switching of the high-side transistor HS, and the inverted signal is used to control the on and off switching of the low-side transistor LS. Those of ordinary skill in the art can understand that the inverted signal of the control signal CTL refers to a signal that is logically complementary to the control signal CTL.

[0020] In Figure 1 the illustrated embodiment, the high-side transistor HS and the low-side transistor LS are shown as N-type metal oxide semiconductor field effect transistors (MOSFETs). Those of ordinary skill in the art can understand that in other embodiments, the high-side transistor HS and the low-side transistor LS can also include other suitable types of semiconductor switching devices, such as junction field effect transistors, insulated gate bipolar transistors, and double-diffused metal oxide semiconductors, etc. In addition, in one embodiment, the low-side transistor LS can also be replaced by a unidirectional conduction diode type.

[0021] In Figure 1 the illustrated embodiment, the output voltage feedback circuit 20 is coupled to the output terminal of the switching converter, and is used to sample the output voltage signal Vout and generate a voltage feedback signal Vfb, where the voltage feedback signal Vfb represents the output voltage signal Vout. In one embodiment, the output voltage feedback circuit 20 includes a voltage divider composed of resistors R1 and R2. In other embodiments, the output voltage feedback circuit 20 can also directly sample the output voltage signal Vout.

[0022] In Figure 1 the illustrated embodiment, the control circuit includes a ramp compensation circuit, a comparison circuit, and a logic circuit.

[0023] The slope compensation circuit is coupled to the switching node SW and generates a ramp signal ramp according to the square-wave voltage signal Vsw at the switching node SW. Specifically, the slope compensation circuit includes a first filter circuit 101, a second filter circuit 102, a third filter circuit 103, and a difference amplifier circuit 104.

[0024] The first filter circuit 101 has an input end and an output end. The input end of the first filter circuit 101 is coupled to the switching node SW. The first filter circuit 101 filters the square-wave voltage signal Vsw at the joint point SW to generate a first filtered signal sig1 at the output end of the first filter circuit 101.

[0025] The second filter circuit 102 has an input end and an output end. The input end of the second filter circuit 102 receives the first filtered signal. The second filter circuit 102 filters the first filtered signal sig1 to generate a second filtered signal sig2 at the output end of the second filter circuit 102.

[0026] The third filter circuit 103 has an input end and an output end. The input end of the third filter circuit 103 receives the second filtered signal sig2. The third filter circuit 103 filters the second filtered signal to generate a third filtered signal Vout_sense at the output end of the third filter circuit 103.

[0027] The difference amplifier circuit 104 receives the first filtered signal sig1, the second filtered signal sig2, and the third filtered signal Vout_sense, subtracts the first filtered signal sig1 from the second filtered signal sig2, and amplifies the difference between the first filtered signal sig1 and the second filtered signal sig2 by k times to generate the ramp signal ramp, where the value of k is determined by the value of the third filtered signal Vout_sense. In one embodiment, the value of k is inversely proportional to the value of the third filtered signal Vout_sense.

[0028] In one embodiment, the slope compensation circuit further includes a voltage division circuit. The square-wave voltage Vsw of the node SW is voltage-divided and then sent to the first filter circuit 101 for filtering. At this time, the first filter circuit 101 filtering the square-wave voltage signal Vsw at the joint point SW includes filtering the voltage-divided signal of the square-wave voltage signal Vsw.

[0029] The ramp signal ramp will be sent to the comparison circuit. In Figure 1In the illustrated embodiment, the comparison circuit receives the voltage feedback signal Vfb and the ramp signal ramp, compares the sum of the voltage feedback signal Vfb and the ramp signal ramp with the voltage reference signal Vref, and generates a comparison signal CA. In one embodiment, the comparison signal CA includes a high-low logic level signal for controlling the conduction time of the controllable switch in the switch circuit 10. For example, in one embodiment, when the comparison signal CA changes from logic low to logic high, the high-side switch HS in the switch circuit 10 conducts, and the low-side switch LS turns off. In other embodiments, the comparison circuit may also superimpose the ramp signal ramp on the voltage reference signal Vref and then compare it with the voltage feedback signal Vfb to generate the comparison signal CA.

[0030] The comparison signal CA will be sent to the logic circuit. According to the control mode selected by the control circuit, the logic circuit will generate a control signal CTL and the inverted signal of the control signal CTL based on the comparison signal CA. For example, in the COT control mode, the logic circuit will also receive a constant on-time control signal and generate a control signal CTL and the inverted signal of the control signal CTL according to the comparison signal CA and the constant on-time control signal. Also, for example, in peak current control, the logic circuit will also receive a logic signal generated according to the current sampling signal and generate a control signal CTL and the inverted signal of the control signal CTL according to the logic signal and the comparison signal CA. In still other embodiments, the logic circuit may also receive a clock signal and generate a control signal CTL and the inverted signal of the control signal CTL according to the clock signal and the comparison signal CA. The embodiments of the present application do not limit the control mode.

[0031] Figure 2 It is the circuit schematic diagram of the ramp compensation circuit according to an embodiment of the present invention. In Figure 2 In the illustrated embodiment, the first filter circuit 101, the second filter circuit 102, and the third filter circuit 103 are all shown as being composed of RC filter circuits. Specifically, the first filter circuit 101 includes a resistor R VIC1 and a capacitor C VIC1 . The resistor R VIC1 and the capacitor C VIC1 are serially coupled between the switch node SW and the reference ground. The common terminal of the resistor R VIC1 and the capacitor C VIC1 is used as the output terminal of the first filter circuit 101. Among them, the voltage at the common terminal of the resistor R VIC1 and the capacitor C VIC1 is the first filter signal sig1. The second filter circuit 102 includes a resistor R VIC2 and a capacitor C VIC2 . The resistor R VIC2and capacitor C VIC2 are serially coupled between the switching node SW and the reference ground, and resistor R VIC2 and capacitor C VIC2 The common terminal of is used as the output terminal of the second filter circuit 102. Among them, resistor R VIC2 and capacitor C VIC2 The voltage of the common terminal of is the second filtered signal sig2. The third filter circuit 103 includes resistor R VIC3 and capacitor C VIC3 . Resistor R VIC3 and capacitor C VIC3 are serially coupled between the switching node SW and the reference ground, and resistor R VIC3 and capacitor C VIC3 The common terminal of is used as the output terminal of the third filter circuit 103. Among them, resistor R VIC3 and capacitor C VIC3 The voltage of the common terminal of is the third filtered signal Vout_sense.

[0032] In Figure 2 In the illustrated embodiment, the difference amplifier circuit 104 is shown to include a subtraction operation unit and an amplitude amplification unit. The subtraction operation unit receives the first filtered signal sig1 and the second filtered signal sig2, and subtracts the first filtered signal sig1 and the second filtered signal sig2 to generate a first ramp signal ramp1. The amplitude amplification unit amplifies the first ramp signal ramp1 by k times according to the value of the third filtered signal Vout_sense. In one embodiment, the value of k is inversely proportional to the value of the third filtered signal Vout_sense.

[0033] In Figure 2 In the illustrated embodiment, at a certain operating frequency f, the ramp signal ramp can be expressed by the following formula (1):

[0034]

[0035] Among them, k is the amplification factor of the amplitude amplification unit. The ripple signal ΔVfb of the feedback voltage Vfb can be expressed by the following formula (2):

[0036]

[0037] Among them, Vref is equal to Vout_steady is the expected steady-state output voltage value of the output voltage Vout. Therefore, the ratio coefficient FA between the ramp signal ramp and the ripple signal ΔVfb of the feedback voltage Vfb can be expressed as:

[0038]

[0039] As can be seen from Equation (3), during the process of the output voltage Vout varying with the load, the designed amplification factor k is inversely proportional to the output voltage Vout. At the same time, by selecting an appropriate value of the amplification factor k, the ratio coefficient FA can be ensured to remain unchanged. That is to say, the amplitude of the compensation ramp signal ramp1 will change with the change of the output voltage Vout, and a constant ratio coefficient FA can be obtained at different output voltages Vout, so as to ensure that the system can achieve the optimal dynamic response at different output voltages Vout.

[0040] Figure 3 FIG. is a circuit schematic diagram of a ramp compensation circuit according to another embodiment of the present invention. In Figure 3 the illustrated embodiment, the first filter circuit 101, the second filter circuit 102, and the third filter circuit 103 are the same as those in Figure 2 the illustrated embodiment, and the difference amplifier circuit 104 is shown as an error amplifier 1041. The error amplifier 1041 has a first input terminal, a second input terminal, a control terminal, and an output terminal. The first input terminal of the error amplifier 1041 receives the first filtered signal sig1; the second input terminal of the error amplifier 1041 receives the second filtered signal sig2; the control terminal of the error amplifier 1041 receives the third filtered signal Vout_sense; the error amplifier 1041 amplifies the difference between the first filtered signal sig1 and the second filtered signal sig2 by k times according to the value of the third filtered signal Vout_sense and generates a ramp signal ramp at the output terminal.

[0041] Figure 4 FIG. is a circuit schematic diagram of the error amplifier 1041 according to an embodiment of the present invention. As shown in the figure, the error amplifier 1041 includes a first differential amplifier circuit, a second differential amplifier circuit, and a current mirror.

[0042] The first differential amplifier circuit receives the third filtered signal Vout_sense, compares the third filtered signal Vout_sense with the internal reference voltage Vbase, and outputs a first current regulation signal ireg1 representing the difference between the third filtered signal Vout_sense and the internal reference voltage Vbase. The current mirror receives the first current regulation signal ireg1 and mirrors the first current regulation signal ireg1 to output a second current regulation signal ireg2. In one embodiment, the first current regulation signal ireg1 and the second current regulation signal ireg2 have a proportional relationship. The second differential amplifier circuit receives the second current regulation signal ireg2, the first filtered signal sig1, and the second filtered signal sig2, compares the first filtered signal sig1 and the second filtered signal sig2 under the control of the second current regulation signal ireg2, and outputs a ramp signal ramp representing the difference between the first filtered signal sig1 and the second filtered signal sig2. The ratio of the difference between the first filtered signal sig1 and the second filtered signal sig2 to the value of the ramp signal ramp is controlled by the second current regulation signal ireg2.

[0043] Figure 5 FIG. is a schematic flowchart of a method for generating a ramp signal for a switching converter according to an embodiment of the present invention. This method for generating a ramp signal can be used in the aforementioned switching converter and other switching converters within the scope of protection of the present invention application. This method for generating a ramp signal includes steps S01-S04.

[0044] Step S01: Filter the voltage Vsw of the switching node SW to generate a first filtered signal sig1.

[0045] Step S02: Filter the first filtered signal sig1 to generate a second filtered signal sig2.

[0046] Step S03: Filter the second filtered signal sig2 to generate a third filtered signal Vout_sense.

[0047] Step S04: Amplify the difference between the first filtered signal sig1 and the second filtered signal sig2 by k times to generate a ramp signal ramp. Wherein, the value of k is determined by the value of the third filtered signal Vout_sense.

[0048] Although the present invention has been described above with reference to several exemplary embodiments, those of ordinary skill in the relevant art should understand that the terms used in the disclosed embodiments of the present invention are illustrative and exemplary, rather than restrictive. They are only used to describe specific embodiments and do not limit the present invention. In addition, without departing from the principles and concepts of the present invention, those of ordinary skill in the art have made various modifications to the disclosed embodiments of the present invention in form and detail without creative efforts, and these modifications all fall within the protection scope defined by the claims of this application or their equivalent scope.

Claims

1. A ramp compensation circuit for a switching converter, the switching converter having an upper transistor and a lower transistor, characterized in that, The ramp compensation circuit includes: A first filter circuit having an input terminal and an output terminal. The input terminal of the first filter circuit is coupled to the common node of the upper transistor and the lower transistor. The first filter circuit filters the voltage on the common node to generate a first filtered signal at the output terminal of the first filter circuit; A second filter circuit having an input terminal and an output terminal. The input terminal of the second filter circuit receives the first filtered signal. The second filter circuit filters the first filtered signal to generate a second filtered signal at the output terminal of the second filter circuit; A third filter circuit having an input terminal and an output terminal. The input terminal of the third filter circuit receives the second filtered signal. The third filter circuit filters the second filtered signal to generate a third filtered signal at the output terminal of the third filter circuit; and A difference amplifier circuit for receiving the first filtered signal, the second filtered signal, and the third filtered signal. The difference amplifier circuit subtracts the first filtered signal from the second filtered signal and amplifies the difference between the first filtered signal and the second filtered signal by k times to generate a ramp signal, where the value of k is determined by the value of the third filtered signal.

2. The ramp compensation circuit according to claim 1, wherein The value of k is inversely proportional to the value of the third filtered signal.

3. The ramp compensation circuit according to claim 1, wherein The first filter circuit includes: A first resistor having a first end and a second end. The first end of the first resistor is coupled to the common node to receive the voltage on the common node; and A first capacitor having a first end and a second end. The first end of the first capacitor is coupled to the second end of the first resistor. The second end of the first capacitor is coupled to the reference ground. The voltage on the first end of the first capacitor is the first filtered signal.

4. The ramp compensation circuit according to claim 3, wherein The second filter circuit includes: A second resistor having a first end and a second end. The first end of the second resistor is coupled to the second end of the first resistor; and A second capacitor having a first end and a second end. The first end of the second capacitor is coupled to the second end of the second resistor. The second end of the second capacitor is coupled to the reference ground. The voltage on the first end of the second capacitor is the second filtered signal.

5. The ramp compensation circuit according to claim 4, wherein The third filter circuit includes: A third resistor having a first end and a second end. The first end of the third resistor is coupled to the second end of the second resistor; and A third capacitor having a first end and a second end. The first end of the third capacitor is coupled to the second end of the third resistor. The second end of the third capacitor is coupled to the reference ground. The voltage on the first end of the third capacitor is the third filtered signal.

6. The ramp compensation circuit according to claim 1, characterized in that, The difference amplifier circuit includes: A subtraction operation unit for receiving the first filtered signal and the second filtered signal and performing a subtraction operation on the first filtered signal and the second filtered signal to generate a first ramp signal; and An amplitude amplification unit for receiving the first ramp signal and the third filtered signal. The third filtered signal controls the amplitude amplification unit to amplify the first ramp signal by k times to generate a ramp signal.

7. The slope compensation circuit according to claim 1, characterized in that, The difference amplifier circuit includes: An error amplifier having a first input terminal, a second input terminal, a control terminal, and an output terminal. The first input terminal of the error amplifier receives a first filtered signal, the second input terminal of the error amplifier receives a second filtered signal, the control terminal of the error amplifier receives a third filtered signal, the error amplifier compares the first filtered signal and the second filtered signal, amplifies the difference between the first filtered signal and the second filtered signal, and generates a ramp signal at the output terminal.

8. The slope compensation circuit according to claim 7, wherein The error amplifier includes: A first differential amplifier circuit that receives the third filtered signal and a reference voltage signal, and compares the third filtered signal and the reference voltage signal to generate a first current regulation signal, wherein the current regulation signal represents the difference between the third filtered signal and the reference voltage signal; A current mirror that mirrors the first current regulation signal into a second current regulation signal; and A second differential amplifier circuit that receives the first filtered signal, the second filtered signal, and the second current regulation signal, and generates a ramp signal based on the first filtered signal, the second filtered signal, and the second current regulation signal.

9. A control circuit for a switching converter, the switching converter including an upper transistor and a lower transistor, the control circuit converting an input voltage into an output voltage by controlling the conduction and cutoff of the upper transistor and the lower transistor, characterized in that, The control circuit includes: A ramp compensation circuit as described in any one of claims 1 to 8 for generating a ramp signal; A comparison circuit having a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparison circuit receives the sum of the voltage feedback signal and the ramp signal, the second input terminal of the comparison circuit receives a reference voltage signal, and the comparison circuit compares the sum of the voltage feedback signal and the ramp signal with the reference voltage signal to generate a comparison signal, wherein the voltage feedback signal represents the output voltage; and A logic circuit that receives the comparison signal and generates a control signal based on the comparison signal to control the conduction and cutoff of the upper transistor and the lower transistor.

10. A ramp signal generation method for a switching converter, the switching converter having an upper transistor and a lower transistor, characterized in that, The method for generating the ramp signal includes: Filtering the voltage at the common node of the upper transistor and the lower transistor to generate a first filtered signal; Filtering the first filtered signal to generate a second filtered signal; Filtering the second filtered signal to generate a third filtered signal; and Amplifying the difference between the first filtered signal and the second filtered signal by k times to generate a ramp signal, wherein the value of k is determined by the value of the third filtered signal.

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