A radio frequency switch and its control method

Abstract

The present application discloses a radio frequency switch and its control method. The radio frequency switch includes: a receiving branch and a transmitting branch; the receiving branch includes: a first series branch and a first parallel branch; the transmitting branch includes: a second series branch and a second parallel branch; the first series branch, the first parallel branch, the second series branch, and the second parallel branch are arranged in an asymmetric series-parallel structure. The method includes: using a positive voltage to control the conduction states of the first series branch, the first parallel branch, the second series branch, and the second parallel branch, so as to control the radio frequency switch to switch between a receiving mode and a transmitting mode. By using the asymmetric series-parallel structure, the performance of the transmitter part in the millimeter-wave phased array transceiver is greatly optimized, the linearity of the transmitter is improved, and at the same time, a lower insertion loss and better isolation can be achieved. By controlling the radio frequency switch with a positive voltage, an additional negative voltage generation circuit is not required, thereby saving circuit area.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and particularly to a radio frequency switch and its control method. Background Art

[0002] With the rapid development of current wireless communication technology, people are exploring more deeply in fields such as radar detection, aerospace, 5G / 6G / satellite communication, etc. Traditional mechanical scanning radars can no longer meet the needs of society. Phased array technology is a new type of active scanning method. By controlling the phase and amplitude of each unit of the antenna, spatial beams in different directions can be formed. Currently, phased array technology has been widely applied in many aspects such as radars and 5G / 6G communications.

[0003] Radio frequency switches can achieve the switching of phased array transceiver states in phased array technology, ensuring the core functions of phased arrays, and have an important position in radio frequency / microwave communication systems. With the large-scale application of 5G millimeter waves, higher requirements are placed on the linearity of the transmitter part of the radio frequency switch in millimeter wave phased array transceivers.

[0004] Therefore, how to improve the linearity of the transmitter part of the radio frequency switch in a millimeter wave phased array transceiver has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] Based on the above problems, this application provides a radio frequency switch and its control method.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] In a first aspect, an embodiment of this application provides a radio frequency switch, which includes:

[0008] A receiving branch and a transmitting branch;

[0009] The receiving branch includes: a first series branch and a first parallel branch;

[0010] The transmitting branch includes: a second series branch and a second parallel branch;

[0011] The first series branch, the first parallel branch, the second series branch and the second parallel branch are arranged in an asymmetric series-parallel structure.

[0012] Optionally, the receiving branch and the transmitting branch include:

[0013] Multiple PMOS transistors, and the gates and drains of the multiple PMOS transistors are connected to each other.

[0014] Optionally, the receiving branch and the transmitting branch include:

[0015] Multiple NMOS transistors, with a resistor connected in series between the source and drain of each of the multiple NMOS transistors.

[0016] Optionally, the first series branch includes:

[0017] A first feedback capacitor;

[0018] The second series branch includes:

[0019] A second feedback capacitor.

[0020] Optionally, the RF switch uses a transmission line for input and / or output matching.

[0021] Optionally, the first series branch includes:

[0022] A first DC-blocking capacitor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a second DC-blocking capacitor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first feedback capacitor, a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, a fourth voltage-dividing resistor, a fifth voltage-dividing resistor, a first biasing resistor, a second biasing resistor, a third biasing resistor, and a fourth biasing resistor;

[0023] One end of the first DC-blocking capacitor is connected to the antenna terminal through a first transmission line, and the other end of the first DC-blocking capacitor is connected to the source of the first NMOS transistor;

[0024] The drain of the first NMOS transistor is connected to the source of the second NMOS transistor;

[0025] The drain of the second NMOS transistor is connected to the source of the third NMOS transistor;

[0026] The drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor;

[0027] One end of the second DC-blocking capacitor is connected to the drain of the fourth NMOS transistor through a second transmission line, and the other end of the second DC-blocking capacitor is connected to the receiver;

[0028] The gate and drain of the first PMOS transistor are connected to the gate of the first NMOS transistor, and the source of the first PMOS transistor is connected to the body terminal of the first NMOS transistor;

[0029] The gate and drain of the second PMOS transistor are connected to the gate of the second NMOS transistor, and the source of the second PMOS transistor is connected to the body terminal of the second NMOS transistor;

[0030] The gate and drain of the third PMOS transistor are connected to the gate of the third NMOS transistor, and the source of the third PMOS transistor is connected to the body terminal of the third NMOS transistor;

[0031] The gate and drain of the fourth PMOS transistor are connected to the gate of the fourth NMOS transistor, and the source of the fourth PMOS transistor is connected to the body terminal of the fourth NMOS transistor;

[0032] One end of the first feedback capacitor is connected to the source terminal of the first NMOS transistor, and the other end of the first feedback capacitor is connected to the first signal control terminal through the first voltage-dividing resistor, the second voltage-dividing resistor, the third voltage-dividing resistor, the fourth voltage-dividing resistor, and the fifth voltage-dividing resistor connected in series;

[0033] Both ends of the second voltage-dividing resistor are respectively connected to the source and drain of the second NMOS transistor;

[0034] Both ends of the third voltage-dividing resistor are respectively connected to the source and drain of the third NMOS transistor;

[0035] Both ends of the fourth voltage-dividing resistor are respectively connected to the source and drain of the fourth NMOS transistor;

[0036] One end of the first bias resistor is connected to the gate of the first NMOS transistor, and the other end of the first bias resistor is connected to the second signal control terminal;

[0037] One end of the second bias resistor is connected to the gate of the second NMOS transistor, and the other end of the second bias resistor is connected to the second signal control terminal;

[0038] One end of the third bias resistor is connected to the gate of the third NMOS transistor, and the other end of the third bias resistor is connected to the second signal control terminal;

[0039] One end of the fourth bias resistor is connected to the gate of the fourth NMOS transistor, and the other end of the fourth bias resistor is connected to the second signal control terminal.

[0040] Optionally, the first parallel branch includes:

[0041] A third DC-blocking capacitor, a fifth NMOS transistor, a sixth NMOS transistor, a fourth DC-blocking capacitor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth bias resistor, a sixth bias resistor, a sixth voltage-dividing resistor, a seventh voltage-dividing resistor, and an eighth voltage-dividing resistor;

[0042] The source of the fifth NMOS transistor is connected to the third DC-blocking capacitor;

[0043] The drain of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor;

[0044] The drain of the sixth NMOS transistor is grounded through the fourth DC blocking capacitor;

[0045] The gate and drain of the fifth PMOS transistor are connected to the gate of the fifth NMOS transistor, and the source of the fifth PMOS transistor is connected to the body terminal of the fifth NMOS transistor;

[0046] The gate and drain of the sixth PMOS transistor are connected to the gate of the sixth NMOS transistor, and the source of the sixth PMOS transistor is connected to the body terminal of the sixth NMOS transistor;

[0047] One end of the fifth bias resistor is connected to the gate of the fifth NMOS transistor, and the other end of the fifth bias resistor is connected to the first signal control terminal;

[0048] One end of the sixth bias resistor is connected to the gate of the sixth NMOS transistor, and the other end of the sixth bias resistor is connected to the first signal control terminal;

[0049] Both ends of the sixth voltage dividing resistor are respectively connected to the source and drain of the fifth NMOS transistor;

[0050] Both ends of the seventh voltage dividing resistor are respectively connected to the source and drain of the sixth NMOS transistor;

[0051] One end of the eighth voltage dividing resistor is connected to the seventh voltage dividing resistor, and the other end of the eighth voltage dividing resistor is connected to the second signal control terminal.

[0052] Optionally, the second series branch includes:

[0053] A fifth DC blocking capacitor, a seventh NMOS transistor, an eighth NMOS transistor, a sixth DC blocking capacitor, a seventh PMOS transistor, an eighth PMOS transistor, a seventh bias resistor, an eighth bias resistor, a second feedback capacitor, a ninth voltage dividing resistor, a tenth voltage dividing resistor, and an eleventh voltage dividing resistor;

[0054] One end of the fifth DC blocking capacitor is connected to the antenna terminal through a first transmission line, and the other end of the fifth DC blocking capacitor is connected to the drain of the seventh NMOS transistor;

[0055] The source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor;

[0056] The sixth DC blocking capacitor is connected to the source of the eighth NMOS transistor through a third transmission line, and the other end of the sixth DC blocking capacitor is connected to the transmitter;

[0057] The gate and drain of the seventh PMOS transistor are connected to the gate of the seventh NMOS transistor, and the source of the seventh PMOS transistor is connected to the body terminal of the seventh NMOS transistor;

[0058] The gate and drain of the eighth PMOS transistor are connected to the gate of the eighth NMOS transistor, and the source of the eighth PMOS transistor is connected to the body terminal of the eighth NMOS transistor;

[0059] One end of the seventh bias resistor is connected to the gate of the seventh NMOS transistor, and the other end of the seventh bias resistor is connected to the first signal control terminal;

[0060] One end of the eighth bias resistor is connected to the gate of the eighth NMOS transistor, and the other end of the eighth bias resistor is connected to the first signal control terminal;

[0061] One end of the second feedback capacitor is connected to the source terminal of the seventh bias resistor, and the other end of the second feedback capacitor is connected to the second signal control terminal through the ninth voltage-dividing resistor, the tenth voltage-dividing resistor, and the eleventh voltage-dividing resistor connected in series;

[0062] Both ends of the tenth voltage-dividing resistor are respectively connected to the source and drain of the eighth NMOS transistor.

[0063] Optionally, the second parallel branch includes:

[0064] A seventh DC-blocking capacitor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, an eighth DC-blocking capacitor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a ninth bias resistor, a tenth bias resistor, an eleventh bias resistor, a twelfth bias resistor, a twelfth voltage-dividing resistor, a thirteenth voltage-dividing resistor, a fourteenth voltage-dividing resistor, a fifteenth voltage-dividing resistor, and a sixteenth voltage-dividing resistor;

[0065] The drain of the ninth NMOS transistor is connected to the seventh DC-blocking capacitor;

[0066] The source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor;

[0067] The source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor;

[0068] The source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor;

[0069] The source of the twelfth NMOS transistor is grounded through the eighth DC-blocking capacitor;

[0070] The gate and drain of the ninth PMOS transistor are connected to the gate of the ninth NMOS transistor, and the source of the ninth PMOS transistor is connected to the body terminal of the ninth NMOS transistor;

[0071] The gate and drain of the tenth PMOS transistor are connected to the gate of the tenth NMOS transistor, and the source of the tenth PMOS transistor is connected to the body terminal of the tenth NMOS transistor;

[0072] The gate and drain of the eleventh PMOS transistor are connected to the gate of the eleventh NMOS transistor, and the source of the eleventh PMOS transistor is connected to the body terminal of the eleventh NMOS transistor;

[0073] The gate and drain of the twelfth PMOS transistor are connected to the gate of the twelfth NMOS transistor, and the source of the twelfth PMOS transistor is connected to the body terminal of the twelfth NMOS transistor;

[0074] The drain of the ninth NMOS transistor is connected to the first signal control terminal through the twelfth voltage dividing resistor, the thirteenth voltage dividing resistor, the fourteenth voltage dividing resistor, the fifteenth voltage dividing resistor, and the sixteenth voltage dividing resistor connected in series;

[0075] Both ends of the twelfth voltage dividing resistor are respectively connected to the source and drain of the ninth NMOS transistor;

[0076] Both ends of the thirteenth voltage dividing resistor are respectively connected to the source and drain of the tenth NMOS transistor;

[0077] Both ends of the fourteenth voltage dividing resistor are respectively connected to the source and drain of the eleventh NMOS transistor;

[0078] Both ends of the fifteenth voltage dividing resistor are respectively connected to the source and drain of the twelfth NMOS transistor;

[0079] One end of the ninth bias resistor is connected to the gate of the ninth NMOS transistor, and the other end of the ninth bias resistor is connected to the second signal control terminal;

[0080] One end of the tenth bias resistor is connected to the gate of the tenth NMOS transistor, and the other end of the tenth bias resistor is connected to the second signal control terminal;

[0081] One end of the eleventh bias resistor is connected to the gate of the eleventh NMOS transistor, and the other end of the eleventh bias resistor is connected to the second signal control terminal;

[0082] One end of the twelfth bias resistor is connected to the gate of the twelfth NMOS transistor, and the other end of the twelfth bias resistor is connected to the second signal control terminal.

[0083] Second aspect, embodiments of the present application provide a method for controlling a radio frequency switch, characterized in that it is used to control any of the above-mentioned radio frequency switches, and the method includes:

[0084] Using pure positive pressure to control the conduction states of the first series branch, the first parallel branch, the second series branch, and the second parallel branch, so as to control the radio frequency switch to switch between the receiving mode and the transmitting mode.

[0085] Compared with the prior art, the present application has the following beneficial effects:

[0086] A radio frequency switch and its control method provided by an embodiment of the present application, the radio frequency switch includes: a receiving branch and a transmitting branch; the receiving branch includes: a first series branch and a first parallel branch; the transmitting branch includes: a second series branch and a second parallel branch; the first series branch, the first parallel branch, the second series branch, and the second parallel branch are arranged in an asymmetric series-parallel structure. The radio frequency switch control method includes: using pure positive pressure to control the conduction states of the first series branch, the first parallel branch, the second series branch, and the second parallel branch, so as to control the radio frequency switch to switch between the receiving mode and the transmitting mode. The radio frequency switch provided by the embodiment of the present application, by using an asymmetric series-parallel structure, greatly optimizes the performance of the transmitter part in a millimeter-wave phased array transceiver, improves the linearity of the transmitter, and at the same time can achieve low insertion loss and good isolation. The radio frequency switch control method provided by the embodiment of the present application controls the radio frequency switch through pure positive pressure, and does not require an additional negative pressure generation circuit in the phased array transceiver, thereby saving circuit area. Description of the Drawings

[0087] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0088] Figure 1 It is a schematic structural diagram of a radio frequency switch provided by an embodiment of the present application;

[0089] Figure 2 It is a schematic circuit structure diagram of a first series branch in a radio frequency switch provided by an embodiment of the present application;

[0090] Figure 3 It is a schematic circuit structure diagram of a first parallel branch in a radio frequency switch provided by an embodiment of the present application;

[0091] Figure 4Schematic diagram of the circuit structure of the second series branch in a radio frequency switch provided by an embodiment of the present application;

[0092] Figure 5 Schematic diagram of the circuit structure of the second parallel branch in a radio frequency switch provided by an embodiment of the present application;

[0093] Figure 6 Schematic diagram of the circuit structure of a radio frequency switch provided by an embodiment of the present application. Detailed implementation manners

[0094] As described above, currently, there are higher requirements for the linearity of the transmitter part of the radio frequency switch in the millimeter-wave phased array transceiver.

[0095] The inventors of the present application found through research that currently, the radio frequency switches applied in millimeter-wave phased array transceivers mostly adopt symmetric structures. At this time, if the high linearity requirements of the transmitter (TX) part are to be met, many transistors can be stacked in its series branch, but this will make the insertion loss and isolation of the TX part worse. Therefore, the inventors invented a radio frequency switch and its control method through research, which can achieve high linearity of the transmitter part of the radio frequency switch in the millimeter-wave phased array transceiver, while realizing low insertion loss and good isolation at the same time.

[0096] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0097] Example 1

[0098] Refer to Figure 1 , which is a schematic diagram of the structure of a radio frequency switch provided by an embodiment of the present application, including:

[0099] A first series branch 111, a first parallel branch 112, a second series branch 121, and a second parallel branch 122; the first series branch 111 and the first parallel branch 112 form a receiving branch 11, and the second series branch 121 and the second parallel branch 122 form a transmitting branch 12; the receiving branch is used to receive signals through an antenna and transmit the signals through a receiver (Receiver, abbreviated as RX); the transmitting branch is used to transmit signals to the antenna through a transmitter (Transmitter, abbreviated as TX) and the antenna transmits the signals.

[0100] It should be noted that the first series branch 111, the first parallel branch 112, the second series branch 121, and the second parallel branch 122 are arranged in an asymmetric series-parallel structure. That is to say, the circuit structures of the first series branch and the second series branch are different, and the circuit structures of the first parallel branch and the second parallel branch are different. Such an asymmetric series-parallel structure greatly optimizes the performance of the TX part of the millimeter-wave phased array transceiver, significantly improves the TX linearity, and at the same time can achieve extremely low insertion loss and good isolation.

[0101] It should be noted that in the embodiments provided in the present application, the first series branch 111, the first parallel branch 112, the second series branch 121, and the second parallel branch 122 may include multiple PMOS transistors with their own gates and drains connected. Specifically, they may be FB (Floating Body)-PMOS bias transistors. The PMOS transistors with their own gates and drains connected can form a diode form, which can reduce the insertion loss of the RF switch.

[0102] It should be noted that in the embodiments provided in the present application, the first series branch 111, the first parallel branch 112, the second series branch 121, and the second parallel branch 122 may include multiple NMOS transistors with a resistor connected in series between their own sources and drains. Specifically, they may be BC (Body Contact)-NMOS switch transistors. The resistor connected in series between the source and the drain can be a resistor with a relatively large resistance value, which can make the source-drain voltage of the MOS transistor in the off state evenly distributed.

[0103] It should be noted that in the embodiments provided in the present application, in the first series branch 111 and the second series branch 121, a feedback capacitor may be included respectively. The introduction of the feedback capacitor can improve both the insertion loss and the isolation of the switch.

[0104] It should be noted that in the embodiments provided in the present application, the RF switch can use a transmission line for input and / or output matching, which is convenient to match the input or output impedance to 50 ohms in the millimeter-wave band, so as to achieve a lower return loss and a lower insertion loss.

[0105] In the embodiments provided in the present application, the first series branch 111 may include two DC-blocking capacitors, four NMOS transistors, four PMOS transistors, one feedback capacitor, five voltage-dividing resistors, and four bias resistors. The specific connection method can be seen in Figure 2, This figure is a schematic circuit diagram of the first series branch in a radio frequency switch provided by an embodiment of the present application, including: a first DC blocking capacitor C10, a first NMOS transistor N211, a second NMOS transistor N212, a third NMOS transistor N213, a fourth NMOS transistor N214, a second DC blocking capacitor C3, a first PMOS transistor P211, a second PMOS transistor P212, a third PMOS transistor P213, a fourth PMOS transistor P214, a first feedback capacitor C5, a first voltage dividing resistor R211, a second voltage dividing resistor R212, a third voltage dividing resistor R213, a fourth voltage dividing resistor R214, a fifth voltage dividing resistor R215, a first bias resistor Rg211, a second bias resistor Rg212, a third bias resistor Rg213, and a fourth bias resistor Rg214.

[0106] Specifically, first connect the DC blocking capacitor C10 and then connect it to the source and drain of N211, N212, N213, and N214 in sequence, and then connect it to the transmission line T3 and the DC blocking capacitor C3 to connect to RX; P211, P212, P213, and P214 are connected to form a diode form by connecting their respective gates and drains, and then connected to the gates of N211, N212, N213, and N214, and then connected to the bias resistors Rg211, Rg212, Rg213, and Rg214 and then connected together to connect to the second signal control terminal V2. The sources of P211, P212, P213, and P214 are respectively connected to the body terminals of N211, N212, N213, and N214. The source of N211 is first connected to the feedback capacitor C5 and then connected to the voltage dividing resistor R211. The sources and drains of N212, N213, and N214 are respectively connected to the voltage dividing resistors R212, R213, and R214. The other side of the resistor R214 is connected to R215 and the first signal control terminal V1.

[0107] In the embodiment provided by the present application, the first parallel branch 112 may include two DC blocking capacitors, two NMOS transistors, two PMOS transistors, two bias resistors, and three voltage dividing resistors. The specific connection method can be referred to Figure 3 , This figure is a schematic circuit diagram of the first parallel branch in a radio frequency switch provided by an embodiment of the present application, including: a third DC blocking capacitor C7, a fifth NMOS transistor N221, a sixth NMOS transistor N 222, a fourth DC blocking capacitor C8, a fifth PMOS transistor P221, a sixth PMOS transistor P222, a fifth bias resistor Rg221, a sixth bias resistor Rg222, a sixth voltage dividing resistor R221, a seventh voltage dividing resistor R222, and an eighth voltage dividing resistor R223.

[0108] Specifically, the DC-blocking capacitor C7 can be connected first, the source and drain of N221 and N222 are connected in sequence, and then connected to the DC-blocking capacitor C8 to the ground. P221 and P222 are connected in the form of diodes with their respective gates and drains, then connected to the gates of N221 and N222, then connected to the bias resistors Rg221 and Rg222 and then connected together to the first signal control terminal V1. The sources of P221 and P222 are respectively connected to the body terminals of N221 and N222. The source and drain of N221 and N222 are respectively connected with voltage-dividing resistors R221 and R222, and the other side of the resistor R222 is connected to R223 and the signal control terminal V2.

[0109] In the embodiment provided by the present application, the second series branch 121 may include two DC-blocking capacitors, two NMOS transistors, two PMOS transistors, two bias resistors, one feedback capacitor, and three voltage-dividing resistors. The specific connection method can be seen in Figure 4 , which is a schematic diagram of the circuit structure of the second series branch in a radio frequency switch provided by an embodiment of the present application, including: the fifth DC-blocking capacitor C1, the seventh NMOS transistor N111, the eighth NMOS transistor N112, the sixth DC-blocking capacitor C2, the seventh PMOS transistor P111, the eighth PMOS transistor P112, the seventh bias resistor Rg111, the eighth bias resistor Rg112, the second feedback capacitor C4, the ninth voltage-dividing resistor R111, the tenth voltage-dividing resistor R112, and the eleventh voltage-dividing resistor R112.

[0110] Specifically, the DC-blocking capacitor C1 can be connected first, and then connected to the sources and drains of N111 and N112 in sequence, and then connected to the transmission line T2 and the DC-blocking capacitor C2 connected to TX. P111 and P112 are connected in the form of diodes with their respective gates and drains, then connected to the gates of N111 and N112, then connected to the bias resistors Rg111 and Rg112 and then connected together to the first signal control terminal V1. The sources of P111 and P112 are respectively connected to the body terminals of N111 and N112. The source of N111 is first connected with the feedback capacitor C4 and then with the voltage-dividing resistor R111. The source and drain of N112 are connected with the voltage-dividing resistor R112, and the other side of the resistor R112 is connected to R113 and the second signal control terminal V2.

[0111] In the embodiment provided by the present application, the second parallel branch 122 may include two DC-blocking capacitors, four NMOS transistors, four PMOS transistors, four bias resistors, and five voltage-dividing resistors. The specific connection method can be seen in Figure 5, This figure is a schematic circuit diagram of the second parallel branch in a radio frequency switch provided by an embodiment of the present application, including: the seventh DC-blocking capacitor C6, the ninth NMOS transistor N121, the tenth NMOS transistor N122, the eleventh NMOS transistor N123, the twelfth NMOS transistor N124, the eighth DC-blocking capacitor C9, the ninth PMOS transistor P121, the tenth PMOS transistor P122, the eleventh PMOS transistor P123, the twelfth PMOS transistor P124, the ninth bias resistor Rg121, the tenth bias resistor Rg122, the eleventh bias resistor Rg123, the twelfth bias resistor Rg124, the twelfth voltage-dividing resistor R121, the thirteenth voltage-dividing resistor R122, the fourteenth voltage-dividing resistor R123, the fifteenth voltage-dividing resistor R124, and the sixteenth voltage-dividing resistor R125.

[0112] Specifically, the DC-blocking capacitor C6 can be connected first, and the sources and drains of N121, N122, N123, and N124 are connected in sequence and then connected to the DC-blocking capacitor C9 to ground. P121, P122, P123, and P124 are connected with their gates and drains in the form of diodes, then connected to the gates of N121, N122, N123, and N124, then connected to the bias resistors Rg221, Rg222, Rg123, and Rg124 and then connected together to the second signal control terminal V2. The sources of P121, P122, P123, and P124 are respectively connected to the body terminals of N121, N122, N123, and N124. The source-drain poles of N121, N122, N123, and N124 are respectively connected with the voltage-dividing resistors R121, R122, R123, and R124, and the other side of the resistor R124 is connected to R125 and the first signal control terminal V1.

[0113] It should be noted that in the embodiment provided by the present application, as an example, the overall circuit structure of the radio frequency switch can be referred to Figure 6 , This figure is a schematic circuit diagram of a radio frequency switch provided by an embodiment of the present application, including two radio frequency signal paths, namely the receiving branch from the antenna to the RX and the transmitting branch from the TX to the antenna. Each branch includes series and parallel branches.

[0114] The radio frequency switch provided by the embodiment of the present application greatly optimizes the performance of the transmitter part in the millimeter-wave phased array transceiver by using an asymmetric series-parallel structure, improves the linearity of the transmitter, and at the same time can achieve low insertion loss and good isolation.

[0115] Example 2

[0116] The embodiment of the present application further provides a radio frequency (RF) switch control method for controlling any RF switch in the above embodiments. The method includes: controlling the conduction states of the first series branch, the first parallel branch, the second series branch, and the second parallel branch by using pure positive pressure, so as to control the switching of the RF switch between the receiving mode and the transmitting mode.

[0117] Specifically, reference can be made to Figure 6 , which is a schematic diagram of the RF switch circuit structure provided by the embodiment of the present application. When the first signal control terminal V1 remains at a high level, such as 1.5V, and the second signal control terminal V2 remains at a low level, such as 0V, the TX branch is turned on, and the NMOS transistors N111 and N112 are turned on. The millimeter-wave signal is transmitted from the TX branch and transmitted out from the antenna port. When the second signal control terminal V2 remains at a high level, such as 1.5V, and the first signal control terminal V1 remains at a low level, such as 0V, the RX branch is turned on, and the NMOS transistors N211, N212, N213, and N214 are turned on. The millimeter-wave signal is transmitted from the antenna port and transmitted out from the RX port.

[0118] The RF switch control method provided by the embodiment of the present application controls the RF switch by using pure positive pressure, and no additional negative pressure generation circuit is required in the phased array transceiver, thereby saving the circuit area.

[0119] It should be noted that each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key points of each embodiment are the differences from other embodiments. Those of ordinary skill in the art can understand and implement without creative efforts.

[0120] As mentioned above, it is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any change or replacement that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A radio frequency switch, characterized in that: The radio frequency switch comprises: receiving branch and transmitting branch; The receiving branch includes: a first series branch and a first parallel branch; The transmitting branch includes: a second series branch and a second parallel branch; The first series branch, the first parallel branch, the second series branch and the second parallel branch are arranged in an asymmetric series-parallel structure; The first series branch comprises: a first DC blocking capacitor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a second DC blocking capacitor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first feedback capacitor, a first voltage dividing resistor, a second voltage dividing resistor, a third voltage dividing resistor, a fourth voltage dividing resistor, a fifth voltage dividing resistor, a first bias resistor, a second bias resistor, a third bias resistor, and a fourth bias resistor; One end of the first DC blocking capacitor is connected to the antenna end through a first transmission line, and the other end of the first DC blocking capacitor is connected to the source of the first NMOS transistor; The drain of the first NMOS transistor is connected to the source of the second NMOS transistor; The drain of the second NMOS transistor is connected to the source of the third NMOS transistor; The drain of the third NMOS tube is connected to the source of the fourth NMOS tube; One end of the second DC blocking capacitor is connected to the drain of the fourth NMOS transistor through a second transmission line, and the other end of the second DC blocking capacitor is connected to a receiver; The gate and drain of the first PMOS transistor are connected to the gate of the first NMOS transistor, and the source of the first PMOS transistor is connected to the body of the first NMOS transistor; The gate and drain of the second PMOS transistor are connected to the gate of the second NMOS transistor, and the source of the second PMOS transistor is connected to the body of the second NMOS transistor; The gate and drain of the third PMOS transistor are connected to the gate of the third NMOS transistor, and the source of the third PMOS transistor is connected to the body of the third NMOS transistor; The gate and drain of the fourth PMOS transistor are connected to the gate of the fourth NMOS transistor, and the source of the fourth PMOS transistor is connected to the body of the fourth NMOS transistor; One end of the first feedback capacitor is connected to the source end of the first NMOS transistor, and the other end of the first feedback capacitor is connected in series to the first signal control end through a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, a fourth voltage-dividing resistor, and a fifth voltage-dividing resistor; Two ends of the second voltage-dividing resistor are respectively connected to the source and drain of the second NMOS transistor; Two ends of the third voltage-dividing resistor are respectively connected to the source and drain of the third NMOS transistor; Two ends of the fourth voltage-dividing resistor are respectively connected to the source and drain of the fourth NMOS transistor; One end of the first bias resistor is connected to the gate of the first NMOS transistor, and the other end of the first bias resistor is connected to the second signal control end; One end of the second bias resistor is connected to the gate of the second NMOS transistor, and the other end of the second bias resistor is connected to the second signal control terminal; One end of the third bias resistor is connected to the gate of the third NMOS transistor, and the other end of the third bias resistor is connected to the second signal control terminal; One end of the fourth bias resistor is connected to the gate of the fourth NMOS transistor, and the other end of the fourth bias resistor is connected to the second signal control end.

2. The radio frequency switch according to claim 1, wherein: The receiving branch and the transmitting branch include: A plurality of PMOS tubes, wherein the gates and drains of the plurality of PMOS tubes are connected.

3. The radio frequency switch according to claim 1, wherein: The receiving branch and the transmitting branch include: A plurality of NMOS transistors are provided, wherein a resistor is connected in series between the source and the drain of the plurality of NMOS transistors.

4. The radio frequency switch according to claim 1, wherein: The first series branch comprises: a first feedback capacitor; The second series branch comprises: The second feedback capacitor.

5. The radio frequency switch according to claim 1, wherein: The radio frequency switch uses a transmission line for input and / or output matching.

6. The radio frequency switch according to claim 1, characterized in that: The first parallel branch comprises: a third DC blocking capacitor, a fifth NMOS transistor, a sixth NMOS transistor, a fourth DC blocking capacitor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth bias resistor, a sixth bias resistor, a sixth voltage-dividing resistor, a seventh voltage-dividing resistor, and an eighth voltage-dividing resistor; The source of the fifth NMOS tube is connected to the third DC blocking capacitor; The drain of the fifth NMOS transistor is connected to the source of the sixth NMOS transistor; The drain of the sixth NMOS transistor is grounded through the fourth DC blocking capacitor; The gate and drain of the fifth PMOS transistor are connected to the gate of the fifth NMOS transistor, and the source of the fifth PMOS transistor is connected to the body of the fifth NMOS transistor; The gate and drain of the sixth PMOS transistor are connected to the gate of the sixth NMOS transistor, and the source of the sixth PMOS transistor is connected to the body of the sixth NMOS transistor; One end of the fifth bias resistor is connected to the gate of the fifth NMOS transistor, and the other end of the fifth bias resistor is connected to the first signal control terminal; One end of the sixth bias resistor is connected to the gate of the sixth NMOS transistor, and the other end of the sixth bias resistor is connected to the first signal control terminal; Two ends of the sixth voltage-dividing resistor are respectively connected to the source and drain of the fifth NMOS transistor; Two ends of the seventh voltage-dividing resistor are respectively connected to the source and drain of the sixth NMOS transistor; One end of the eighth voltage-dividing resistor is connected to the seventh voltage-dividing resistor, and the other end of the eighth voltage-dividing resistor is connected to the second signal control end.

7. The radio frequency switch according to claim 1, wherein: The second series branch comprises: a fifth DC blocking capacitor, a seventh NMOS transistor, an eighth NMOS transistor, a sixth DC blocking capacitor, a seventh PMOS transistor, an eighth PMOS transistor, a seventh bias resistor, an eighth bias resistor, a second feedback capacitor, a ninth voltage-dividing resistor, a tenth voltage-dividing resistor, and an eleventh voltage-dividing resistor; One end of the fifth DC blocking capacitor is connected to the antenna terminal through the first transmission line, and the other end of the fifth DC blocking capacitor is connected to the drain of the seventh NMOS transistor; The source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor; The sixth DC blocking capacitor is connected to the source of the eighth NMOS transistor through a third transmission line, and the other end of the sixth DC blocking capacitor is connected to the transmitter; The gate and drain of the seventh PMOS transistor are connected to the gate of the seventh NMOS transistor, and the source of the seventh PMOS transistor is connected to the body of the seventh NMOS transistor; The gate and drain of the eighth PMOS transistor are connected to the gate of the eighth NMOS transistor, and the source of the eighth PMOS transistor is connected to the body of the eighth NMOS transistor; One end of the seventh bias resistor is connected to the gate of the seventh NMOS transistor, and the other end of the seventh bias resistor is connected to the first signal control terminal; One end of the eighth bias resistor is connected to the gate of the eighth NMOS transistor, and the other end of the eighth bias resistor is connected to the first signal control terminal; One end of the second feedback capacitor is connected to the source end of the seventh bias resistor, and the other end of the second feedback capacitor is connected in series to the second signal control end through the ninth voltage-dividing resistor, the tenth voltage-dividing resistor, and the eleventh voltage-dividing resistor; The two ends of the tenth voltage resistor are connected to the source and drain of the eighth NMOS transistor respectively.

8. The radio frequency switch according to claim 1, wherein: The second parallel branch includes: a seventh DC blocking capacitor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, an eighth DC blocking capacitor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a ninth bias resistor, a tenth bias resistor, an eleventh bias resistor, a twelfth bias resistor, a twelfth voltage-dividing resistor, a fourteenth voltage-dividing resistor, a fifteenth voltage-dividing resistor, and a sixteenth voltage-dividing resistor; The drain of the ninth NMOS tube is connected to the seventh DC blocking capacitor; The source of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor; The source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor; The source of the eleventh NMOS transistor is connected to the drain of the twelfth NMOS transistor; The source of the twelfth NMOS transistor is grounded via the eighth DC blocking capacitor; The gate and drain of the ninth PMOS transistor are connected to the gate of the ninth NMOS transistor, and the source of the ninth PMOS transistor is connected to the body of the ninth NMOS transistor; The gate and drain of the tenth PMOS transistor are connected to the gate of the tenth NMOS transistor, and the source of the tenth PMOS transistor is connected to the body of the tenth NMOS transistor; The gate and drain of the eleventh PMOS transistor are connected to the gate of the eleventh NMOS transistor, and the source of the eleventh PMOS transistor is connected to the body of the eleventh NMOS transistor; The gate and drain of the twelfth PMOS tube are connected to the gate of the twelfth NMOS tube, and the source of the twelfth PMOS tube is connected to the body of the twelfth NMOS tube; The drain of the ninth NMOS transistor is connected in series to the first signal control terminal through a twelfth voltage-dividing resistor, a thirteenth voltage-dividing resistor, a fourteenth voltage-dividing resistor, a fifteenth voltage-dividing resistor, and a sixteenth voltage-dividing resistor; The two ends of the twelfth voltage-dividing resistor are respectively connected to the source and drain of the ninth NMOS transistor; The two ends of the tenth three-voltage resistor are respectively connected to the source and drain of the tenth NMOS transistor; The two ends of the fourteenth voltage-dividing resistor are respectively connected to the source and drain of the eleventh NMOS transistor; The two ends of the fifteenth voltage-dividing resistor are respectively connected to the source and drain of the twelfth NMOS transistor; One end of the ninth bias resistor is connected to the gate of the ninth NMOS transistor, and the other end of the ninth bias resistor is connected to the second signal control terminal; One end of the tenth bias resistor is connected to the gate of the tenth NMOS transistor, and the other end of the tenth bias resistor is connected to the second signal control terminal; One end of the eleventh bias resistor is connected to the gate of the eleventh NMOS transistor, and the other end of the eleventh bias resistor is connected to the second signal control terminal; One end of the twelfth bias resistor is connected to the gate of the twelfth NMOS transistor, and the other end of the twelfth bias resistor is connected to the second signal control end.

9. A radio frequency switch control method, characterized in that: For controlling the radio frequency switch according to any one of claims 1 to 8, the method comprising: The conduction states of the first series branch, the first parallel branch, the second series branch, and the second parallel branch are controlled by a pure positive voltage to control the radio frequency switch to switch between a receiving mode and a transmitting mode.

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