Direct input type infrared sensor pixel circuit with built-in correlated double sampling

Abstract

The present invention discloses a direct-input infrared sensor pixel circuit with built-in correlated double sampling, comprising an infrared detection diode PD, an injection switch S1, a reset switch S2, control switches S3, S4, S5, S6, a row selection switch S7, a source follower SF, and sampling capacitors C1, C2, and C3. The output end of the input stage circuit is connected to the column line COL of the pixel array. The invention solves the disadvantage that a traditional DI-type input stage circuit cannot implement CDS under global exposure, eliminates random reset noise caused by two different reset signals under global exposure of the traditional DI input stage circuit, and performs CDS operation inside the input stage circuit, thereby eliminating the post-stage CDS circuit in the infrared readout circuit, saving power consumption and area. At the same time, the input stage circuit proposed by the present invention directly outputs the CDS voltage, which saves readout time compared with the traditional input stage structure that outputs the signal voltage first and then the reset voltage, thereby improving the frame rate of the infrared imaging system.

Description

Technical Field

[0001] The invention belongs to the technical field of image acquisition and information processing, and relates to a direct input infrared sensor pixel circuit with built-in correlated double sampling. Background Art

[0002] Infrared imaging technology has been widely used in military and civilian fields in recent years. The current infrared imaging system mainly consists of infrared detectors and infrared readout circuits. The input stage circuit is a key link in the infrared readout circuit and determines the upper limit of the readout circuit performance.

[0003] Based on the circuit structure, input stage circuits can be divided into four categories: self-integration (SI), direct injection (DI), buffered direct injection (BDI), and capacitive transimpedance amplifier (CTIA). For ultra-large array infrared focal plane readout circuits, the input stage structure requires a small unit area and power consumption, as well as good linearity and dynamic range, so a DI input stage structure is typically used. However, traditional DI input stage circuits perform two samples of the same frame under global exposure at different reset times, making it incompatible with true correlated double sampling (CDS) operation and therefore difficult to eliminate random reset noise. However, achieving global exposure compatibility with correlated double sampling would significantly increase the complexity of the pixel structure, increase the pixel area, and reduce the fill factor, which is unacceptable for ultra-large array infrared readout circuits. Summary of the Invention

[0004] The purpose of the present invention is to provide a direct-input infrared sensor pixel circuit with built-in correlated double sampling, which solves the shortcoming that the traditional DI-type input stage circuit cannot implement CDS under global exposure. In addition, by performing CDS operation inside the input stage circuit, the subsequent CDS circuit in the infrared readout circuit can be omitted, saving power consumption and area.

[0005] The technical solution adopted by the present invention is a direct input infrared sensor pixel circuit with built-in correlated double sampling, including an infrared detection diode PD, the positive electrode of the infrared detection diode PD is connected to the bias common terminal VCOM, the negative electrode of the infrared detection diode PD is connected to the source of the injection switch S1, the drain of the injection switch S1 is respectively connected to the source of the reset switch S2, the source of the control switch S3 and the upper plate of the capacitor C1, the drain of the reset switch S2 and the drain of the source follower SF are connected to the power supply voltage VDD, the drain of the control switch S3 is connected to the drain of the control switch S4 and the source of the control switch S5, the source of the control switch S4 is connected to the upper plate of the capacitor C2, the lower plate of the capacitor C2, the lower plate of the capacitor C1 and the source of the control switch S6 are all connected to the ground voltage GND, the drain of the control switch S5 is connected to the upper plate of the capacitor C3, the lower plate of the capacitor C3 is connected to the drain of the control switch S6 and the gate of the source follower SF, the source of the source follower SF is connected to the drain of the row select switch S7, and the source of the row select switch S7 is connected to the column line COL.

[0006] The present invention is also characterized in that:

[0007] The injection switch S1 , the reset switch S2 , the control switch S3 , the control switch S4 , the control switch S5 , the control switch S6 , and the row selection switch S7 are all N-channel enhancement-type insulated gate field-effect transistors.

[0008] The infrared detection diode PD is an infrared detector made of mercury cadmium telluride material.

[0009] The MOS transistors used in the injection switch S1, reset switch S2, control switch S3, control switch S4, control switch S5, control switch S6, row selection switch S7 and source follower SF are all NMOS transistors, and are arranged in a form in which the source and drain are interchangeable.

[0010] The working sequence of the direct input infrared sensor pixel circuit with built-in correlated double sampling is:

[0011] Step 1, global reset operation: injection switch S1, reset switch S2, control switch S3, control switch S4 are turned on, and the other switches are turned off, the infrared detection diode PD and capacitors C1 and C2 are reset, and the reset voltage V is stored in capacitors C1 and C2. RST ;

[0012] Step 2, integration operation: the injection switch S1 is turned on, the other switches are turned off, and the signal voltage V is stored in the capacitor C1. SIG ;

[0013] Step 3, charge transfer: control switches S3, S5, and S6 are turned on, and the remaining switches are turned off, and the charge in capacitor C1 is transferred to capacitor C3;

[0014] Step 4, Correlated Double Sampling (CDS): Control switches S4 and S5 are turned on, and the others are turned off. The voltage on the top plate of capacitor C3 is V RST , the bottom plate voltage of capacitor C3 is V RST -V SIG ;

[0015] Step 5, readout: the row select switch S7 is turned on, and the correlated double sampling (CDS) voltage of the bottom plate of the capacitor C3 is read out row by row to the column line through the source follower SF;

[0016] Step 6: Global reset for the next frame. After the global reset, all pixels perform the integration operation for the next frame, and the pixels in the following row wait to read out the CDS voltage of this frame.

[0017] The present invention provides a DI-type input stage circuit capable of CDS, which has a small circuit scale and significant advantages over traditional structures in terms of noise and readout rate, making it suitable for large-area infrared readout circuits. Compared to traditional input stage structures, the present invention's method can firstly complete CDS within the input stage circuit while maintaining global exposure, eliminating the need for additional CDS circuitry in subsequent stages and significantly reducing random reset noise in the infrared readout circuit. Secondly, the input stage structure only outputs a CDS signal, which can improve the readout rate of the infrared readout circuit compared to traditional input stage structures that output both integration and reset signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic structural diagram of a direct input infrared sensor pixel circuit with built-in correlated double sampling according to the present invention;

[0019] Figure 2 This is the working sequence of the direct input infrared sensor pixel circuit with built-in correlated double sampling of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] The present invention has a built-in correlated double sampling direct input type infrared sensor pixel circuit, such as Figure 1 As shown, it includes an infrared detection diode PD, an injection switch S1, a reset switch S2, a control switch S3, a control switch S4, a control switch S5, a control switch S6, a row selection switch S7, a source follower SF, a sampling capacitor C1, a sampling capacitor C2, a sampling capacitor C3 and a pixel surface array line COL.

[0022] Switches S1 to S7 and SF are all N-channel enhancement-type insulated gate field-effect transistors, and their gates are connected to the corresponding control signals. PD is an infrared detection diode made of mercury cadmium telluride material, used to collect infrared signals and convert them into current. C1, C2, and C3 are sampling capacitors (of any type) used to collect the charge generated by infrared radiation; the positive electrode of the infrared detection diode PD is connected to the bias common terminal VCOM, and the negative electrode of the infrared detection diode PD is connected to the source of the injection switch S1. The drain of the injection switch S1 is connected to the source of the reset switch S2, the source of the control switch S3, and the upper plate of the capacitor C1. The drain of the reset switch S2 and the drain of the source follower SF are connected. The electrode of the control switch S3 is connected to the power supply voltage VDD, the drain of the control switch S3 is connected to the drain of the control switch S4 and the source of the control switch S5, the source of the control switch S4 is connected to the upper plate of the capacitor C2, the lower plate of the capacitor C2, the lower plate of the capacitor C1 and the source of the control switch S6 are all connected to the ground voltage GND, the drain of the control switch S5 is connected to the upper plate of the capacitor C3, the lower plate of the capacitor C3 is connected to the drain of the control switch S6 and the gate of the source follower SF, the source of the source follower SF is connected to the drain of the row select switch S7, and the source of the row select switch S7 is connected to the column line COL.

[0023] The working sequence of the direct input type infrared sensor pixel circuit with built-in correlated double sampling of the present invention is as follows: Figure 2 As shown, the steps are as follows:

[0024] Step 1, global reset operation: injection switch S1, reset switch S2, control switch S3, control switch S4 are turned on, control switch S5, control switch S6, and row selection switch S7 are turned off, and the infrared detection diode PD and capacitors C1 and C2 are reset. The reset voltage V is stored in capacitors C1 and C2. RST ;

[0025] Step 2, integration operation: the injection switch S1 is turned on, the other switches are turned off, and the signal voltage V is stored in the capacitor C1. SIG ;

[0026] Step 3, charge transfer: control switches S3, S5, and S6 are turned on, injection switch S1, reset switch S2, control switch S4, and row select switch S7 are all turned off, and the charge in capacitor C1 is transferred to capacitor C3;

[0027] Step 4, Correlated Double Sampling (CDS): Control switches S4 and S5 are turned on, injection switch S1, reset switch S2, control switch S3, control switch S6, and row select switch S7 are all turned off, and the upper plate voltage of capacitor C3 is V RST , the bottom plate voltage of capacitor C3 is V RST -V SIG ;

[0028] Step 5, readout: the row select switch S7 is turned on, and the correlated double sampling (CDS) voltage of the bottom plate of the capacitor C3 is read out row by row to the column line through the source follower SF;

[0029] Step 6: Global reset for the next frame. After the global reset, all pixels perform the integration operation for the next frame, and the pixels in the following row wait to read out the CDS voltage of this frame.

[0030] The working principle of the direct input type infrared sensor pixel circuit with built-in correlated double sampling of the present invention is as follows:

[0031] The injection switch S1 and VCOM jointly determine the bias voltage of the infrared detection diode PD and control the size of the integral current. The reset voltage of the current frame is stored in the capacitor C2, and the signal voltage of the current frame is stored in the capacitor C3. The voltage of the lower plate of the capacitor C2 is raised to VRST through the upper plate of the capacitor C3, thereby storing the CDS voltage of the current frame on the lower plate of the capacitor C2. When the next frame is reset, the reset voltage is stored in the capacitor C2 again. The control switch S5 ensures that the voltage signals stored on the upper and lower plates of the capacitor C3 are not affected by the circuit reset and integration. Finally, the CDS voltage is read out through the source follower SF. In this way, the true CDS function can be realized in the DI input stage circuit under global exposure.

Claims

1. A direct input infrared sensor pixel circuit with built-in correlated double sampling, characterized by: It includes an infrared detection diode PD, the positive electrode of the infrared detection diode PD is connected to the bias common terminal VCOM, the negative electrode of the infrared detection diode PD is connected to the source of the injection switch S1, the drain of the injection switch S1 is respectively connected to the source of the reset switch S2, the source of the control switch S3 and the upper plate of the capacitor C1, the drain of the reset switch S2 and the drain of the source follower SF are connected to the power supply voltage VDD, the drain of the control switch S3 is connected to the drain of the control switch S4 and the source of the control switch S5, the source of the control switch S4 is connected to the upper plate of the capacitor C2, the lower plate of the capacitor C2, the lower plate of the capacitor C1 and the source of the control switch S6 are all connected to the ground voltage GND, the drain of the control switch S5 is connected to the upper plate of the capacitor C3, the lower plate of the capacitor C3 is connected to the drain of the control switch S6 and the gate of the source follower SF, the source of the source follower SF is connected to the drain of the row selection switch S7, and the source of the row selection switch S7 is connected to the column line COL; The injection switch S1, reset switch S2, control switch S3, control switch S4, control switch S5, control switch S6, and row selection switch S7 are all N-channel enhancement type insulated gate field effect transistors; The infrared detection diode PD is an infrared detector made of mercury cadmium telluride material; The MOS transistors used in the injection switch S1, reset switch S2, control switch S3, control switch S4, control switch S5, control switch S6, row selection switch S7 and source follower SF are all NMOS transistors, and are arranged in a form in which the source and drain are interchangeable; The working sequence of the direct input infrared sensor pixel circuit with built-in correlated double sampling is as follows: Step 1, global reset operation: injection switch S1, reset switch S2, control switch S3, control switch S4 are turned on, and the other switches are turned off, the infrared detection diode PD and capacitors C1 and C2 are reset, and the reset voltage V is stored in capacitors C1 and C2. RST ; Step 2, integration operation: the injection switch S1 is turned on, the other switches are turned off, and the signal voltage V is stored in the capacitor C1. SIG ; Step 3, charge transfer: control switches S3, S5, and S6 are turned on, and the remaining switches are turned off, and the charge in capacitor C1 is transferred to capacitor C3; Step 4, Correlated Double Sampling (CDS): Control switches S4 and S5 are turned on, and the others are turned off. The voltage on the top plate of capacitor C3 is V RST , the bottom plate voltage of capacitor C3 is V RST -V SIG ; Step 5, readout: the row select switch S7 is turned on, and the correlated double sampling (CDS) voltage of the bottom plate of the capacitor C3 is read out row by row to the column line through the source follower SF; Step 6: Global reset for the next frame. After the global reset, all pixels perform the integration operation for the next frame, and the pixels in the following row wait to read out the CDS voltage of this frame.

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