Ramp signal generator and image sensor including the same

Abstract

The present disclosure relates to a ramp signal generator and an image sensor including the same. The ramp signal generator includes: a resistor circuit coupled to a first voltage terminal and an output terminal and configured to adjust a resistance value applied to the output terminal based on a plurality of control signals, through which a ramp signal is output; and a current circuit coupled to a second voltage terminal and the output terminal and configured to adjust a current level applied to the output terminal and a rate of change of the current level based on a clock signal. The plurality of control signals are generated based on an analog gain having a multiple range, and the clock signal has a first frequency when the analog gain has a first range within the multiple range, and has a second frequency when the analog gain has a second range within the multiple range.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly, to an image sensor including a ramp signal generator. Background Art

[0002] Image sensors are devices that capture images by exploiting the properties of semiconductors that react to light. Image sensors can be broadly categorized as charge-coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. CMOS image sensors have recently become more widely used because they allow analog and digital control circuits to be directly implemented on a single integrated circuit (IC). Summary of the Invention

[0003] Various embodiments of the present disclosure are directed to an image sensor that can generate an optimized ramp signal when adjusting an analog gain.

[0004] According to one embodiment of the present disclosure, a ramp signal generator may include: a resistance circuit, which is connected to a first voltage terminal and an output terminal and is suitable for adjusting the resistance value applied to the output terminal according to multiple control signals, and the ramp signal is output through the output terminal; and a current circuit, which is connected to a second voltage terminal and the output terminal and is suitable for adjusting the current level applied to the output terminal and the rate of change of the current level according to a clock signal, wherein the multiple control signals are generated based on an analog gain having a predetermined multiple range, and wherein when the analog gain has a first range within the predetermined multiple range, the clock signal has a first frequency, and when the analog gain has a second range within the predetermined multiple range, the clock signal has a second frequency.

[0005] According to one embodiment of the present disclosure, an image sensor may include: a pixel array adapted to generate pixel signals; a ramp signal generator adapted to: generate the ramp signal via an output terminal by adjusting a resistance value applied to the output terminal and a rate of change of a current level applied to the output terminal according to a plurality of control signals and a clock signal when an analog gain has a first range within a predetermined multiple range, and generate the ramp signal via the output terminal by adjusting only the resistance value according to a plurality of control signals and a clock signal when the analog gain has a second range within the predetermined multiple range; and a signal converter adapted to read out the pixel signal based on the ramp signal.

[0006] According to one embodiment of the present disclosure, an image sensor may include: a timing controller configured to generate a clock having one of a first frequency and a second frequency according to a selected gain value among gain values; a ramp signal generator configured to generate a ramp signal at an output node on a path between a high voltage node and a low voltage node, and including: a current circuit configured to adjust a level of current flowing on the path according to an edge of the clock; and a resistance circuit configured to adjust a resistance value between the output node and the low voltage node according to the selected gain value; and a signal converter configured to convert an analog pixel signal into a digital pixel signal according to the ramp signal, wherein the first frequency is lower than the second frequency, and wherein the first frequency and the second frequency correspond to selected gain values ​​belonging to a higher group and a lower group of gain values, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an image sensor according to one embodiment of the present disclosure.

[0008] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 Block diagram of the ramp signal generator illustrated in FIG.

[0009] Figure 3 This is an example of an embodiment according to the present disclosure. Figure 2 The block diagram of the current circuit is shown.

[0010] Figure 4 This is an example of an embodiment according to the present disclosure. Figure 2 The circuit diagram of the resistor circuit is shown.

[0011] Figure 5 This is an example of an embodiment according to the present disclosure. Figure 1 A graph of the ramp signal is shown. DETAILED DESCRIPTION

[0012] Various embodiments of the present disclosure are described below with reference to the accompanying drawings to describe the present disclosure in detail so that those skilled in the art to which the present disclosure belongs can easily implement the technical spirit of the present disclosure.

[0013] It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the other element, or electrically connected to or coupled to the other element with one or more elements interposed therebetween. In addition, it will be understood that when used in this specification, the terms “comprises,” “having,” “includes,” and “containing” do not exclude the presence of one or more other elements, but rather may further include or have one or more other elements unless otherwise mentioned. Throughout the description of the specification, some components are described in the singular, but the present disclosure is not limited thereto, and it will be understood that these components may be formed in the plural.

[0014] Figure 1 is a block diagram illustrating an image sensor 100 according to an embodiment of the present disclosure.

[0015] Reference Figure 1 , the image sensor 100 may include a row controller 110 , a pixel array 120 , a timing controller 130 , a ramp signal generator 140 , and a signal converter 150 .

[0016] The row controller 110 may generate, for each row, a row control signal RCTRLs for controlling the pixel array 120. For example, the row controller 110 may generate a first row control signal for controlling pixels arranged in a first row of the pixel array 120, and generate a y-th row control signal for controlling pixels arranged in a y-th row of the pixel array 120, where "y" is a natural number greater than 2. The row control signals RCTRLs may include the first row control signal to the y-th row control signal.

[0017] The pixel array 120 may include a plurality of pixels (not shown) arranged at intersections of a plurality of rows and a plurality of columns. Based on the row control signal RCTRLs, the plurality of pixels may output pixel signals PXOUT<1:n> for each row through a plurality of column lines. For example, pixels arranged in the first row among the plurality of pixels may generate pixel signals PXOUT<1:n> in the first unit row time based on the first row control signal, and pixels arranged in the yth row among the plurality of pixels may generate pixel signals PXOUT<1:n> in the yth unit row time based on the yth row control signal.

[0018] The timing controller 130 may generate a plurality of control signals VCTRLs and a clock signal CLK according to analog gains having a predetermined multiple range. For example, the predetermined multiple range may include 1 times (AG×1) to 64 times (AG×64). For example, the timing controller 130 may generate a plurality of control signals VCTRLs corresponding to the analog gains and generate a clock signal CLK having a frequency corresponding to the analog gains.

[0019] The timing controller 130 may include a first control circuit CC1 and a second control circuit CC2. The first control circuit CC1 may generate multiple control signals VCTRLs based on the analog gain. For example, the first control circuit CC1 may generate multiple control signals VCTRLs corresponding to any multiples within a predetermined range of multiples based on the analog gain. The second control circuit CC2 may generate a clock signal CLK based on the analog gain. For example, the second control circuit CC2 may generate a clock signal CLK having a first frequency when the analog gain is within a first range within the predetermined range of multiples, and a clock signal CLK having a second frequency when the analog gain is within a second range within the predetermined range of multiples. The second range may include relatively low multiples within the predetermined range of multiples. For example, the second range may include 1x (AGx1) to 32x (AGx32) within the range of 1x (AGx1) to 64x (AGx64). The first range may include relatively high multiples within the predetermined range of multiples. For example, the first range may include 33x (AGx33) to 64x (AGx64) within the range of 1x (AGx1) to 64x (AGx64). The second frequency may be a relatively high frequency, and the first frequency may be a relatively low frequency. For example, the first frequency may be a frequency corresponding to half (1 / 2) of the second frequency.

[0020] The ramp signal generator 140 can generate a ramp signal VRAMP having a slope corresponding to the analog gain based on a plurality of control signals VCTRLs and a clock signal CLK. For example, when the analog gain has a first range within a predetermined multiple range, the ramp signal generator 140 can generate the ramp signal VRAMP via the output terminal VOUT of the ramp signal VRAMP by adjusting both the resistance value applied to the output terminal VOUT and the rate of change of the current level applied to the output terminal VOUT. When the analog gain has a second range within the predetermined multiple range, the ramp signal generator 140 can generate the ramp signal VRAMP via the output terminal VOUT by adjusting only the resistance value, of the resistance value and the rate of change of the current level. That is, when the analog gain has the second range, the ramp signal generator 140 can adjust the resistance value based on the high-frequency clock signal CLK while the rate of change of the current level is set to a first value (i.e., a fixed value or a default value). When the analog gain has the first range, the ramp signal generator 140 can adjust the resistance value based on the low-frequency clock signal CLK while the rate of change of the current level is set to a second value (i.e., a changed value or a variable value).

[0021] The signal converter 150 may convert the analog pixel signals PXOUT<1:n> into digital pixel signals DOUT<1:n> based on the ramp signal VRAMP and the pixel signals PXOUT<1:n>. For example, the signal converter 150 may include a plurality of analog-to-digital converters (ADCs) corresponding to a plurality of columns.

[0022] Figure 2 This is an example of an embodiment according to the present disclosure. Figure 1 A block diagram of an example of a ramp signal generator 140 is shown.

[0023] Reference Figure 2 , the ramp signal generator 140 may include a current circuit 141 and a resistance circuit 143 .

[0024] The current circuit 141 can be coupled to the high voltage terminal and the output terminal VOUT. The current circuit 141 can adjust the current level and the rate of change of the current level applied to the output terminal VOUT based on the clock signal CLK. For example, the current circuit 141 can adjust the current level based on a specific edge of the clock signal CLK (i.e., a rising edge or a falling edge) and adjust the rate of change of the current level based on the frequency of the clock signal CLK. The current level can correspond to the direction of the ramp change of the ramp signal VRAMP, and the rate of change of the current level can correspond to the slope of the ramp signal VRAMP.

[0025] The resistance circuit 143 may be coupled to the low voltage terminal and the output terminal VOUT. The resistance circuit 143 may adjust the resistance value applied to the output terminal VOUT based on a plurality of control signals VCTRLs. The resistance value may correspond to the slope of the ramp signal VRAMP.

[0026] Figure 3 This is an example of an embodiment according to the present disclosure. Figure 2 A block diagram of an example of a current circuit 141 is shown.

[0027] Reference Figure 3 , the current circuit 141 may include a row decoder RDEC, a column decoder CDEC and a current cell array RCA.

[0028] The row decoder RDEC may generate a plurality of row selection signals RSELs based on the clock signal CLK. For example, the row decoder RDEC may activate all of the plurality of row selection signals RSELs and then sequentially deactivate the plurality of row selection signals RSELs.

[0029] The column decoder CDEC may generate a plurality of column selection signals CSELs based on the clock signal CLK. For example, the column decoder CDEC may activate all of the plurality of column selection signals CSELs and then sequentially deactivate the plurality of column selection signals CSELs.

[0030] The current cell array RCA can sequentially adjust the current level of the ramp signal VRAMP applied to the output terminal VOUT of the ramp signal VRAMP based on multiple row select signals RSELs and multiple column select signals CSELs, and adjust the rate of change of the current level. The current cell array RCA can include multiple current cells CE arranged at the intersections of multiple rows and multiple columns. The multiple current cells CE can be selected based on the multiple row select signals RSELs and multiple column select signals CSELs. For example, the multiple current cells CE can all be enabled based on the multiple activated row select signals RSELs and multiple activated column select signals CSELs, and then sequentially disabled based on the multiple row select signals RSELs and multiple column select signals CSELs being sequentially disabled. The number of enabled current cells CE and disabled current cells CE can be related to the current level of the ramp signal VRAMP, and the interval at which each current cell CE changes from an enabled state to a disabled state can be related to the slope of the ramp signal VRAMP.

[0031] Although the present embodiment includes the row decoder RDEC and the column decoder CDEC, the present embodiment is not limited thereto and may include only one of the row decoder RDEC and the column decoder CDEC depending on the arrangement structure of the current cell array RCA.

[0032] Figure 4This is an example of an embodiment according to the present disclosure. Figure 2 A circuit diagram of an example of the resistance circuit 143 is shown.

[0033] Reference Figure 4 The resistance circuit 143 may include a fixed resistance unit DC and a plurality of variable resistance units RC1 to RC8. Hereinafter, the plurality of variable resistance units RC1 to RC8 are described as first to eighth variable resistance units RC1 to RC8, and the plurality of control signals VCTRLs are described as first to eighth control signals VCTRL<1:8>.

[0034] The fixed resistance unit DC can apply a fixed resistance value to the output terminal VOUT. That is, the fixed resistance unit DC can apply a fixed resistance value to the output terminal VOUT as a default value. For example, the fixed resistance unit DC may include a resistor RR and a switch TT. The resistor RR may be connected between the output terminal VOUT and the switch TT. The resistor RR may have a fixed resistance value. The switch TT may be connected between the resistor RR and the low voltage terminal. The switch TT may include a transistor having a gate terminal connected to the high voltage terminal and a source terminal and a drain terminal connected between the resistor RR and the low voltage terminal. The reference symbol “×16” may represent the number of fixed resistance units DC connected in parallel to the output terminal VOUT.

[0035] The first variable resistance unit RC1 can be configured based on the first control signal VCTRL <1> The first resistance value is selectively applied to the output terminal VOUT. That is, the first variable resistance unit RC1 can additionally apply the first variable resistance value to the output terminal VOUT. For example, the first variable resistance unit RC1 may include a first resistor R1 and a first switch T1. The first resistor R1 may be connected between the output terminal VOUT and the first switch T1. The first resistor R1 may have a first resistance value. The first switch T1 may be connected between the first resistor R1 and the low voltage terminal. The first switch T1 may include a first transistor having a first control signal VCTRL. <1> The reference sign “×2” may represent the number of first variable resistance units RC1 coupled to the output terminal VOUT.

[0036] The second variable resistance unit RC2 can be configured based on the second control signal VCTRL <2> The second resistance value is selectively applied to the output terminal VOUT. That is, the second variable resistance unit RC2 can additionally apply the second variable resistance value to the output terminal VOUT. For example, the second variable resistance unit RC2 may include a second resistor R2 and a second switch T2. The second resistor R2 may be connected between the output terminal VOUT and the second switch T2. The second resistor R2 may have a second resistance value. The second switch T2 may be connected between the second resistor R2 and the low voltage terminal. The second switch T2 may include a second transistor having a second control signal VCTRL. <2> The reference sign “×4” may denote the number of second variable resistance units RC2 coupled in parallel to the output terminal VOUT.

[0037] The third variable resistance unit RC3 can be configured based on the third control signal VCTRL <3> The third resistance value is selectively applied to the output terminal VOUT. That is, the third variable resistance unit RC3 can additionally apply the third variable resistance value to the output terminal VOUT. For example, the third variable resistance unit RC3 may include a third resistor R3 and a third switch T3. The third resistor R3 may be connected between the output terminal VOUT and the third switch T3. The third resistor R3 may have a third resistance value. The third switch T3 may be connected between the third resistor R3 and the low voltage terminal. The third switch T3 may include a third transistor having a third control signal VCTRL. <3> The reference sign “×8” may denote the number of third variable resistance units RC3 coupled to the output terminal VOUT.

[0038] The fourth variable resistance unit RC4 can be based on the fourth control signal VCTRL <4> The fourth resistance value is selectively applied to the output terminal VOUT. That is, the fourth variable resistance unit RC4 can additionally apply the fourth variable resistance value to the output terminal VOUT. For example, the fourth variable resistance unit RC4 may include a fourth resistor R4 and a fourth switch T4. The fourth resistor R4 may be connected between the output terminal VOUT and the fourth switch T4. The fourth resistor R4 may have a fourth resistance value. The fourth switch T4 may be connected between the fourth resistor R4 and the low voltage terminal. The fourth switch T4 may include a fourth transistor having a fourth control signal VCTRL. <4> The reference sign “×16” may denote the number of fourth variable resistance units RC4 coupled to the output terminal VOUT.

[0039] The fifth variable resistance unit RC5 can be based on the fifth control signal VCTRL <5> The fifth resistance value is selectively applied to the output terminal VOUT. That is, the fifth variable resistance unit RC5 can additionally apply the fifth variable resistance value to the output terminal VOUT. For example, the fifth variable resistance unit RC5 may include a fifth resistor R5 and a fifth switch T5. The fifth resistor R5 may be connected between the output terminal VOUT and the fifth switch T5. The fifth resistor R5 may have a fifth resistance value. The fifth switch T5 may be connected between the fifth resistor R5 and the low voltage terminal. The fifth switch T5 may include a fifth transistor having a fifth control signal VCTRL. <5> The reference sign “×32” may denote the number of fifth variable resistance units RC5 coupled to the output terminal VOUT.

[0040] The sixth variable resistance unit RC6 can be based on the sixth control signal VCTRL <6> The sixth resistance value is selectively applied to the output terminal VOUT. That is, the sixth variable resistance unit RC6 can additionally apply the sixth variable resistance value to the output terminal VOUT. For example, the sixth variable resistance unit RC6 may include a sixth resistor R6 and a sixth switch T6. The sixth resistor R6 may be connected between the output terminal VOUT and the sixth switch T6. The sixth resistor R6 may have a sixth resistance value. The sixth switch T6 may be connected between the sixth resistor R6 and the low voltage terminal. The sixth switch T6 may include a sixth transistor having a sixth control signal VCTRL. <6> The reference numeral '×64' may denote the number of sixth variable resistance units RC6 coupled to the output terminal VOUT.

[0041] The seventh variable resistance unit RC7 can be based on the seventh control signal VCTRL <7> The seventh resistance value is selectively applied to the output terminal VOUT. That is, the seventh variable resistance unit RC7 can additionally apply the seventh variable resistance value to the output terminal VOUT. For example, the seventh variable resistance unit RC7 may include a seventh resistor R7 and a seventh switch T7. The seventh resistor R7 may be connected between the output terminal VOUT and the seventh switch T7. The seventh resistor R7 may have a seventh resistance value. The seventh switch T7 may be connected between the seventh resistor R7 and the low voltage terminal. The seventh switch T7 may include a seventh transistor having a seventh control signal VCTRL. <7> The reference numeral “×128” may denote the number of seventh variable resistance units RC7 coupled to the output terminal VOUT.

[0042] The eighth variable resistance unit RC8 can be based on the eighth control signal VCTRL <8> The eighth resistance value is selectively applied to the output terminal VOUT. That is, the eighth variable resistance unit RC8 can additionally apply the eighth variable resistance value to the output terminal VOUT. For example, the eighth variable resistance unit RC8 may include an eighth resistor R8 and an eighth switch T8. The eighth resistor R8 may be connected between the output terminal VOUT and the eighth switch T8. The eighth resistor R8 may have an eighth resistance value. The eighth switch T8 may be connected between the eighth resistor R8 and the low voltage terminal. The eighth switch T8 may include an eighth transistor having a function of receiving the eighth control signal VCTRL <8> The reference sign “×256” may represent the number of eighth variable resistance units RC8 coupled to the output terminal VOUT.

[0043] Hereinafter, the operation of the image sensor 100 having the above-described configuration according to one embodiment is described.

[0044] Pixel array 120 can output pixel signals PXOUT<1:n> through a plurality of column lines based on row control signals RCTRLs. For example, pixel array 120 can generate pixel signals PXOUT<1:n> corresponding to pixels arranged in the first row in a first unit row time based on a first row control signal among row control signals RCTRLs, and can generate pixel signals PXOUT<1:n> corresponding to pixels arranged in the yth row in a yth unit row time based on a yth row control signal among row control signals RCTRLs.

[0045] The timing controller 130 may generate a plurality of control signals VCTRLs and a clock signal CLK according to the analog gain. For example, the timing controller 130 may generate a plurality of control signals VCTRLs and a clock signal CLK as shown in Table 1 below according to the analog gain.

[0046] [Table 1]

[0047] serial number Control Target Analog gain CLK VCTRLs 1 resistance value AG×1~AG×32 high frequency VCTRL<1:8> 2 Resistance value + frequency AG×33~AG×64 low frequency VCTRL<1:8>

[0048] When the analog gain has one of the values ​​of 1 times (AG×1) to 32 times (AG×32) included in the second range, the timing controller 130 may generate a clock signal CLK having a high frequency as a default value and generate a plurality of control signals VCTRLs so as to adjust only the resistance value applied to the output terminal VOUT. For example, when the analog gain has one of the values ​​of 1 times (AG×1) to 32 times (AG×32) included in the second range, the timing controller 130 may combine the plurality of control signals VCTRL<1:8> according to the analog gain having the value while the clock signal CLK is fixed at a high frequency.

[0049] When the analog gain has one of 33 times (AG×33) to 64 times (AG×64) included in the first range, the timing controller 130 may generate a clock signal CLK having a low frequency and generate a plurality of control signals VCTRLs so as to adjust the resistance value applied to the output terminal VOUT. For example, when the analog gain has one of 33 times (AG×33) to 64 times (AG×64) included in the first range, the timing controller 130 may combine the plurality of control signals VCTRL<1:8> according to the analog gain having the multiple while the clock signal CLK becomes low frequency. The low frequency may be a frequency corresponding to half (1 / 2) of the high frequency.

[0050] The ramp signal generator 140 can generate a ramp signal VRAMP having a slope corresponding to the analog gain based on a plurality of control signals VCTRLs and a clock signal CLK. For example, when the analog gain has a multiple of 1 times (AG×1) to 32 times (AG×32) within the second range, the ramp signal generator 140 can adjust the resistance value applied to the output terminal VOUT of the ramp signal VRAMP while maintaining the rate of change of the current level applied to the output terminal VOUT at a default value, thereby generating a ramp signal VRAMP having a slope corresponding to the multiple through the output terminal VOUT. When the analog gain has a multiple of 33 times (AG×33) to 64 times (AG×64) within the first range, the ramp signal generator 140 can adjust the resistance value applied to the output terminal VOUT of the ramp signal VRAMP while changing the rate of change of the current level applied to the output terminal VOUT, thereby generating a ramp signal VRAMP having a slope corresponding to the multiple through the output terminal VOUT.

[0051] The ramp signal generator 140 may adjust a resistance value of the output terminal VOUT applied to the ramp signal VRAMP based on the following “Equation 1”.

[0052] [Formula 1]

[0053]

[0054] Here, “AG” may refer to analog gain, “N” may refer to the number of variable resistance units selected from the total number of the first to eighth variable resistance units RC1 to RC8 , and “1 (=16 / 16)” may refer to the fixed resistance unit DC.

[0055] For example, when all of the first to eighth variable resistance units RC1 to RC8 are not selected, that is, when all of the multiple control signals VCTRL<1:8> are disabled, the ramp signal generator 140 can apply only the fixed resistance value of the fixed resistance unit DC to the output terminal VOUT of the ramp signal VRAMP, thereby generating the ramp signal VRAMP having a slope corresponding to an analog gain of 1 times (AG×1).

[0056] The signal converter 150 may convert the analog type pixel signal PXOUT<1:n> into the digital type pixel signal DOUT<1:n> based on the ramp signal VRAMP and the pixel signal PXOUT<1:n>.

[0057] Figure 5 is a graph illustrating a ramp signal VRAMP according to one embodiment of the present disclosure.

[0058] Reference Figure 5 The ramp signal VRAMP may have a slope corresponding to the analog gain. For example, when the analog gain is 32 times (AG×32), the ramp signal VRAMP may have a relatively steep slope, and when the analog gain is 64 times (AG×64), the ramp signal VRAMP may have a relatively gentle slope.

[0059] When the analog gain is 32 times (AG×32), the ramp signal generator 140 can adjust only the resistance value while the rate of change of the current level (i.e., the frequency of the clock signal CLK) is fixed to a preset value, and generate a ramp signal VRAMP with a relatively steep slope. When the analog gain is 64 times (AG×64), the ramp signal generator 140 can adjust the resistance value while changing the rate of change of the current level (i.e., the frequency of the clock signal CLK), and generate a ramp signal VRAMP with a relatively gentle slope.

[0060] According to one embodiment of the present disclosure, the resistance value and the rate of change of the current level (ie, the frequency of the clock signal) applied to the output terminal of the ramp signal can be appropriately combined and adjusted according to the analog gain, which makes it possible to generate an optimized ramp signal.

[0061] One embodiment of the present disclosure has a beneficial effect in terms of area by configuring a circuit (ie, a ramp signal generator) for generating an optimized ramp signal when adjusting an analog gain.

[0062] Although the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are provided for illustration only and are not intended to be limiting. Furthermore, it should be noted that, as will be appreciated by those skilled in the art in light of this disclosure, the present disclosure may be implemented in various ways through substitutions, changes, and modifications that fall within the scope of the appended claims. Furthermore, the claims may be combined to form additional claims.

[0063] CROSS-REFERENCE TO RELATED APPLICATIONS

[0064] This application claims priority to Korean Patent Application No. 10-2021-0183738, filed on December 21, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A ramp signal generator, comprising: a resistance circuit coupled to the first voltage terminal and an output terminal and adapted to adjust a resistance value applied to the output terminal according to a plurality of control signals, the ramp signal being outputted through the output terminal; and a current circuit coupled to the second voltage terminal and the output terminal and adapted to adjust a current level applied to the output terminal and a rate of change of the current level according to a clock signal, wherein the plurality of control signals are generated according to analog gains having a predetermined range of multiples, and When the analog gain has a first range within the predetermined multiple range, the clock signal has a first frequency, and when the analog gain has a second range within the predetermined multiple range, the clock signal has a second frequency.

2. The ramp signal generator according to claim 1, wherein: The resistance circuit comprises: a first resistance unit adapted to apply a fixed resistance value to the output terminal; and A plurality of second resistance units are adapted to apply variable resistance values ​​to the output terminal based on the plurality of control signals.

3. The ramp signal generator according to claim 1, wherein: The current circuit comprises: a decoder adapted to generate a plurality of selection signals based on the clock signal; and A current cell array is configured to sequentially adjust the current levels and adjust a rate of change of the current levels based on the plurality of selection signals.

4. The ramp signal generator according to claim 1, wherein: Within the predetermined multiple range, the first range includes relatively high multiples, and the second range includes relatively low multiples.

5. The ramp signal generator according to claim 1, wherein: The first frequency is higher than the second frequency.

6. An image sensor, comprising: a pixel array adapted to generate pixel signals; A ramp signal generator, wherein the ramp signal generator is adapted to: When the analog gain has a first range within a predetermined multiple range, a ramp signal is generated via the output terminal by adjusting a resistance value applied to the output terminal and a rate of change of a current level applied to the output terminal according to a plurality of control signals and a clock signal, and When the analog gain has a second range within the predetermined multiple range, the ramp signal is generated via the output terminal by adjusting only the resistance value according to the plurality of control signals and the clock signal, and A signal converter is configured to read out the pixel signal based on the ramp signal.

7. The image sensor according to claim 6, wherein: When the analog gain has the second range, the ramp signal generator sets the rate of change of the current level to a first value based on the clock signal with a relatively high frequency, and when the analog gain has the first range, the ramp signal generator sets the rate of change of the current level to a second value based on the clock signal with a relatively low frequency.

8. The image sensor according to claim 6, wherein: The ramp signal generator comprises: a resistance circuit coupled to a first voltage terminal and the output terminal and adapted to adjust the resistance value applied to the output terminal based on the plurality of control signals, and A current circuit is coupled to the second voltage terminal and the output terminal and is adapted to adjust the current level applied to the output terminal and the rate of change of the current level based on the clock signal.

9. The image sensor according to claim 8, wherein: The resistance circuit comprises: a first resistance unit adapted to apply a fixed resistance value to the output terminal; and A plurality of second resistance units are adapted to apply variable resistance values ​​to the output terminal based on the plurality of control signals.

10. The image sensor according to claim 8, wherein The current circuit comprises: a decoder adapted to generate a plurality of selection signals based on the clock signal; and A current cell array is adapted to sequentially adjust the current levels applied to the output terminals and adjust a rate of change of the current levels based on the plurality of selection signals. 11 . The image sensor according to claim 6 , further comprising a timing controller adapted to generate the plurality of control signals according to the analog gains.

12. The image sensor according to claim 11, wherein: The timing controller comprises: a first control circuit adapted to generate the plurality of control signals according to the analog gains having the predetermined multiple range; and A second control circuit is adapted to generate the clock signal having a first frequency when the analog gain has the first range within the predetermined multiple range, and to generate the clock signal having a second frequency when the analog gain has the second range within the predetermined multiple range.

13. An image sensor, comprising: a timing controller that generates a clock having one of a first frequency and a second frequency according to a selected gain value among the gain values; a ramp signal generator that generates a ramp signal at an output node on a path between a high voltage node and a low voltage node, and includes: a current circuit that adjusts a level of current flowing on the path according to an edge of the clock, and a resistance circuit that adjusts a resistance value between the output node and the low voltage node according to the selected gain value; and a signal converter, wherein the signal converter converts the analog pixel signal into a digital pixel signal according to the ramp signal, wherein the first frequency is lower than the second frequency, and The first frequency and the second frequency correspond to the selected gain values ​​belonging to the upper group and the lower group of gain values, respectively.

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