Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure and a method of fabricating the same are provided. The semiconductor structure includes a semiconductor substrate having an active region defined by an isolation structure. The semiconductor structure includes a trench extending through the active region and the isolation structure. The active region of the semiconductor substrate includes a fin structure disposed in the trench. The fin structure includes a first protrusion extending upward along a first sidewall of the trench.

Description

[0001] This application claims priority to U.S. Patent Application Nos. 17 / 554,813 and 17 / 554,102 (i.e., priority date of “December 17, 2021”), the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure having a fin structure. BACKGROUND

[0003] With the rapid growth of the electronics industry, the development of semiconductor elements has achieved high performance and miniaturization. Due to the size reduction of semiconductor elements, such as dynamic random access memory (DRAM) elements, a short channel effect can occur. To address such issues, a buried-channel array transistor (BCAT) element is proposed.

[0004] However, although the recessed channel of the BCAT element improves the short channel effect, the BCAT element has other problems, such as a decrease in threshold voltage (Vth) and current leakage, which adversely affect the performance and stability of the semiconductor element.

[0005] The above description of background art is provided merely for purposes of background information and does not constitute an admission of prior art by the present disclosure, nor does it constitute any part of the prior art of the present disclosure, and any acknowledgement of the above background art does not constitute any part of the present invention. SUMMARY

[0006] One embodiment of the present disclosure provides a semiconductor structure including a semiconductor substrate. The semiconductor substrate has an active region defined by an isolation structure. A trench passes through the active region and the isolation structure. The active region of the semiconductor substrate includes a fin structure in the trench. The fin structure includes a first protrusion extending upward along a first sidewall of the trench.

[0007] Another embodiment of the present disclosure provides a semiconductor structure including a semiconductor substrate and a conductive element. The semiconductor substrate has an active region including a fin structure. The fin structure includes a main body portion and a first tapered portion. The first tapered portion protrudes from an upper surface of the main body portion. The conductive element is disposed on the main body portion and the first tapered portion of the fin structure.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an active region. The method further includes removing a portion of the active region of the semiconductor substrate to form a trench and an initial fin structure. The method also includes removing a portion of the initial fin structure to form a fin structure including a first protrusion extending upwardly along a first sidewall of the trench.

[0009] When designing a fin structure including protrusions extending upwards along the trench sidewalls, these protrusions can provide an extension of the fin structure that can be further covered by conductive elements. Since the electric field is relatively high near the trench sidewalls (i.e., the location of the doped region or the source / drain region of a unit transistor), the protrusions covered by conductive elements can increase the area covered by the conductive elements (i.e., the gate control region). Therefore, additional gate control regions can be created, and gate control of the semiconductor structure (i.e., the transistor) channel can be improved.

[0010] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0011] The disclosure of the present invention can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0012] FIG. 1A This is a top view illustrating semiconductor structures according to some embodiments of the present disclosure.

[0013] FIG. 1B This is a cross-sectional view illustrating semiconductor structures according to some embodiments of this disclosure.

[0014] FIG. 1C This is a three-dimensional view illustrating semiconductor structures according to some embodiments of this disclosure.

[0015] FIG. 1D This is a perspective view illustrating a portion of a semiconductor structure according to some embodiments of the present disclosure.

[0016] FIG. 2A and FIG. 2B This illustrates a stage of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0017] FIG. 3A and FIG. 3B An example of a stage of a method of fabricating a semiconductor structure according to some embodiments of the disclosure.

[0018] FIG. 4A and FIG. 4B An example of a stage of a method of fabricating a semiconductor structure according to some embodiments of the disclosure.

[0019] FIG. 5A and FIG. 5B An example of a stage of a method of fabricating a semiconductor structure according to some embodiments of the disclosure.

[0020] FIG. 6A and FIG. 6B An example of a stage of a method of fabricating a semiconductor structure according to some embodiments of the disclosure.

[0021] FIG. 7A and FIG. 7B An example of a stage of a method of fabricating a semiconductor structure according to some embodiments of the disclosure.

[0022] FIG. 8A and FIG. 8B An example of a stage of a method of fabricating a semiconductor structure according to some embodiments of the disclosure.

[0023] FIG. 9 is a flowchart illustrating a method of fabricating a semiconductor structure according to some embodiments of the disclosure.

[0024] The following reference signs are used in the drawings:

[0025] 1: semiconductor structure

[0026] 1B-1B’: lines

[0027] 1D: portion

[0028] 2B-2B’: lines

[0029] 3B-3B’: lines

[0030] 4B-4B’: lines

[0031] 5B-5B’: lines

[0032] 6B-6B’: lines

[0033] 7B-7B’: lines

[0034] 10: semiconductor substrate

[0035] 10A: active region

[0036] 20: isolation structure

[0037] 30: trench

[0038] 30A: Trench

[0039] 40: Conductive elements

[0040] 50: Dielectric layer

[0041] 90: Preparation method

[0042] 100: Fin structure

[0043] 100A: Initial fin structure

[0044] 100A1: Top surface

[0045] 100A2: Side View

[0046] 110: protrusion

[0047] 111: Incline

[0048] 112: Incline

[0049] 113: Incline

[0050] 120: Main body

[0051] 121: Upper surface

[0052] 122: Incline

[0053] 123: Incline

[0054] 124: Bottom

[0055] 130: Protrusion

[0056] 131: Incline

[0057] 132: Incline

[0058] 133: Incline

[0059] 201: Upper surface

[0060] 301: Sidewall

[0061] 302: Sidewall

[0062] 303: Bottom surface

[0063] PR: Patterned photoresist layer

[0064] S91: Operation

[0065] S92: Operation

[0066] S93: Operation

[0067] T1: Depth

[0068] T2: Distance

[0069] T3: Thickness

[0070] T4: Thickness

[0071] T5: Thickness

[0072] T6: Distance

[0073] W1: Width

[0074] W2: Width

[0075] W3: Length

[0076] W4: Length

[0077] X: Direction

[0078] Y: direction

[0079] Z: Direction Detailed Implementation

[0080] Embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as commonly done by one of ordinary skill in the art related to the content of this disclosure. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same reference numerals.

[0081] It should be understood that although the terms first, second, third, etc., can be used to describe various elements, components, regions, layers, or portions, these elements, components, regions, layers, or portions are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or portion from another. Therefore, the first element, component, region, layer, or portion discussed below can be referred to as the second element, component, region, layer, or portion without departing from the teachings of the concept of the invention.

[0082] The terminology used herein is for describing particular embodiments only and is not intended to limit one to the concepts of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms “comprising” and “including” as used in this specification indicate the presence of the stated feature, integer, step, operation, element, or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0083] FIG. 1A This is a top view illustrating a semiconductor structure 1 according to some embodiments of this disclosure. FIG. 1B This is a cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of this disclosure. FIG. 1C This is a three-dimensional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure, and FIG. 1D This is a perspective view illustrating a portion 1D of a semiconductor structure 1 according to some embodiments of the present disclosure. The semiconductor structure 1 includes a semiconductor substrate 10, an isolation structure 20, one or more trenches 30, one or more conductive elements 40, and one or more dielectric layers 50.

[0084] FIG. 1B It is along FIG. 1A A cross-sectional view along line 1B-1B'. In some embodiments, FIG. 1B It is along FIG. 1C The sectional view of line 1B-1B' in the diagram. It should be noted that, for clarity, FIG. 1D Some elements (e.g., conductive element 40 and dielectric layer 50) are omitted.

[0085] The semiconductor substrate 10 may include one or more active regions 10A defined by the isolation structure 20. In some embodiments, the active regions 10A of the semiconductor substrate 10 are adjacent to and defined by the isolation structure 20. The fabrication techniques of the semiconductor substrate 10 may be, or include, for example, silicon, doped silicon, silicon-germanium, silicon-on-insulator, silicon-on-sapphire, silicon-germanium-on-insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, indium phosphide, gallium indium phosphide, or any other group IV-IV, III-V, or I-VI semiconductor materials.

[0086] The fabrication technology of the isolation structure 20 may be or include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0087] The trench 30 may pass through the active region 10A and the isolation structure 20. In some embodiments, the trench 30 extends along a direction of extension along the Y-axis (or the Y direction) and has a width W1 along the X-axis (or the X direction). In some embodiments, the trench 30 has a sidewall 301 and a sidewall 302 opposite to the sidewall 301. The width W1 is the distance between the sidewall 301 and the sidewall 302. In some embodiments, the width W1 of the trench 30 is from about 20 nanometers (nm) to about 30 nanometers. In some embodiments, the trench 30 has a depth T1. In some embodiments, the depth T1 of the trench 30 is from about 20 nanometers to about 150 nanometers.

[0088] In some embodiments, the trench 30 includes one or more trench portions in one or more active regions 10A and one or more trench portions in the isolation structure 20. In some embodiments, the trench portions in the active regions 10A are connected to the trench portions in the isolation structure 20. In some embodiments, the trench portions in the active regions 10A have a length W4 along the extending direction (e.g., the Y-axis) of the trench 30. In some embodiments, the length W4 of the trench portions of the trench 30 in the active regions 10A is about 5 nanometers to about 30 nanometers.

[0089] In some embodiments, the active region 10A of the semiconductor substrate 10 may further include a doped region adjacent to the sidewalls 301 and 302 of the trench 30. This doped region may be adjacent to a trench portion of the trench 30 in the active region 10A. The doped region may be a source and / or drain region.

[0090] In some embodiments, the active region 10A of the semiconductor substrate 10 includes one or more fin structures 100 in the trench 30. In some embodiments, the fin structure 100 includes a body portion 120 and protrusions 110 and 130. In some embodiments, the body portion 120 is connected to the protrusions 110 and 130.

[0091] Reference FIG. 1B to FIG. 1D The main body portion 120 of the fin structure 100 may have an upper surface 121, a bottom surface 124 opposite to the upper surface 121, and inclined surfaces 122 and 123. In some embodiments, the area of ​​the upper surface 121 is smaller than the area of ​​the bottom surface 124. In some embodiments, the inclined surface 122 of the main body portion 120 extends from the upper surface 121 to the bottom surface 124. In some embodiments, the inclined surface 123 of the main body portion 120 extends from the upper surface 121 to the bottom surface 303 of the groove 30. In some embodiments, the inclined surface 123 of the main body portion 120 extends from the upper surface 121 to the bottom surface 303 of the groove 30.

[0092] In some embodiments, the upper surface 121 of the body portion 120 has a width W2 along the X-axis. In some embodiments, the ratio (W2 / W1) of the width W2 of the upper surface 121 of the body portion 120 to the width W1 of the groove 30 is equal to or greater than about 0.5. In some embodiments, the ratio (W2 / W1) of the width W2 of the upper surface 121 of the body portion 120 to the width W1 of the groove 30 is equal to or greater than about 0.6. In some embodiments, the ratio (W2 / W1) of the width W2 of the upper surface 121 of the body portion 120 to the width W1 of the groove 30 is equal to or greater than about 0.7. In some embodiments, the ratio (W2 / W1) of the width W2 of the upper surface 121 of the body portion 120 to the width W1 of the groove 30 is equal to or greater than about 0.8.

[0093] In some embodiments, the upper surface 121 of the body portion 120 has a length W3 along the extending direction (e.g., the Y-axis) of the groove 30. In some embodiments, the length W3 may extend along a direction (e.g., the Y-axis) that is substantially perpendicular to the extending direction of the width W2 (e.g., the X-axis). In some embodiments, the ratio (W3 / W4) of the length W3 of the upper surface 121 of the body portion 120 to the length W4 of the groove portion of the groove 30 in the active region 10A is equal to or greater than about 0.5. In some embodiments, the ratio (W3 / W4) of the length W3 of the upper surface 121 of the body portion 120 to the length W4 of the groove portion of the groove 30 in the active region 10A is equal to or greater than about 0.6. In some embodiments, the ratio (W3 / W4) of the length W3 of the upper surface 121 of the body portion 120 to the length W4 of the groove portion of the groove 30 in the active region 10A is equal to or greater than about 0.7. In some embodiments, the ratio (W3 / W4) of the length W3 of the upper surface 121 of the main body portion 120 to the length W4 of the groove portion of the groove 30 in the active region 10A is equal to or greater than about 0.8.

[0094] In some embodiments, the body portion 120 has a thickness T4. The thickness T4 of the body portion 120 may be defined by the vertical distance between the upper surface 121 and the bottom surface 124 of the body portion 120. In some embodiments, the thickness T4 is from about 10 nanometers to about 100 nanometers. In some embodiments, the ratio (T4 / T1) of the thickness T4 of the body portion 120 to the depth T1 of the trench 30 is equal to or less than about 0.5. In some embodiments, the ratio (T4 / T1) of the thickness T4 of the body portion 120 to the depth T1 of the trench 30 is equal to or less than about 0.4. In some embodiments, the ratio (T4 / T1) of the thickness T4 of the body portion 120 to the depth T1 of the trench 30 is equal to or less than about 0.3.

[0095] In some embodiments, the opening of the trench 30 may be spaced apart from the upper surface 121 of the body portion 120 by a certain distance T2. In some embodiments, the distance T2 is about 10 nanometers to about 100 nanometers.

[0096] In some embodiments, a portion of the isolation structure 20 is in the trench 30 and has an upper surface 201, and a slope 122 of the body portion 120 extends from the upper surface 121 of the body portion 120 to the upper surface 201 of the isolation structure 20 in the trench 30. In some embodiments, a slope 123 of the body portion 120 extends from the upper surface 121 of the body portion 120 to the upper surface 201 of the isolation structure 20 in the trench 30.

[0097] In some embodiments, a protrusion 110 of the fin structure 100 protrudes from the upper surface 121 of the body portion 120. In some embodiments, the protrusion 110 extends upward along the sidewall 301 of the groove 30. In some embodiments, the protrusion 110 includes a plurality of ramps (e.g., ramps 111, 112, and 113). In some embodiments, ramp 111 of the protrusion 110 is connected to the upper surface 121 of the body portion 120. In some embodiments, ramp 112 of the protrusion 110 is connected to ramp 122 of the body portion 120. In some embodiments, ramp 113 of the protrusion 110 is connected to ramp 123 of the body portion 120. In some embodiments, the protrusion 110 may be conical, or may include a conical portion. In some embodiments, the protrusion 110 is conical or has a conical shape.

[0098] In some embodiments, the protrusion 110 has a thickness T3. The thickness T3 of the protrusion 110 may be defined by the vertical distance between the bottommost and topmost surfaces or endpoints of the protrusion 110. The bottommost surface of the protrusion 110 may be at the same height as the upper surface 121 of the body portion 120. In some embodiments, the thickness T3 of the protrusion 110 is from about 5 nanometers to about 50 nanometers. In some embodiments, the ratio (T3 / T2) of the thickness T3 of the protrusion 110 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 is equal to or less than about 0.5. In some embodiments, the ratio (T3 / T2) of the thickness T3 of the protrusion 110 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 is equal to or less than about 0.4. In some embodiments, the ratio (T3 / T2) of the thickness T3 of the protrusion 110 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 is equal to or less than about 0.3.

[0099] In some embodiments, a protrusion 130 of the fin structure 100 protrudes from the upper surface 121 of the body portion 120. In some embodiments, the protrusion 130 extends upward along the sidewall 302 of the groove 30. In some embodiments, the protrusion 130 includes a plurality of ramps (e.g., ramps 131, 132, and 133). In some embodiments, the ramp 131 of the protrusion 130 faces the ramp 111 of the protrusion 110. In some embodiments, the ramp 131 of the protrusion 130 is connected to the upper surface 121 of the body portion 120. In some embodiments, the ramp 132 of the protrusion 130 is connected to the ramp 122 of the body portion 120. In some embodiments, the ramp 133 of the protrusion 130 is connected to the ramp 123 of the body portion 120. In some embodiments, the protrusion 130 may be conical, or may include a conical portion. In some embodiments, the protrusion 130 is conical or has a conical shape.

[0100] In some embodiments, the protrusion 130 has a thickness T5. The thickness T5 of the protrusion 130 may be defined by the vertical distance between the bottommost and topmost surfaces or endpoints of the protrusion 130. The bottommost surface of the protrusion 130 may be at the same height as the upper surface 121 of the body portion 120. In some embodiments, the thickness T5 of the protrusion 130 is from about 5 nanometers to about 50 nanometers. In some embodiments, the ratio (T5 / T2) of the thickness T5 of the protrusion 130 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 is equal to or less than about 0.5. In some embodiments, the ratio (T5 / T2) of the thickness T5 of the protrusion 130 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 is equal to or less than about 0.4. In some embodiments, the ratio (T5 / T2) of the thickness T5 of the protrusion 130 to the distance T2 between the opening of the trench 30 and the upper surface 121 of the body portion 120 is equal to or less than about 0.3.

[0101] In some embodiments, protrusions 110 and 130 are located on two opposite sides of the upper surface 121 of the body portion 120. In some embodiments, protrusions 110 and 130 project in the same direction or orientation (e.g., along the Z-axis). In some embodiments, the inclined surface 112 of protrusion 110, the inclined surface 132 of protrusion 130, and the inclined surface 122 of the body portion 120 form a continuous plane or surface. In some embodiments, the inclined surface 113 of protrusion 110, the inclined surface 133 of protrusion 130, and the inclined surface 123 of the body portion 120 form a continuous plane or surface.

[0102] Conductive elements 40 may be disposed on protrusions 110 of the fin structure 100 in the trench 30. In some embodiments, conductive elements 40 are disposed on protrusions 110 and 130 of the fin structure 100 in the trench 30. In some embodiments, conductive elements 40 are disposed on the body portion 120 of the fin structure 100 and protrusions 110 and 130 in the trench 30. In some embodiments, conductive elements 40 are conformally formed on the slopes (e.g., slopes 111, 112, and 113) of the protrusion 110. In some embodiments, conductive elements 40 completely cover the slopes (e.g., slopes 111, 112, and 113) of the protrusion 110. In some embodiments, conductive elements 40 are conformally formed on the slopes (e.g., slopes 131, 132, and 133) of the protrusion 130. In some embodiments, conductive elements 40 completely cover the slopes (e.g., slopes 131, 132, and 133) of the protrusion 130. In some embodiments, the conductive element 40 is conformally formed on the inclined surfaces (e.g., inclined surfaces 122 and 123) of the body portion 120. In some embodiments, the conductive element 40 comprises a conductive material, such as doped polysilicon, a metal, or a metal silicide. The metal may be, for example, aluminum, copper, tungsten, cobalt, or an alloy thereof. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. In some embodiments, the conductive element 40 may be or include a word line.

[0103] A dielectric layer 50 may be disposed between the conductive element 40 and the protrusions 110 of the fin structure 100. In some embodiments, the dielectric layer 50 is disposed between the conductive element 40 in the trench 30 and the protrusions 110 and 130 of the fin structure 100. In some embodiments, the dielectric layer 50 is disposed between the conductive element 40 in the trench 30 and the body portion 120 and the protrusions 110 and 130 of the fin structure 100. In some embodiments, the dielectric layer 50 is conformally formed on the slopes (e.g., slopes 111, 112, and 113) of the protrusion 110. In some embodiments, the dielectric layer 50 completely covers the slopes (e.g., slopes 111, 112, and 113) of the protrusion 110. In some embodiments, the dielectric layer 50 is conformally formed on the slopes (e.g., slopes 131, 132, and 133) of the protrusion 130. In some embodiments, the dielectric layer 50 completely covers the bevels of the protrusion 130 (e.g., bevels 131, 132, and 133). In some embodiments, the dielectric layer 50 is conformally formed on the bevels of the body portion 120 (e.g., bevels 122 and 123). In some embodiments, the dielectric layer 50 may be or include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorinated silicates, or a high-k material. In some embodiments, the dielectric layer 50 may be or include, barium strontium titanate, lead zirconate titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, etc. In some embodiments, the dielectric layer 50 may be or include a word line insulating layer.

[0104] In some embodiments, in the design of the fin structure 100, the subthreshold swing of the cell transistor in the semiconductor structure 1 can be reduced by about 10 mV / dec to about 20 mV / dec. In some embodiments, in the design of the fin structure 100, the subthreshold swing of the cell transistor in the semiconductor structure 1 can be reduced by about 10% to about 20%. In some embodiments, in the design of the fin structure 100, the threshold voltage of the cell transistor in the semiconductor structure 1 can be reduced by about 20 millivolts (mV). Therefore, gate control of the cell transistor in the semiconductor structure 1 can be increased, channel formation time can be reduced, and thus the switching speed of the cell transistor in the semiconductor structure 1 can be increased. Furthermore, current leakage can be mitigated or prevented, thereby improving the electrical performance of the semiconductor structure 1.

[0105] According to some embodiments of this disclosure, in the design of the fin structure 100, a protrusion 110 extending upward along the sidewall 301 of the trench 30 is included. The protrusion 110 provides an extension of the fin structure 100, which can be further covered by the conductive element 40. Since the electric field is relatively high near the sidewall 301 of the trench 30 (i.e., the location of the doped region or the source / drain region of the unit transistor), the protrusion 110 covered by the conductive element 40 can increase the area covered by the conductive element 40 (i.e., the gate control region). Therefore, an additional gate control region can be created, and gate control of the semiconductor structure (i.e., the transistor) channel can be improved.

[0106] Furthermore, if the upper surface 121 of the main body portion 120 of the fin structure 100 is too small, the space for filling the conductive element 40 in the trench 30 and contacting it with the fin structure 100 may be relatively insufficient, thus the resistance of the conductive element 40 may unintentionally increase. Conversely, according to some embodiments of this disclosure, at the aforementioned ratio (W2 / W1) of the width W2 of the upper surface 121 of the main body portion 120 to the width W1 of the trench 30, for example, at least equal to or greater than about 0.5, the formed conductive element 40 can have sufficient volume and width. Therefore, the resistance of the conductive element 40 will not unintentionally increase, and the conductivity of the conductive element 40 can be protected from adverse effects.

[0107] FIG. 2A , FIG. 2B , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 7A and FIG. 8B The various stages of a method for fabricating a semiconductor structure 1 according to some embodiments of this disclosure are illustrated.

[0108] FIG. 2A and FIG. 2B This illustrates a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 2B It is along FIG. 2A The sectional view of line 2B-2B' in the diagram.

[0109] A semiconductor substrate 10 having an active region 10A can be provided. The semiconductor substrate 10 can be fabricated using, for example, silicon, doped silicon, silicon-germanium, silicon-on-insulator, silicon-on-sapphire, silicon-germanium-on-insulator, silicon carbide, germanium, gallium arsenide, gallium phosphide, gallium arsenide phosphide, indium phosphide, gallium indium phosphide, or any other group IV-IV, III-V, or I-VI semiconductor material.

[0110] A photolithography process can be performed to pattern the semiconductor substrate 10 to define the locations of multiple active regions 10A. Following this photolithography process, an etching process can be performed to form multiple trenches in the semiconductor substrate 10.

[0111] FIG. 3A and FIG. 3B This illustrates a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 3B It is along FIG. 3A The sectional view of line 3B-3B' in the diagram.

[0112] An isolation structure 20 can be formed in the semiconductor substrate 10, and multiple active regions 10A of the semiconductor substrate 10 can be defined by the isolation structure 20.

[0113] After etching to form multiple trenches in the semiconductor substrate 10, an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or fluorinated silicate, can be used to fill the multiple trenches of the semiconductor substrate 10 by a deposition process. After the deposition process, a planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent process steps, and to conformally form the isolation structure 20 and the multiple active regions 10A.

[0114] FIG. 4A and FIG. 4B This illustrates a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 4B It is along FIG. 4A The sectional view of line 4B-4B' in the diagram.

[0115] A patterned photoresist layer PR can be formed on the isolation structure 20 and the active region 10A of the semiconductor substrate 10. A photoresist layer can be coated on the isolation structure 20 and the active region 10A of the semiconductor substrate 10, and then the photoresist layer can be exposed and developed to form a patterned photoresist layer PR with multiple openings to expose portions of the isolation structure 20 and the active region 10A of the semiconductor substrate 10. The patterned photoresist layer PR can have a predetermined pattern for forming trenches (e.g., trench 30, discussed below) through the active region 10A and the isolation structure 20. The openings of the patterned photoresist layer PR correspond to the locations where the trenches (e.g., trench 30, discussed below) are subsequently formed through the active region 10A and the isolation structure 20.

[0116] FIG. 5A and FIG. 5B This illustrates a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 5B It is along FIG. 5A The sectional view is shown along line 5B-5B'. It should be noted that, for clarity, FIG. 5A The patterned photoresist layer PR is omitted in the text.

[0117] In some embodiments, a portion of the active region 10A of the semiconductor substrate 10 is removed to form a trench 30A and an initial fin structure 100A within the trench 30A. In some embodiments, the active region 10A and the isolation structure 20 are etched through openings in a patterned photoresist layer PR to form one or more trenches 30A penetrating the active region 10A and the isolation structure 20. In some embodiments, anisotropic etching operations may be performed to form the trench 30A and the initial fin structure 100A therein. In some embodiments, anisotropic dry etching is performed on the active region 10A of the semiconductor substrate 10 using a reactive ion etching (RIE) process to form the trench 30A and the initial fin structure 100A within the trench 30A.

[0118] In some embodiments, the initial fin structure 100A has a planar upper surface 100A1. In some embodiments, the initial fin structure 100A has one or more side surfaces (e.g., side surface 100A2) that are substantially perpendicular to the upper surface 100A1 of the initial fin structure 100A.

[0119] In some embodiments, the trench 30A extends through the isolation structure 20. In some embodiments, the opening of the trench 30A is spaced apart from the upper surface 100A1 of the initial fin structure 100A by a certain distance T6, which in some embodiments is about 5 nanometers to about 50 nanometers.

[0120] FIG. 6A and FIG. 6BThis illustrates a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 6B It is along FIG. 6A The sectional view of line 6B-6B' in the diagram. It should be noted that, for clarity, FIG. 6A The patterned photoresist layer PR is omitted in the text.

[0121] In some embodiments, a portion of the initial fin structure 100A is removed to form the fin structure 100 in the trench 30. In some embodiments, the formed fin structure 100 includes a body portion 120 and protrusions 110 and 130. In some embodiments, an isotropic etching operation may be performed to form the fin structure 100.

[0122] In some embodiments, an isotropic etching process is used to etch the initial fin structure 100A using a dry etching process or a wet etching process to form the fin structure 100 in the trench 30. In some embodiments, the isotropic etching operation has relatively high etch selectivity between the semiconductor substrate 10 and the isolation structure 20, so that the isolation structure 20 is only slightly etched or not etched at all in the isotropic etching operation.

[0123] In some embodiments, trench 30A, the initial fin structure 100A in trench 30A, and the fin structure 100 in trench 30 can be formed by etching based on the same patterned photoresist layer PR. In some embodiments, the isotropic etching operation is performed after an anisotropic etching operation is performed on the active region of the semiconductor substrate.

[0124] In some embodiments, the fin structure 100 includes a body portion 120 and protrusions 110 and 130. In some embodiments, the body portion 120 is connected to the protrusions 110 and 130.

[0125] In some embodiments, the main body portion 120 of the fin structure 100 may have an upper surface 121, a bottom surface 124 opposite to the upper surface 121, and inclined surfaces 122 and 123. In some embodiments, the area of ​​the upper surface 121 is smaller than the area of ​​the bottom surface 124. In some embodiments, the inclined surface 122 of the main body portion 120 extends from the upper surface 121 to the bottom surface 124. In some embodiments, the inclined surface 123 of the main body portion 120 extends from the upper surface 121 to the bottom surface 303 of the trench 30. In some embodiments, the inclined surface 123 of the main body portion 120 extends from the upper surface 121 to the bottom surface 303 of the trench 30.

[0126] In some embodiments, the trench 30 extends further through the isolation structure 20. In some embodiments, a portion of the isolation structure 20 is in the trench 30 and has an upper surface 201, and a slope 122 of the body portion 120 extends from the upper surface 121 of the body portion 120 to the upper surface 201 of the isolation structure 20 in the trench 30. In some embodiments, a slope 123 of the body portion 120 extends from the upper surface 121 of the body portion 120 to the upper surface 201 of the isolation structure 20 in the trench 30.

[0127] In some embodiments, a protrusion 110 of the fin structure 100 protrudes from the upper surface 121 of the body portion 120. In some embodiments, the protrusion 110 extends upward along the sidewall 301 of the groove 30. In some embodiments, the protrusion 110 includes a plurality of ramps (e.g., ramps 111, 112, and 113). In some embodiments, ramp 111 of the protrusion 110 is connected to the upper surface 121 of the body portion 120. In some embodiments, ramp 112 of the protrusion 110 is connected to ramp 122 of the body portion 120. In some embodiments, ramp 113 of the protrusion 110 is connected to ramp 123 of the body portion 120. In some embodiments, the protrusion 110 may be conical, or may include a conical portion. In some embodiments, the protrusion 110 has a conical shape.

[0128] In some embodiments, a protrusion 130 of the fin structure 100 protrudes from the upper surface 121 of the body portion 120. In some embodiments, the protrusion 130 extends upward along the sidewall 302 of the groove 30. In some embodiments, the protrusion 130 includes a plurality of ramps (e.g., ramps 131, 132, and 133). In some embodiments, the ramp 131 of the protrusion 130 faces the ramp 111 of the protrusion 110. In some embodiments, the ramp 131 of the protrusion 130 is connected to the upper surface 121 of the body portion 120. In some embodiments, the ramp 132 of the protrusion 130 is connected to the ramp 122 of the body portion 120. In some embodiments, the ramp 133 of the protrusion 130 is connected to the ramp 123 of the body portion 120. In some embodiments, the protrusion 130 may be conical, or may include a conical portion. In some embodiments, the protrusion 130 has a conical shape.

[0129] In some embodiments, protrusions 110 and 130 are located on opposite sides of the upper surface 121 of the body portion 120. In some embodiments, protrusions 110 and 130 project in the same direction or orientation (e.g., along the Z-axis). In some embodiments, the inclined surface 112 of protrusion 110, the inclined surface 132 of protrusion 130, and the inclined surface 122 of the body portion 120 form a continuous plane or surface. In some embodiments, the inclined surface 113 of protrusion 110, the inclined surface 133 of protrusion 130, and the inclined surface 123 of the body portion 120 form a continuous plane or surface.

[0130] FIG. 7A and FIG. 7B This illustrates a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 7B It is along FIG. 7A The sectional view of line 7B-7B' in the diagram. It should be noted that, for clarity, FIG. 7A The patterned photoresist layer PR is omitted in the text.

[0131] In some embodiments, the dielectric layer 50 is conformally formed on the sidewalls 301 and 302 of the fin structure 100 and the trench 30.

[0132] In some embodiments, a dielectric layer 50 is deposited on the fin structure 100. In some embodiments, the dielectric layer 50 is deposited on the fin structure 100 using a CVD process, an ALD process, or a similar process. In some embodiments, the dielectric layer 50 deposited on the top surface of the patterned photoresist layer PR can be removed using, for example, an etching process, while the dielectric layer 50 deposited on the sidewalls 301 and 302 of the trench 30 remains in place. In other embodiments, the dielectric layer 50 can be grown on the exposed portions of the substrate 10 (i.e., the sidewalls 301 and 302 of the trench 30) using a thermal oxidation process.

[0133] In some embodiments, the dielectric layer 50 may be fabricated using techniques such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorinated silicates, or a high-k material. In some embodiments, the dielectric layer 50 may be fabricated using techniques such as barium strontium titanate, lead zirconate titanate, titanium oxide, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, etc.

[0134] FIG. 8A and FIG. 8B This illustrates a stage of a method for fabricating a semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, FIG. 8B It is along FIG. 8A The sectional view of line 8B-8B' in the middle.

[0135] In some embodiments, conductive elements 40 are conformally formed on the main body portion 120 and protrusions 110 and 130 of the fin structure 100 and the sidewalls 301 and 302 of the trench 30. In some embodiments, conductive elements 40 are conformally formed on the dielectric layer 50 of the trench 30.

[0136] In some embodiments, conductive element 40 is deposited on dielectric layer 50. In some embodiments, conductive element 40 is formed on dielectric layer 50 using CVD, PVD, or ALD. In some embodiments, patterned photoresist layer PR is removed. In some embodiments, patterned photoresist layer PR is removed by an ashing or stripping process.

[0137] In some embodiments, the conductive element 40 includes a conductive material, such as doped polycrystalline silicon, a metal, or a metal silicide. The metal may be, for example, aluminum, copper, tungsten, cobalt, or an alloy thereof. The metal silicide may be, for example, nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or similar materials.

[0138] FIG. 9 This is a flowchart illustrating a method 90 for fabricating a semiconductor structure according to some embodiments of this disclosure.

[0139] The fabrication method 90 begins with operation S91, in which a semiconductor substrate is provided having an active region.

[0140] The fabrication method 90 continues to operate S92, wherein a portion of the active region of the semiconductor substrate is removed to form a trench and an initial fin structure in the trench.

[0141] Preparation method 90 continues in operation S93, wherein a portion of the initial fin structure is removed to form a fin structure. The fin structure includes a first protrusion extending upward along a first sidewall of the groove.

[0142] The preparation method 90 is merely illustrative and is not intended to limit the scope of this disclosure beyond that expressly mentioned in the claims. Additional operations may be provided before, during, or after each operation of the preparation method 90, and some of these operations may be replaced, eliminated, or moved for additional embodiments of the preparation method. In some embodiments, the preparation method 90 may further include… FIG. 9 Operations not described herein. In some embodiments, the preparation method may include 90 steps. FIG. 9 One or more operations described in the text.

[0143] One embodiment of this disclosure provides a semiconductor structure including a semiconductor substrate. The semiconductor substrate has an active region defined by an isolation structure. A trench passes through the active region and the isolation structure. The active region of the semiconductor substrate includes a fin structure in the trench. The fin structure includes a first protrusion extending upward along a first sidewall of the trench.

[0144] Another embodiment of this disclosure provides a semiconductor structure including a semiconductor substrate and a conductive element. The semiconductor substrate has an active region including a fin structure. The fin structure includes a body portion and a first tapered portion. The first tapered portion protrudes from an upper surface of the body portion. The conductive element is disposed on the body portion and the first tapered portion of the fin structure.

[0145] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an active region. The method further includes removing a portion of the active region of the semiconductor substrate to form a trench and an initial fin structure. The method also includes removing a portion of the initial fin structure to form a fin structure including a first protrusion extending upwardly along a first sidewall of the trench.

[0146] When designing a fin structure including protrusions extending upwards along the trench sidewalls, these protrusions can provide an extension of the fin structure that can be further covered by conductive elements. Since the electric field is relatively high near the trench sidewalls (i.e., the location of the doped region or the source / drain region of a unit transistor), the protrusions covered by conductive elements can increase the area covered by the conductive elements (i.e., the gate control region). Therefore, additional gate control regions can be created, and gate control of the semiconductor structure (i.e., the transistor) channel can be improved.

[0147] While this disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined by the scope of the disclosed patent. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0148] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the content of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the patent disclosure of this invention.

Claims

1. A semiconductor structure, comprising: A semiconductor substrate having an active region defined by an isolation structure, and a trench passing through the active region and the isolation structure; The active region of the semiconductor substrate includes a fin structure in a trench, and the fin structure includes a first protrusion extending upward along a first sidewall of the trench. The fin structure includes a main body portion connected to the first protrusion, and the first protrusion protruding from an upper surface of the main body portion; the groove has a first width along a first direction, the upper surface of the main body portion has a second width along the first direction, and the ratio of the second width to the first width is equal to or greater than 0.

5.

2. The semiconductor structure of claim 1, wherein the main body portion has a bottom surface opposite the upper surface, and an area of ​​the upper surface is smaller than an area of ​​the bottom surface.

3. The semiconductor structure of claim 1, wherein the main body portion has a bevel extending from the upper surface to a bottom surface of the trench.

4. The semiconductor structure of claim 3, wherein the first protrusion has a first inclined surface connected to the upper surface of the main body portion, and a second inclined surface connected to the inclined surface of the main body portion.

5. The semiconductor structure of claim 1, wherein the first protrusion of the fin structure has a tapered shape.

6. The semiconductor structure of claim 1, wherein the fin structure further comprises: A second protrusion extends along a second sidewall opposite to the first sidewall of the groove.

7. The semiconductor structure of claim 1, further comprising: A conductive element is disposed on the first protrusion of the fin structure in the trench.

8. The semiconductor structure of claim 7, further comprising: A dielectric layer is disposed between the conductive element and the first protrusion of the fin structure.

9. A semiconductor structure, comprising: A semiconductor substrate having an active region including a fin structure, the fin structure comprising: One main body; and A first conical portion protrudes from an upper surface of the main body portion; and A conductive element is disposed on the main body portion and the first conical portion of the fin structure; One of the grooves passes through the active region, and the fin structure is located in the groove; the groove has a first width along a first direction, the upper surface of the main body portion has a second width along the first direction, and the ratio of the second width to the first width is equal to or greater than 0.

5.

10. The semiconductor structure of claim 9, further comprising: An isolation structure defines the active region, wherein the trench extends through the isolation structure.

11. The semiconductor structure of claim 10, wherein a portion of the isolation structure in the trench has an upper surface, and the body portion of the fin structure has a ramp extending from the upper surface of the body portion to the upper surface of the isolation structure in the trench.

12. The semiconductor structure of claim 9, further comprising: A dielectric layer is disposed between the conductive element and the first tapered portion of the fin structure.

13. The semiconductor structure of claim 12, wherein the first tapered portion includes a plurality of inclined surfaces connected to the main body portion.

14. The semiconductor structure of claim 13, wherein the dielectric layer is conformally formed on the plurality of inclined surfaces of the first tapered portion.

15. The semiconductor structure of claim 9, wherein the first tapered portion includes a plurality of inclined surfaces connected to the main body portion, and the conductive element is conformally formed on the plurality of inclined surfaces of the first tapered portion.

16. The semiconductor structure of claim 9, wherein the main body portion of the fin structure has a first inclined surface and a second inclined surface extending from the upper surface of the main body portion to a bottom surface of the main body portion.

17. The semiconductor structure of claim 16, wherein the conductive element is conformally formed on the first and second inclined surfaces of the body portion.

18. A method for fabricating a semiconductor structure, comprising: A semiconductor substrate is provided, having an active region; A fin-like structure is formed in the active region, the fin-like structure comprising: One main body; and A first conical portion protrudes from an upper surface of the main body portion; and A conductive element is formed on the main body portion and the first conical portion of the fin-shaped structure; A trench is formed through the active region, and the fin structure is located in the trench. The trench has a first width along a first direction, and the upper surface of the main body portion has a second width along the first direction. The ratio of the second width to the first width is equal to or greater than 0.

5.

19. The method for preparing the semiconductor structure as described in claim 18, further comprising: An isolation structure is formed that defines the active region, wherein the trench extends through the isolation structure.

20. The method of fabricating a semiconductor structure as claimed in claim 19, wherein a portion of the isolation structure in the trench has an upper surface, and the main body portion of the fin structure has a slope extending from the upper surface of the main body portion to the upper surface of the isolation structure in the trench.

21. The method for preparing the semiconductor structure as described in claim 18, further comprising: A dielectric layer is formed between the conductive element and the first tapered portion of the fin structure.

22. The method for fabricating a semiconductor structure as claimed in claim 21, wherein the first tapered portion includes a plurality of inclined surfaces connected to the main body portion.

23. The method for fabricating a semiconductor structure as claimed in claim 22, wherein the dielectric layer is conformally formed on the plurality of inclined surfaces of the first tapered portion.

24. The method for fabricating a semiconductor structure as claimed in claim 18, wherein the first tapered portion includes a plurality of inclined surfaces connected to the main body portion, and the conductive element is conformally formed on the plurality of inclined surfaces of the first tapered portion.

25. The method for fabricating a semiconductor structure as claimed in claim 18, wherein the main body portion of the fin structure has a first inclined surface and a second inclined surface extending from the upper surface of the main body portion to a bottom surface of the main body portion.

26. The method for fabricating a semiconductor structure as claimed in claim 25, wherein the conductive element is conformally formed on the first inclined surface and the second inclined surface of the main body portion.

27. A method for fabricating a semiconductor structure, comprising: A semiconductor substrate is provided, having an active region; A portion of the active region of the semiconductor substrate is removed to form a trench and an initial fin structure in the trench; as well as A portion of the initial fin structure is removed to form a fin structure including a first protrusion extending upward along a first sidewall of the groove; The fin structure includes a main body portion connected to the first protrusion, and the first protrusion protruding from an upper surface of the main body portion; the groove has a first width along a first direction, the upper surface of the main body portion has a second width along the first direction, and the ratio of the second width to the first width is equal to or greater than 0.

5.

28. The method of fabricating a semiconductor structure as claimed in claim 27, wherein the formation of the trench and the initial fin structure in the trench, and the formation of the fin structure, are performed by etching based on the same patterned photoresist layer.

29. The method for fabricating a semiconductor structure as claimed in claim 27, wherein the formation of the trench and the initial fin structure in the trench is performed by an anisotropic etching operation.

30. The method for preparing the semiconductor structure as described in claim 29, further comprising: An isolation structure is formed that defines the active region, wherein the trench extends through the isolation structure.

31. The method of fabricating a semiconductor structure as claimed in claim 27, wherein the formation of the fin structure, the fin structure including the first protrusion extending upward along the first sidewall of the trench, is performed by an isotropic etching operation.

32. The method for preparing the semiconductor structure according to claim 31, further comprising: An isolation structure is formed that defines the active region, wherein the trench extends through the isolation structure, and the fin structure has a ramp extending from an upper surface to an upper surface of the isolation structure in the trench.

33. The method for fabricating a semiconductor structure as claimed in claim 27, wherein forming the initial fin structure includes performing an anisotropic etching operation on the active region of the semiconductor substrate, and forming the fin structure includes performing an isotropic etching operation on the active region of the semiconductor substrate after performing the anisotropic etching operation.

34. The method for preparing the semiconductor structure as described in claim 27, further comprising: A conductive element is conformally formed on the first protrusion of the fin structure and the first sidewall of the groove.

35. The method for preparing the semiconductor structure as described in claim 27, further comprising: A dielectric layer is conformally formed on the first sidewall of the fin structure and the trench.

36. The method for preparing the semiconductor structure as described in claim 35, further comprising: A conductive element is conformally formed on the dielectric layer in the trench.

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