Printed circuit substrate, printed circuit, and method for manufacturing printed circuit substrate

Abstract

Disclosed is a substrate for printed circuits, which comprises a base film having polyimide as a main component and a conductor layer formed on at least one side of the base film, the conductor layer having a metal sintered layer formed on the base film and an electrolysis-free plating layer formed on the metal sintered layer, wherein the number of voids having a maximum width of 5 μm or more in plan view in the base film is 10 or less per 0.25 mm 2 of the reference unit area on the surface of the base film.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a substrate for printed circuit, a printed circuit, and a method for manufacturing a substrate for printed circuit. This application claims priority from Japanese Application No. 2020-171170 filed on October 9, 2020, and the entire content of said Japanese Application is incorporated herein by reference. BACKGROUND

[0002] Patent Literature 1 discloses a substrate for printed circuit provided with a base film having polyimide as a main component and a conductive layer.

[0003] The conductive layer of Patent Literature 1 has a first conductive layer formed by coating and firing of a conductive ink containing metal particles and a second conductive layer formed by electroless plating on one surface side of the first conductive layer.

[0004] The method for manufacturing a substrate for printed circuit of Patent Literature 1 has a process of forming a first conductive layer by coating a conductive ink on one surface side of a base film and firing; a process of forming a second conductive layer on the surface of the first conductive layer by performing electroless plating with palladium as a catalyst after the first conductive layer is formed; and a process of dispersing palladium in the base film by heat treatment after the electroless plating.

[0005] In Patent Literature 1, the process of forming a second conductive layer by electroless plating has a process of adsorbing palladium to the first conductive layer; and a process of causing a metal such as copper, which becomes the second conductive layer, to deposit on the surface of the first conductive layer by immersing a laminate in which the first conductive layer is formed in an electroless plating solution.

[0006] PRIOR ART DOCUMENTS

[0007] PATENT LITERATURE

[0008] Patent Literature 1: Japanese Patent Application Publication No. 2016-119424 SUMMARY

[0009] One aspect of the present disclosure is a substrate for printed circuit. The disclosed substrate has a base film having polyimide as a main component and a conductor layer formed on at least one surface side of the base film, the conductor layer having a metal sintered layer formed on the base film and an electroless plated layer formed on the metal sintered layer, and in the base film, the number of voids having a maximum width of 5 μm or more in plan view is 10 or less per 0.25 mm 2 of a reference unit area on the surface of the base film.

[0010] Another aspect of the present disclosure is a printed circuit. The disclosed printed circuit has a base film having polyimide as a main component and a conductive pattern formed on at least one surface side of the base film, the conductive pattern having a minimum conductor width and a minimum conductor interval, either or both of which is 20 μm or less, the conductive pattern including a metal sintered layer formed on the base film and an electrolysis-free plating layer formed on the metal sintered layer, in the base film, the number of voids having a maximum width of 5 μm or more in plan view is 10 or less per 0.25 mm 2 of the reference unit area on the surface of the base film.

[0011] Another aspect of the present disclosure is a method for manufacturing a base material for a printed circuit. The disclosed manufacturing method has a step of forming a first conductor layer as a metal sintered layer on one surface side of a base film having polyimide as a main component and a step of forming a second conductor layer on the first conductor layer by electrolysis-free plating using a catalyst, the step of forming the second conductor layer including electrolysis assistance in which a conductor that becomes the catalyst is precipitated from an electrolysis-free plating solution onto the first conductor layer by applying an electric potential to the first conductor layer in the electrolysis-free plating solution. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a schematic cross-sectional view of a base material for a printed circuit according to an embodiment.

[0013] Figure 2 is a flowchart showing a method for manufacturing a base material for a printed circuit according to an embodiment.

[0014] Figure 3 is a schematic plan view showing an electrolysis-free plating device.

[0015] Figure 4 is a schematic cross-sectional view of a printed circuit.

[0016] Figure 5 is a schematic cross-sectional view of an inner wall and surroundings of a via included in a base film.

[0017] Figure 6 is a flowchart showing a method for manufacturing a base material for a printed circuit according to a reference example.

[0018] Figure 7 is a schematic cross-sectional view of a base material for a printed circuit according to a reference example.

[0019] Figure 8 is an enlarged cross-sectional view of a void generation site in a base material for a printed circuit according to a reference example.

[0020] Figure 9 is a schematic cross-sectional view of a via formed by etching fromFigure 8 An enlarged sectional view of the base film after the circuit-use base material is shown with the conductor layer removed.

[0021] Figure 10 An enlarged view (schematic view) of a void generation site on the surface of the base film. DETAILED DESCRIPTION

[0022] [Technical Problem to be Solved by the Present Disclosure]

[0023] As shown in Patent Document 1, when a conductive layer is formed by electroless plating, a void can be generated in a base film in which polyimide is the main component. The void is a cavity generated inside the base film. The void is formed near the interface between the base film and the conductive layer, and causes the surface of the base film to locally swell.

[0024] The present inventors have found that the void present on the base film can cause a circuit defect in a printed circuit having a fine pattern. The void is about several μm, which is relatively small. Therefore, in the case of a general printed circuit in which the conductor width or the conductor interval of the conductive pattern is sufficiently large compared to the void, the presence of the void hardly becomes a problem. However, in the case of a fine pattern, since the conductor width or the conductor interval is fine, a circuit defect can occur due to the presence of the void. For example, in the case where the size of the void is the same degree as or more than the narrow conductor width, if a conductor is present on the surface of the base film that swells due to the void, the conductor can peel off, and a conduction defect can occur. In addition, an insulation defect between the conductors can occur due to the peeling of the conductors.

[0025] Therefore, in a circuit-use base material for a fine pattern printed circuit that has a base film in which polyimide is the main component and an electroless plating layer, it is desirable to suppress a circuit defect.

[0026] [Effects of the Present Disclosure]

[0027] According to the present disclosure, a circuit defect of a fine pattern printed circuit can be suppressed.

[0028] [Explanation of Embodiments of the Present Disclosure]

[0029] (1) A circuit-use base material according to an embodiment has a base film in which polyimide is the main component, and a conductor layer formed on at least one side of the base film, the conductor layer having a metal sintered layer formed on the base film, and an electroless plating layer formed on the metal sintered layer, and in the base film, the number of voids having a maximum width of 5 μm or more in a plan view is 0.5 or less per 0.25 mm 210 or less per a reference unit area. In particular, when the base material for a printed circuit according to the embodiments is used for a printed circuit of a fine pattern (for example, either one or both of a minimum conductor width and a minimum conductor interval is 20 μm or less), the number of gaps in which circuit failure is likely to occur is small, and thus circuit failure in the printed circuit of the fine pattern can be suppressed. Here, the fine pattern has both of a minimum conductor width of 20 μm or less and a minimum conductor interval of 20 μm or less.

[0030] Hereinafter, "gap" described in the present specification means a gap formed in the base film near the interface between the base film and the conductor layer, unless otherwise specified.

[0031] (2) The conductor layer can further have a plating layer or a metal foil layer on the electroless plating layer. The electroless plating layer can further have a plating layer or a metal foil layer. By forming the plating layer or the metal foil layer, adjustment of the thickness of the entire conductor layer can be easily and accurately performed. The metal foil layer can be an extremely thin metal foil layer, for example, an extremely thin copper foil layer.

[0032] (3) The number of gaps can be 5 or less per a reference unit area. Since the number of gaps is further reduced, circuit failure can be further suppressed.

[0033] (4) The base film does not contain palladium. The "base film does not contain palladium" means that the base film does not contain palladium at all or that the base film does not substantially contain palladium. The "base film does not substantially contain palladium" means that the base film does not contain palladium except for an unavoidable amount. The unavoidable amount is, for example, an amount of 0.05 ppm or more and 10 ppm or less, which is obtained by cutting the surface of the base film on the conductor layer side and performing ICP analysis. By not containing palladium, the generation of gaps in the base film can be suppressed.

[0034] (5) The height of the surface of the base film at a site where the gap is present in the base film can be 1.5 μm or more relative to the height of the surface of the base film at a site where the gap is not present. If the height of the gap is 1.5 μm or more, circuit failure is likely to occur due to the gap, but as described above, since the number of gaps is small, circuit failure can be appropriately suppressed. Here, the height of the gap is measured by observing the surface of the base film from which the conductor layer is removed using a laser microscope.

[0035] (6) The printed circuit according to the embodiment includes a base film having polyimide as a main component and a conductive pattern formed on at least one surface side of the base film, the conductive pattern having a minimum conductor width and a minimum conductor interval, either or both of which is 20 μm or less, the conductive pattern including a metal sintered layer formed on the base film and an electrolysis-free plating layer formed on the metal sintered layer, and in the base film, the number of voids each having a maximum width of 5 μm or more in plan view is 10 or less per 0.25 mm 2 of the reference unit area on the surface of the base film. By reducing the number of voids that can cause circuit failure, circuit failure in a fine pattern printed circuit can be suppressed.

[0036] (7) In the printed circuit according to the embodiment, either or both of the minimum conductor width and the minimum conductor interval is 15 μm or less. By reducing the number of voids that can cause circuit failure, circuit failure in a fine pattern printed circuit can be suppressed.

[0037] (8) The base film has a through hole that penetrates in the thickness direction.

[0038] (9) The method for manufacturing a printed circuit substrate according to the embodiment includes a step of forming a first conductor layer as a metal sintered layer on one surface side of a base film having polyimide as a main component and a step of forming a second conductor layer on the first conductor layer by electrolysis-free plating using a catalyst, and the step of forming the second conductor layer includes electrolysis assistance in which a conductor that becomes the catalyst is precipitated from an electrolysis-free plating solution onto the first conductor layer by applying an electric potential to the first conductor layer in the electrolysis-free plating solution.

[0039] [Details of the Embodiments of the Present Disclosure]

[0040] Details of the embodiments of the present disclosure will be described below with reference to the drawings.

[0041] [Printed Circuit Substrate]

[0042] Figure 1 The printed circuit substrate 200 illustrated in the drawing includes a base film 1 having insulating properties and a conductor layer 2 laminated on at least one surface side of the base film 1. A printed circuit 300 is manufactured by forming a conductive pattern of a circuit at the conductor layer 2 of the printed circuit substrate 200. The printed circuit 300 is, for example, a flexible printed circuit (FPC).

[0043] [Base Film]

[0044] The base film 1 is a sheet-shaped member. The base film 1 supports a conductive pattern in the printed circuit 300 formed using the printed circuit substrate 200.

[0045] In the embodiment, the material of the base film 1 is polyimide. The base film 1 can contain other components as long as the main component is polyimide. The "main component" herein means a component having a content of 50% by weight or more. Alternatively, the "main component" means a component having the largest content among the components contained. Polyimide can be used because of its large binding force to the metal oxide or the like formed on the surface of the conductor layer 2.

[0046] The thickness of the base film 1 is not particularly limited according to the printed circuit 300 using the printed circuit substrate 200, and for example, as a lower limit of the average thickness of the base film 1, it can be 5 μm or 12 μm. On the other hand, as an upper limit of the average thickness of the base film 1, it can be 2 mm or 1.6 mm. In the case where the average thickness of the base film 1 is less than 5 μm, the strength of the base film 1 can be insufficient. In contrast, in the case where the average thickness of the base film 1 exceeds 2 mm, the thinning of the printed circuit 300 can become difficult.

[0047] On the base film 1 described above, the surface on the side on which the conductor layer 2 is laminated can be subjected to a hydrophilization treatment. The hydrophilization treatment described above can be, for example, a plasma treatment in which the surface is made hydrophilic by irradiation of plasma, or an alkali treatment in which the surface is made hydrophilic by an alkali solution. By subjecting the base film 1 to the hydrophilization treatment, the surface tension of the conductive ink with respect to the base film 1 becomes small, so the conductive ink is easily uniformly applied to the base film 1.

[0048] [Conductor layer]

[0049] The conductor layer 2 has at least a first conductor layer 4 and a second conductor layer 5. The conductor layer 2 can also have the first conductor layer 4, the second conductor layer 5, and a third conductor layer 6 formed on the second conductor layer 5. The first conductor layer 4 is a conductor fired layer formed by application and firing of a conductive ink containing conductor particles such as metal particles. The first conductor layer 4 is formed on the base film 1. The second conductor layer 5 is an electroless plating layer formed on one surface side (opposite to the base film 1) of the first conductor layer 4 by electroless plating. The third conductor layer 6 is, for example, an electroplating layer formed on one surface side (opposite to the base film 1) of the second conductor layer 5 by electroplating.

[0050] The thickness of the conductor layer 2 is determined depending on what kind of printed circuit 300 is made using the printed circuit substrate 200. There is no particular limitation on the lower limit of the average thickness of the conductor layer 2, and it can be 1 μm or 2 μm. On the other hand, there is no particular limitation on the upper limit of the average thickness of the conductor layer 2, and it can be 100 μm or 50 μm. In the case where the average thickness of the conductor layer 2 is less than 1 μm, the conductor layer 2 can become susceptible to damage. In contrast, in the case where the average thickness of the conductor layer 2 exceeds 100 μm, it can become difficult to thin the printed circuit 300.

[0051] [First conductor layer]

[0052] The first conductor layer 4 is a metal sintered layer. The metal sintered layer is, for example, a sintered layer of metal particles. The first conductor layer 4 is formed, for example, by coating of a conductive ink containing metal particles and sintering. The first conductor layer 4 is laminated on one face of the base film 1. In the printed circuit substrate 200, since the first conductor layer 4 is formed by coating of a conductive ink and sintering, it is possible to easily cover one face of the base film 1 with a conductive film. Note that, in order to reliably fix the metal particles on one face of the base film 1 by removing unnecessary organic matter or the like in the conductive ink, the first conductor layer 4 is formed by sintering after coating of the conductive ink.

[0053] The conductive ink in which the first conductor layer 4 is formed contains metal particles as a conductive substance that imparts conductivity. In the present embodiment, as the conductive ink, an ink containing metal particles, a dispersant that disperses the metal particles, and a dispersion medium is used. By coating using such a conductive ink, the first conductor layer 4 composed of fine metal particles is laminated on one face of the base film 1.

[0054] The metal that constitutes the metal particles contained in the conductive ink is not particularly limited, and from the viewpoint of improving the adhesion between the first conductor layer 4 and the base film 1, it can be a metal that forms a metal oxide based on the metal or a group derived from the metal oxide and a metal hydroxide based on the metal or a group derived from the metal hydroxide, and for example, copper, nickel, aluminum, gold, or silver can be used. Among these, since the conductivity is good and the adhesion to the base film 1 is excellent, copper can also be used.

[0055] As a lower limit of the average particle diameter of the metal particles contained in the conductive ink, it can be 1 nm, or it can be 30 nm. On the other hand, as an upper limit of the average particle diameter of the metal particles, it can be 500 nm, or it can be 100 nm. In a case where the average particle diameter of the metal particles is less than 1 nm, the dispersibility and stability of the metal particles in the conductive ink can possibly be reduced. In contrast, in a case where the average particle diameter of the metal particles exceeds 500 nm, the metal particles can possibly become easy to precipitate, or the density of the metal particles can possibly become difficult to be uniform when the conductive ink is applied.

[0056] As a lower limit of the average thickness of the first conductor layer 4, it can be 0.05 μm, or it can be 0.1 μm. On the other hand, as an upper limit of the average thickness of the first conductor layer 4, it can be 2 μm, or it can be 1.5 μm. In a case where the average thickness of the first conductor layer 4 is less than 0.05 μm, it can possibly cause a cutting line on the first conductor layer 4 to reduce the conductivity. In contrast, in a case where the average thickness of the first conductor layer 4 exceeds 2 μm, the thinning of the conductor layer 2 can possibly become difficult, or the metal can not be filled in the voids of the first conductor layer 4 at the time of formation of the second conductor layer 5 to be described later, and the conductivity and strength of the first conductor layer 4 and the conductor layer 2 can possibly become insufficient.

[0057] [Second Conductor Layer]

[0058] The second conductor layer 5 is laminated on the surface of the first conductor layer 4, that is, the surface opposite to the base film 1, by electroless plating. Thus, since the second conductor layer 5 is formed by electroless plating, the metal of the second conductor layer 5 is filled in the voids between the metal particles that form the first conductor layer 4. If the voids remain in the first conductor layer 4, the void portions become a starting point of damage, and the first conductor layer 4 is easily peeled from the base film 1, but by filling the metal that constitutes the second conductor layer 5 in the void portions, the peeling of the first conductor layer 4 can be suppressed.

[0059] As the metal used in the electroless plating, copper, nickel, silver, or the like having good conductivity can be used, but in a case where the metal particles that form the first conductor layer 4 use copper, in consideration of the adhesion to the first conductor layer 4, copper or nickel can be used. Note that in a case where a metal other than nickel is used in the electroless plating, the plating solution used in the electroless plating can also use a plating solution containing nickel or a nickel compound in addition to the plating metal.

[0060] As a lower limit of the average thickness of the second conductor layer 5 formed by the electroless plating, it can be 0.2 μm or 0.3 μm. On the other hand, as an upper limit of the average thickness of the second conductor layer 5 formed by the electroless plating, it can be 1 μm or 0.5 μm. In a case where the average thickness of the second conductor layer 5 formed by the electroless plating is less than 0.2 μm, the second conductor layer 5 cannot sufficiently fill the void portion of the first conductor layer 4, and the conductivity can be lowered. In contrast, in a case where the average thickness of the second conductor layer 5 formed by the electroless plating exceeds 1 μm, the time required for the electroless plating becomes long, and the productivity can be lowered.

[0061] [Third conductor layer]

[0062] The third conductor layer 6 is formed, for example, by plating lamination on the surface of the second conductor layer 5 formed by the electroless plating. The third conductor layer 6 at this time is a plating layer formed by plating. In addition, the third conductor layer 6 can also be a metal foil layer provided on the surface of the second conductor layer 5. The metal foil layer can also be an extremely thin metal foil layer, for example, an extremely thin copper foil layer. The thickness of the metal foil layer is, for example, 0.5 μm or more and 10 μm or less. In this way, by laminating the third conductor layer 6 on the surface of the second conductor layer 5, adjustment of the thickness of the conductor layer 2 can be easily and accurately performed, and in addition, the conductor layer having a thickness required for forming the printed circuit 300 can be formed in a relatively short time.

[0063] As a metal used in plating for forming the third conductor layer 6, copper, nickel, silver, or the like having good conductivity can be used. In a case where the third conductor layer 6 is an extremely thin copper foil layer, lamination can be performed by bonding through heat press bonding or the like.

[0064] The thickness of the third conductor layer 6 is determined in accordance with the thickness of the entire conductor layer 2 required.

[0065] [Method for manufacturing printed circuit substrate]

[0066] Figure 2 The steps of the method for manufacturing the printed circuit substrate are shown. Figure 1 The steps of the method for manufacturing the printed circuit substrate are shown.

[0067] In the embodiment, the method for manufacturing the printed circuit substrate includes a conductive ink preparation step (step S11), a conductive ink coating and baking step (step S12), an electroless plating step (step S14), a heat treatment step (step S15), and a plating step (step S16).

[0068] [Preparation step (step S11)]

[0069] In the preparation process of step Sll, a conductive ink containing metal particles is prepared. In the preparation process, a dispersing agent is dissolved in a dispersion medium, and the above-mentioned metal particles are dispersed in the dispersion medium. That is, the metal particles are inhibited from coagulating by being surrounded by the dispersing agent, and are dispersed well in the dispersion medium.

[0070] Note that the dispersing agent can also be added to the reaction system in the form of a solution dissolved in water or a water-soluble organic solvent.

[0071] As the dispersion medium of the conductive ink, water, a high-polarity solvent, or a dispersion medium obtained by mixing two or more of these can be used, and a dispersion medium obtained by mixing water as a main component and a high-polarity solvent that is soluble with water is preferably used.

[0072] As the dispersing agent contained in the conductive ink, a dispersing agent that does not contain sulfur, phosphorus, boron, halogen, and alkali is preferable from the viewpoint of preventing the deterioration of the printed circuit substrate. As such a dispersing agent, a polyethylene imine, a polyvinyl pyrrolidone, a high-molecular dispersing agent of an amine type such as these, a high-molecular dispersing agent of a hydrocarbon type having a carboxylic acid group in the molecule such as polyacrylic acid and carboxymethyl cellulose, a polyvinyl alcohol (POVAL), a styrene-maleic acid copolymer, an olefin-maleic acid copolymer, a copolymer having a polyethylene imine portion and a polyethylene oxide portion in one molecule, and a high-molecular dispersing agent having a polar group such as these can be listed.

[0073] [Coating and firing process (step S12)]

[0074] In the coating and firing process of step S12, a first conductor layer 4 is formed by coating the conductive ink on one surface side of the base film 1 having insulating properties and performing firing. In the coating and firing process, the conductive ink prepared in step Sll is coated on the surface of the base film 1, dried, and then heated and fired. Note that the surface of the base film 1 on which the conductive ink is coated is modified by previously performing a hydrophilization treatment such as the above-mentioned alkali treatment.

[0075] As the method of coating the conductive ink in which metal particles are dispersed on one surface of the base film 1, a conventionally known coating method such as a spin coating method, a spray coating method, a bar coating method, a die coating method, a slit coating method, a roll coating method, and a dip coating method can be used.

[0076] In addition, the conductive ink can also be coated on only a part of one surface of the base film 1 by screen printing, a dispenser, or the like.

[0077] Next, the dispersion medium in the conductive ink coated on the base film 1 is evaporated, and the conductive ink is dried.

[0078] As a drying method of the conductive ink, natural drying, drying using heating, drying using hot air, or the like can be applied. In addition, a method of not blowing a strong wind that roughens the surface of the conductive ink before drying is adopted.

[0079] Further, by heating the dried conductive ink, the dispersion medium in the conductive ink is thermally decomposed, and the metal particles are fired, thereby forming the first conductor layer 4. By this firing, the metal particles become in a state of being mutually adhered and solidly joined in a sintered state or a stage before reaching the sintered state.

[0080] Therefore, the first conductor layer 4 after the conductive ink coating and firing process can have pores corresponding to the gaps between the above-described metal particles.

[0081] The above-described firing is performed in an atmosphere containing a certain amount of oxygen. The lower limit of the oxygen concentration of the atmosphere at the time of firing is 1 volume ppm, and can also be 10 volume ppm. In addition, the upper limit of the above-described oxygen concentration is 10,000 volume ppm, and can also be 1,000 volume ppm. In the case where the above-described oxygen concentration is less than 1 volume ppm, the amount of generation of the metal oxide in the vicinity of the interface of the first conductor layer 4 decreases, and it can be impossible to sufficiently obtain the effect of improving the adhesion of the first conductor layer 4 to the base film 1 by the metal oxide. On the other hand, in the case where the above-described oxygen concentration exceeds 10,000 volume ppm, the metal particles are excessively oxidized, and the conductivity of the first conductor layer 4 can decrease.

[0082] The lower limit of the temperature of the above-described firing can be 150°C, and can also be 200°C. In addition, the upper limit of the temperature of the above-described firing can be 500°C, and can also be 400°C. If the temperature of the above-described firing is less than 150°C, the amount of generation of the metal oxide in the vicinity of the interface of the first conductor layer 4 decreases, and it can be impossible to sufficiently obtain the effect of improving the adhesion of the first conductor layer 4 to the base film 1 by the metal oxide. On the other hand, when the temperature of the above-described firing exceeds 500°C, the base film 1 can be deformed in the case where the base film 1 is an organic resin such as polyimide.

[0083] [Electroless Plating Process (Step S14)]

[0084] In the electroless plating process of step S14, electroless plating is performed by using an electroless plating solution to cause metal to be deposited to the surface of the first conductor layer 4 and the pores in the inside of the first conductor layer 4, thereby forming the second conductor layer 5. Note that the base film 1 on which the first conductor layer 4 is formed can be subjected to degreasing cleaning and pickling treatment before the electroless plating process of step S14.

[0085] The non-electrolytic plating solution causes metal to deposit. As the metal to be deposited, as described above, copper, nickel, silver, and the like can be listed. In the case of depositing copper, for example, a copper plating solution containing a trace amount of nickel is used as the non-electrolytic plating solution. By using a copper plating solution containing nickel or a nickel compound, a second conductor layer 5 having low stress can be formed. As the copper plating solution, for example, 0.1 moles or more and 60 moles or less of nickel can be contained with respect to 100 moles of copper. In addition, other components such as a complexing agent, a reducing agent, a pH adjuster, and the like can be appropriately incorporated in the copper plating solution.

[0086] The non-electrolytic plating process of step S14 has a process (step S14-1) of causing metal (a conductor) that becomes a catalyst to deposit from the non-electrolytic plating solution onto the first conductor layer 4 by electrolysis assistance. In the non-electrolytic plating process of step S14, the metal (a conductor) deposited by electrolysis assistance of step S14-1 is used as a catalyst to cause metal (a conductor) to deposit to the surface and inside of the first conductor layer 4 by non-electrolytic plating. In a general non-electrolytic plating process, a pretreatment of attaching a catalyst such as palladium is required, but in the non-electrolytic plating process of step S14, since the metal deposited from the non-electrolytic plating is used as a catalyst, the pretreatment of attaching a catalyst such as palladium is not required. As a catalyst that can be used in a general non-electrolytic plating process, in addition to palladium, there are platinum (Pt), nickel (Ni), cobalt (Co), iron (Fe), chromium (Cr), silver (Ag), gold (Au), for example. The printed circuit substrate 200 manufactured by the manufacturing method of a printed circuit substrate of the present disclosure does not contain or substantially does not contain at least one of palladium (Pd), platinum (Pt), nickel (Ni), cobalt (Co), iron (Fe), chromium (Cr), silver (Ag), and gold (Au) in the base film 1.

[0087] Electrolysis assistance is a method of applying an electric potential to a treated product (a plating target) using a non-electrolytic plating solution to perform plating at the initial stage of non-electrolytic plating. By performing electrolysis assistance, even if a non-electrolytic plating solution is used, metal is deposited from the non-electrolytic plating solution onto the first conductor layer 4 using electric energy as in electroplating (electrolytic plating). That is, in electrolysis assistance, a non-electrolytic plating solution is used, and plating is performed by electric current assistance. In the manufacturing method according to the embodiment, before the non-electrolytic plating process of step S14, the base film 110 as a treated product using a non-electrolytic plating solution has the first conductor layer 4 formed on the surface thereof, and has electrical conductivity.

[0088] In electrolysis assistance, the treated product using non-electrolytic plating can be electrified through the first conductor layer 4, and metal is deposited from the non-electrolytic plating solution onto the first conductor layer 4 by electric energy.

[0089] Figure 3An example of a non-electrolytic plating device 100 capable of performing a non-electrolytic plating process (step S14) including an electrolysis assisting process (step S14-1) is shown. The non-electrolytic plating device 100 is provided with a non-electrolytic plating treatment tank 101 into which a non-electrolytic plating solution is supplied. The non-electrolytic plating device 100 is provided with a roller 102 that feeds a base film 110 on which a first conductor layer 4 is formed to the non-electrolytic plating treatment tank 101. The base film 110 on which the first conductor layer 4 is formed is fed to the non-electrolytic plating treatment tank 101 by the roller 102 and is immersed in the non-electrolytic plating solution.

[0090] The roller 102 is made of a material having electrical conductivity, such as SUS. The roller 102 is connected to the negative electrode of a direct current power source 105 and applies a negative potential to the base film 110 on which the first conductor layer 4 is formed. In this way, the roller 102 functions as a first electrode that applies a negative potential to the first conductor layer 4 outside the non-electrolytic plating treatment tank 101. In addition, a Ti plate that becomes a counter electrode 103 (second electrode) is provided inside the non-electrolytic plating treatment tank 101. The counter electrode 103 is connected to the positive electrode of the direct current power source 105 and applies a positive potential to the non-electrolytic plating solution.

[0091] By applying a negative potential to the first conductor layer 4 from the roller 102 that is the first electrode, the potential of the first conductor layer 4 immersed in the non-electrolytic plating solution decreases. As a result, copper or the like metal is deposited from the non-electrolytic plating solution onto the first conductor layer 4 immersed in the non-electrolytic plating solution. The metal deposited by electrolysis assistance becomes a catalyst for non-electrolytic plating. In this way, the electrolysis assisting process is also a process in which the catalyst for non-electrolytic plating is attached to the first conductor layer 4.

[0092] In the non-electrolytic plating treatment tank 101, non-electrolytic plating is performed using the metal deposited by electrolysis assistance as a catalyst. By this non-electrolytic plating, metal is deposited to the surface of the first conductor layer 4, thereby forming a second conductor layer 5, and metal is also deposited into the voids inside the first conductor layer 4, thereby densifying the first conductor layer 4. By this densification of the first conductor layer 4, not only the electrical conductivity of the first conductor layer 4 is improved, but also the adhesion area of the first conductor layer 4 to the base film 1 increases, thereby increasing the peeling strength of the first conductor layer 4 and the conductor layer 2 from the base film 1.

[0093] In the electroless plating process of step S14, if the base film 110 on which the first conductor layer 4 is formed is dipped in the electroless plating solution, an electrolysis-assisted plating is formed on the surface of the first conductor layer 4 instantaneously, and then an electroless plating based on the electroless plating solution is formed. Therefore, the electroless plating solution can be inhibited from intruding into the base film 1. As a result, the damage to the base film 1 by the electroless plating solution can be inhibited. By inhibiting the damage to the base film 1, the thermal decomposition of the base film 1 can be inhibited. In this way, by forming the electrolysis-assisted plating on the base film 1, even if the electroless plating is performed on the base film 1, the damage caused by the electroless plating can be inhibited, and the base film 1 in which the thermal decomposition is inhibited can be obtained.

[0094] Note that, after the electroless plating process of step S14, a post pickling treatment can be performed.

[0095] [Thermal treatment process (step S15)]

[0096] Returning to Figure 2 After the electroless plating process, the thermal treatment process of step S15 is performed. As a lower limit of the treatment temperature in the thermal treatment process, 150°C can be used, or 200°C can be used. On the other hand, as an upper limit of the treatment temperature in the thermal treatment process, 500°C can be used, or 400°C can be used. As a lower limit of the heat treatment time in the thermal treatment process, 15 minutes can be used, or 30 minutes can be used. On the other hand, as an upper limit of the heat treatment time in the thermal treatment process, 720 minutes can be used, or 360 minutes can be used.

[0097] [Electroplating process (step S16)]

[0098] In the electroplating process of step S16, a third conductor layer 6 is formed by further laminating metal on the surface of the second conductor layer 5 formed in the electroless plating process of step S14 through electroplating. At this time, the metal is filled in the voids remaining in the inside of the first conductor layer 4 through the electroplating, so that the first conductor layer 4 is further densified, and the peeling strength of the first conductor layer 4 from the base film 1 is further increased. Through the electroplating process, the thickness of the conductor layer 2 can be easily and reliably grown to a desired thickness.

[0099] As a specific method of the electroplating in the electroplating process, a publicly known electroplating method can be applied. Note that, instead of the electroplating process (step S16), a hot press bonding of an extremely thin copper foil can be performed. In this case, an extremely thin copper foil layer is formed as the third conductor layer 6.

[0100] [Printed circuit]

[0101] The printed circuit 300 is formed by Figure 1The above-described printed circuit substrate 200 is manufactured by performing circuit pattern formation processing for forming a conductive pattern.

[0102] Figure 4 A printed circuit 300 is shown. A conductive pattern 2A, 2B, 2C is formed on a base film 1. The conductive pattern 2A, 2B, 2C in the printed circuit 300 according to the embodiment is a fine pattern, and has a very small minimum conductor width W and also a very small minimum conductor interval S. Here, the minimum conductor width W is the smallest width among the widths of the conductors included in the conductive pattern 2A, 2B, 2C. In addition, the minimum conductor interval refers to the smallest interval among the intervals between the conductors formed by the conductive pattern 2A, 2B, 2C.

[0103] The minimum conductor width W can be 20 μm or less, 15 μm or less, or 10 μm or less. In addition, the minimum conductor interval S can be 20 μm or less, 15 μm or less, or 10 μm or less. Either one of the minimum conductor width and the minimum conductor interval can be the above-described values, but both the minimum conductor width and the minimum conductor interval can be the above-described values.

[0104] The conductive patterns 2A, 2B, 2C each have a conductor layer 2 on the base film 1. The conductor layer 2 has a first conductor layer 4, and a second conductor layer 5 is provided on the first conductor layer. A third conductor layer 6 can be further provided on the second conductor layer 5. The conductive patterns 2A, 2B, 2C each can further have one or more fourth conductor layers 7 on the conductor layer 2. The base film 1 can have a through hole that penetrates in the thickness direction. Figure 5 is a schematic cross-sectional view showing the inner wall of the through hole and the surroundings when the through hole is provided.

[0105] [Method for manufacturing printed circuit]

[0106] The circuit pattern formation processing is, for example, a subtractive method or a semi-additive method.

[0107] In the subtractive method, a photosensitive resist is coated on one face of the printed circuit substrate 200, and the resist is patterned corresponding to the conductive pattern by exposure, development, and the like. Next, the patterned resist is used as a mask, and the conductor layer 2 except for the conductive pattern is removed by etching. Then, finally, the remaining resist is removed, and the printed circuit 300 having a conductive pattern formed of the remaining portion of the conductor layer 2 of the printed circuit substrate 200 of Figure 1 the printed circuit 300.

[0108] In the semi-additive method, a photosensitive resist is coated onto one side of a printed circuit substrate 200. Through exposure and development, openings corresponding to the conductive pattern are patterned on the resist. Next, by using the patterned resist as a mask for plating, a conductor layer is selectively laminated onto the conductor layer 2 exposed at the openings of the mask. Then, after stripping the resist, the surface of the conductor layer and the conductor layer 2 without conductor layers are removed by etching, thereby obtaining a conductive pattern. Figure 1 The printed circuit is a conductive pattern formed by further laminating conductor layers on the remaining portion of the conductor layer 2 of the substrate 200.

[0109] pass Figure 2 The base film 1 in the printed circuit board substrate 200 manufactured by the method does not contain palladium. This is because, in Figure 2 The manufacturing method does not include a step of attaching palladium, which serves as a catalyst for electroless plating in step S14. "The base film does not contain palladium" means that the base film contains no palladium at all, or that the base film substantially does not contain palladium. "The base film substantially does not contain palladium" means that the base film contains no palladium except for an unavoidable amount. An unavoidable amount is, for example, a content of 0.05 ppm or more and 10 ppm or less in ICP analysis of the polyimide on the surface of the base film cut from the conductor layer side.

[0110] By eliminating palladium from base film 1, porosity in base film 1 can be suppressed (see reference). Figures 8 to 10 The generation of voids is explained in detail in the description of the manufacturing method of the printed circuit substrate involved in the reference examples described later.

[0111] pass Figure 2 The base film 1 in the printed circuit substrate 200 manufactured by the manufacturing method has a number of voids generated in the base film 1 per 0.25 mm on the surface of the base film. 2 The number of voids in each reference unit area D is 10 or less. The number of voids in each reference unit area D can be 5 or less, or 1 or less. The number of voids is preferably zero.

[0112] Regarding the porosity, the maximum porosity L of the base film when viewed from above (refer to...). Figure 8 as well as Figure 9 The gaps can be 5μm or more and 10μm or less. Gaps with a maximum width L of 5μm or more and 10μm or less are prone to causing circuit defects in fine patterns like those described above. However, by keeping the number of such gaps to 10 or less per reference unit area D, the probability of circuit defects can be sufficiently suppressed.

[0113] It should be noted that the maximum width L of the gap can be more than 1 / 4 of the minimum conductor width W, or more than 1 / 4 of the minimum conductor spacing S. Alternatively, the maximum width L of the gap can be less than 1 / 2 of the minimum conductor width W, or less than 1 / 2 of the minimum conductor spacing S. If the maximum width L of the gap is too large, circuit defects are easily generated in fine patterns. However, by keeping the number of such gaps to 10 or less per reference unit area D, the probability of circuit defects can be sufficiently suppressed.

[0114] The area of ​​the pores can be 20 μm. 2 Above and 100μm 2 The following applies. If the gaps are large enough, circuit defects are likely to occur in fine patterns. However, by keeping the number of such gaps below 10 per reference unit area D, the probability of circuit defects can be sufficiently suppressed.

[0115] Additionally, the height H of the gap (refer to...) Figure 8 as well as Figure 9 The gap can be between 1.5μm and 5μm. Large gaps (H in diameter) can easily lead to circuit malfunctions. For example... Figure 9 As shown, height H is defined as the height of the base film surface at the location 1B where voids exist, relative to the base film surface at the location 1A where voids do not exist. It should be noted that... Figure 9 It shows from Figure 8 The printed circuit board substrate 200 is a cross-section of the base film after the conductor layer 2 has been removed by etching. The region 1A without voids in the base film can be selected as the region with the lowest height on the base film surface. The height H can be determined by scanning the base film surface using a laser microscope.

[0116] [Refer to the manufacturing method of the printed circuit board substrate mentioned in the example]

[0117] Figure 6 The steps of a method for manufacturing a printed circuit substrate as described in the reference example are shown. Figure 6 The manufacturing method shown is the same as Figure 2 The difference in the manufacturing method shown is that a pretreatment step (step S13) is performed before the electroless plating step, and no electrolytic assistance is performed in the electroless plating step. It should be noted that in... Figure 6 In the manufacturing method shown, the conductive ink preparation step (step S11), the conductive ink coating and firing step (step S12), and the electroplating step (step S16) are... Figure 2 The manufacturing method shown is the same. The following is about... Figure 6 The pretreatment process (step S13), electroless plating process (step S14A), and heat treatment process (step S15) shown will be explained.

[0118] [Pre-treatment step (step S13)]

[0119] In the pre-treatment step of step S13, for example, palladium which becomes a catalyst in the electroless plating is adsorbed on the first conductor layer 4. In the pre-treatment step, palladium ions are adsorbed by bringing the first conductor layer 4 into contact with a catalyst solution containing palladium, and the palladium ions are reduced to metallic palladium. As the palladium concentration of the catalyst solution, for example, it can be 20 mass ppm or more and 1000 mass ppm or less.

[0120] As the lower limit of the temperature of the catalyst solution at the time of the immersion, depending on the immersion time, it can be 30°C, or it can be 40°C. On the other hand, as the upper limit of the temperature of the catalyst solution at the time of the immersion, it can be 70°C, or it can be 60°C.

[0121] As the lower limit of the immersion time in the catalyst solution, depending on the temperature of the catalyst solution, it can be 1 minute, or it can be 2 minutes, or it can be 3 minutes. On the other hand, as the upper limit of the immersion time in the catalyst solution, it can be 10 minutes, or it can be 7 minutes, or it can be 5 minutes.

[0122] [Electroless plating step (step S14A: electroless assisted)]

[0123] In the electroless plating step of step S14A, the palladium adsorbed on the first conductor layer 4 in the pre-treatment step of step S13 is used as a catalyst, and metal is deposited to the surface and the inside of the first conductor layer 4. In the manufacturing method related to the reference example, since palladium is used as a catalyst, electro-assisted plating is not performed.

[0124] In the electroless plating step of step S14A, by performing electroless plating using an electroless plating solution, metal is deposited to the surface of the first conductor layer 4 and to the pores in the inside of the first conductor layer 4, thereby forming the second conductor layer 5. Note that, before the electroless plating step of step S14A, the base film 1 on which the first conductor layer 4 is formed on the surface can be subjected to a degreasing cleaning and an acid pickling treatment.

[0125] The palladium intrudes into the base film 1 at the time of the electroless plating. In addition, the electroless plating solution intrudes into the base film 1 through the first conductor layer 4.

[0126] [Heat treatment step (step S15)]

[0127] Figure 6 The heat treatment step of step S15 shown in the above is performed in the same manner as the heat treatment step shown in the above. Figure 2

[0128] However, by the heat treatment, the palladium present in the vicinity of the interface of the conductor layer 2 and the base film 1 is promoted to intrude into the base film 1.​

[0129] Figure 7 A printed circuit substrate is shown in which palladium is dispersed in the interior of a base film 1. Figure 7 The base film 1 shown has a dispersed portion 3 in which palladium is dispersed. In the dispersed portion 3, the palladium content in the base film 1 is 290 ppm or more by ICP mass analysis. Figure 6 In the case of the manufacturing method of the reference example, in the dispersed portion 3, the palladium content in the base film 1 is 290 ppm or more by ICP mass analysis.

[0130] The dispersed portion 3 is formed by introducing and dispersing palladium from the surface of the base film 1 into the interior of the base film 1. The dispersed portion 3 is formed so as to introduce and disperse palladium substantially uniformly from the interface with the conductor layer 2 of the base film 1, take a portion or the whole of the base film 1 in the thickness direction with the interface with the conductor layer 2 as the base end, and have a substantially constant thickness as a layer. That is, the dispersed portion 3 can include a region to a certain depth from the interface with the conductor layer 2 of the base film 1.

[0131] When a printed circuit substrate is manufactured by the manufacturing method related to the reference example, as shown in Figures 8 to 10 A void 10 is generated in the base film 1. The void 10 is a cavity generated in the interior of the base film 1. The void 10 is formed near the interface 11 of the base film 1 and the conductor layer 2, and causes the surface of the base film 1 to locally expand toward the conductor layer 2 side. The void 10 is generated dispersedly on the surface of the base film 1. The void 10 is amorphous, but is formed substantially as a dot.

[0132] The inventors have found that the cause of the generation of the void 10 is palladium that has intruded into the base film 1 that has polyimide as the main component. The palladium catalyst intrudes into the base film 1 at the time of electroless plating. When the palladium that has intruded into the base film 1 undergoes a reduction reaction under the catalytic action of the palladium, a gas is generated in the base film 1. Due to the generation of the gas, the void 10 is generated in the base film 1.

[0133] Figure 8 is an enlarged sectional view of a void generation site in the printed circuit substrate related to the reference example. In the reference example, the maximum width L of the void 10 in a plan view of the base film is substantially 1 to 10 μm or so. In addition, the height H of the void 10 is substantially 0.1 to 5 μm. A plurality of voids 10 are confirmed in the base film of the printed circuit substrate related to the reference example. On the other hand, in the base film 1 of the printed circuit substrate of the present disclosure, the void 10 having a maximum width L of 5 μm or more in a plan view is suppressed. Here, the maximum width L of the void 10 related to the reference example and the void that is suppressed in the printed circuit substrate of the present disclosure is measured, for example, by removing the conductor layer 2 of the manufactured printed circuit substrate by etching, and performing fluorescence microscope observation of the surface of the base film 1. In addition, the height H of the void 10 is measured, for example, by performing laser microscope observation of the surface of the base film 1 from which the conductor layer 2 has been removed.

[0134] The void 10 is relatively small. Therefore, if it is a general printed circuit in which the conductor width or the conductor interval is sufficiently large compared with the void, the presence of the void 10 hardly becomes a problem. However, in the case of a printed circuit having a fine pattern, since the conductor width or the conductor interval is fine, it is possible that a circuit failure occurs due to the presence of the void 10. For example, if a conductive pattern having a conductor width of the same order as or below the size of the void 10 exists directly above the void 10, it is possible that a conduction failure of the conductive pattern occurs. The greater the maximum width L of the void 10, the more likely the circuit failure occurs, and the greater the height H of the void 10, the more likely the circuit failure occurs. Figures 8 to 10 The void 10 is relatively small. Therefore, if it is a general printed circuit in which the conductor width or the conductor interval is sufficiently large compared with the void, the presence of the void 10 hardly becomes a problem. However, in the case of a printed circuit having a fine pattern, since the conductor width or the conductor interval is fine, it is possible that a circuit failure occurs due to the presence of the void 10. For example, if a conductive pattern having a conductor width of the same order as or below the size of the void 10 exists directly above the void 10, it is possible that a conduction failure of the conductive pattern occurs. The greater the maximum width L of the void 10, the more likely the circuit failure occurs, and the greater the height H of the void 10, the more likely the circuit failure occurs.

[0135] Thus, if a fine pattern printed circuit substrate is manufactured by the manufacturing method according to the Reference Example shown in Figure 6 the void 10 is generated on the base film 1, and it is possible that a circuit failure occurs in the fine pattern printed circuit. In contrast, if a fine pattern printed circuit substrate is manufactured by the manufacturing method according to the Reference Example shown in Figure 2 the generation of the void 10 can be suppressed.

[0136] In the manufacturing method according to the Reference Example shown in Figure 2 In the electroless plating step, a metal catalyst such as palladium is not used, but a catalyst generated by electrolysis assistance is used. Since palladium, which is a cause of generation of the void 10, is not present, the generation of the void 10 in the base film 1 can be suppressed. If a fine pattern printed circuit is manufactured from a printed circuit substrate in which the void 10 hardly exists, the occurrence of a circuit failure can be suppressed.

[0137] Example

[0138] Hereinafter, the results of trial-manufacture of the printed circuit substrates are described.

[0139] [First, second, and third trial products (with electrolysis assistance: copper catalyst)]

[0140] The first, second, and third trial products of the printed circuit substrates were manufactured in accordance with the manufacturing method according to the Reference Example shown in Figure 2The manufacturing process is carried out according to steps S11, S12, and S14. Specifically, it is manufactured according to the following procedure. First, copper particles with an average particle size of 60 nm are dispersed in water as a solvent to prepare a conductive ink with a copper concentration of 26% by mass. In addition, as an insulating base film, both sides of a polyimide film (KAPTON "EN-S" from Toray DuPont Co., Ltd.) with an average thickness of 25 μm are modified by alkali treatment. The above-mentioned conductive ink is coated on both sides of the modified polyimide film, dried in the atmosphere, and then heated at 350°C for 2 hours in a nitrogen atmosphere with an oxygen concentration of 100 ppm by volume, thereby sintering the copper particles in the above-mentioned conductive ink to form a sintered layer, i.e., the first conductor layer, with an average thickness of 0.15 μm.

[0141] Next, use Figure 3 The electroless plating apparatus 100 shown performed electroless plating (step S14) including electrolysis assistance (step S14-1). In the manufacture of the first, second, and third prototypes, palladium was not used as the catalyst for electroless plating; instead, copper deposited from an electroless copper plating solution with electrolysis assistance was used. An electroless copper plating solution containing 0.1 moles of nickel per 100 moles of copper was used. Through electroless plating, a second conductor layer with an average thickness of 0.4 μm was formed on the first conductor layer on both sides of the base film. The formation of the third conductor layer was omitted, resulting in a printed circuit substrate with the first and second conductor layers formed on the base film. The first, second, and third prototypes were all manufactured using the above-described manufacturing method, but on different production lines (plating baths).

[0142] [Fourth prototype (without electrolysis aid: palladium catalyst)]

[0143] The fourth prototype of the substrate for printed circuit boards is prepared in accordance with Figure 6 The steps S11, S12, S13, and S14A shown are used for manufacturing. In the manufacturing of the fourth prototype, the process is carried out in the same manner as for the first, second, and third prototypes until the first conductor layer, which is the sintered layer of metal particles, is manufactured.

[0144] In the manufacture of the fourth prototype, after the formation of the first conductor layer, palladium is adsorbed onto the first conductor layer as a pretreatment (step S13). As a catalyst solution, a solution containing 50 ppm of palladium by mass is used, and palladium is adsorbed onto the first conductor layer by immersion at a liquid temperature of 40°C for 120 seconds.

[0145] In the manufacture of the fourth prototype, the following was used: Figure 3The electrolytic plating device 100 shown did not perform electrolytic assistance (step S14-1), but performed electrolytic plating using palladium as a catalyst (step S14A). As the electrolytic copper plating solution, the same electrolytic copper plating solution as that used in the manufacture of the first, second, and third trial products was used. By electrolytic plating, a second conductor layer having an average thickness of 0.4 μm was formed on the first conductor layer on both sides of the base film. The formation of the third conductor layer was omitted, and a fourth trial product of a base material for printed circuits having the first conductor layer and the second conductor layer formed on the base film was obtained.

[0146] [Fourth trial product]

[0147] The fourth trial product is a trial product in which the first conductor layer is omitted from the fourth trial product. In other respects, the fourth trial product is the same as the third trial product. That is, the fourth trial product has a base film and a second conductor layer formed directly on the base film. The manufacture of the fourth trial product is performed by omitting the conductive ink preparation process (step Sll) and the conductive ink coating and baking process (step S12) in the manufacturing process of the fourth trial product from the manufacturing process of the third trial product. Note that, in the formation of the second conductor layer, the same electrolytic copper plating solution as that used in the manufacture of the first, second, and third trial products was used. Figure 3 The electrolytic plating device 100 shown performed electrolytic plating using palladium as a catalyst (step S14A). In addition, in the manufacture of the fourth trial product, electrolytic assistance was not performed (step S14-1).

[0148] [Fourth trial product]

[0149] The fourth trial product is a trial product in which the first conductor layer is omitted from the fourth trial product. In other respects, the fourth trial product is the same as the third trial product. That is, the fourth trial product has a base film and a second conductor layer formed directly on the base film. The manufacture of the fourth trial product is performed by omitting the conductive ink preparation process (step Sll) and the conductive ink coating and baking process (step S12) in the manufacturing process of the fourth trial product from the manufacturing process of the third trial product. Note that, in the formation of the second conductor layer, the same electrolytic copper plating solution as that used in the manufacture of the first, second, and third trial products was used. -4 The fourth trial product is a trial product in which the first conductor layer is omitted from the fourth trial product. In other respects, the fourth trial product is the same as the third trial product. That is, the fourth trial product has a base film and a second conductor layer formed directly on the base film. The manufacture of the fourth trial product is performed by omitting the conductive ink preparation process (step Sll) and the conductive ink coating and baking process (step S12) in the manufacturing process of the fourth trial product from the manufacturing process of the third trial product. Note that, in the formation of the second conductor layer, the same electrolytic copper plating solution as that used in the manufacture of the first, second, and third trial products was used.

[0150] [Measurement of palladium content]

[0151] The palladium content was measured by ICP mass analysis for each of the test products. As the ICPMS analysis device, an ICPMS 7700X manufactured by Agilent Technologies was used. As the pretreatment, the polyimide exposed portion (interface with the conductor layer 2) of the base film was cut out, and the cut-out polyimide was subjected to complete decomposition in 8 mL of concentrated sulfuric acid using a microwave. To the liquid after the complete decomposition, ultrapure water was added, and the volume was made 50 mL.

[0152] [Measurement of carbon dioxide generation amount]

[0153] To evaluate the case where the thermal decomposition was suppressed in the first test product using electrolysis assistance, the amount of carbon dioxide emitted from the first test product and the fourth test product in a high-temperature state was measured. The size of the first test product used in the measurement was 20 x 20 mm (8 cm 2 ) on both sides.

[0154] A thermobalance-mass spectrometer (TG-MS) was used in the measurement. As the thermobalance-mass spectrometer, an STA449 F5 Jupiter manufactured by NETZSCH and a JMS-Q1500GC manufactured by JEOL were used. As the measurement atmosphere gas, helium was used. As the ionization method of the generated gas component, an electron ionization method was used. As the temperature condition, the temperature was increased at a rate of 10°C / min from room temperature (R.T.) to 100°C, and then, the temperature was increased at a rate of 5°C / min to 350°C, and the temperature was maintained at 350°C for 90 minutes. When the temperature was maintained at 350°C for 90 minutes, the amount of carbon dioxide generated from each of the first test product and the fourth test product was measured. Note that the calculation of the carbon dioxide generation amount was performed by introducing a known amount of carbon dioxide into the thermobalance-mass spectrometer, and a standard curve was prepared from the detection intensity thereof. Then, the carbon dioxide generation amount was converted using the standard curve from the detection intensity at the time of measurement of each of the first test product and the fourth test product.

[0155] The carbon dioxide generation amount of the first test product when left at 350°C for 90 minutes was 0.5 μg / cm 2 . In addition, the carbon dioxide generation amount of the fourth test product when left at 350°C for 90 minutes was 8.3 μg / cm 2 . Thus, the carbon dioxide generation amount of the first test product when left at 350°C for 90 minutes can be 1 μg / cm 2 Hereinafter, the damage caused by electroless plating is suppressed, and the thermal decomposition is suppressed.

[0156] [Observation results of test products]

[0157] Etching was performed on the conductor layer of each of the first to sixth test products to expose the base film surface. The etching was performed by immersing the test product in an etching solution containing ferric chloride (specific gravity 1.33 g / cm 3, and the temperature was 45°C) for 2 minutes. After the immersion, water washing and drying were performed. The surface of the base film that appeared by the removal by etching was observed. In the observation of the surface of the base film, a metal microscope BX51 manufactured by OLYMPUS Corporation was used, and the photographing was performed under a bright field.

[0158] In the metal microscope image, the number N of voids in each 0.25 mm 2 square unit area D was measured by visual observation. Here, voids having a maximum width of less than 5 μm were not measured. That is, the measured voids had a maximum width L of 5 μm or more and a height H of 1.5 μm or more in the metal microscope image in which the surface of the base film was observed in plan view.

[0159] The maximum width L of the voids was measured by performing image processing for extracting the void region from the metal microscope image, and measuring the maximum width of the extracted void region. In addition, the area of the voids was measured by counting the number of pixels of the extracted void region. The height H was measured by scanning the surface of the base film using a laser microscope.

[0160] The number of voids per square unit area D was measured by converting the total number T of voids present in the metal microscope image into the number N of voids per square unit area D. Specifically, since a region of 0.02 mm 2 X in width X of the surface of the base film appeared in the metal microscope image, the number N of voids per square unit area D was measured by the operation of T / (X / D).

[0161] No void having a maximum width of 5 μm or more was observed on the surface of the base film of the first trial product. That is, the number N of voids per square unit area D was 0 in the first trial product.

[0162] The number N of voids per square unit area D was 3 in the second trial product. The maximum width L of the largest void among the voids confirmed in the second trial product was 6 μm, and the height H was 3 μm.

[0163] The number N of voids per square unit area D was 9 in the third trial product. The maximum width L of the largest void among the voids confirmed in the third trial product was 8 μm, and the height H was 4 μm.

[0164] In the surface of the base film of the fourth trial product, voids were present dispersedly. The number N of voids per square unit area D was 76 in the fourth trial product. The maximum width L of the largest void among the voids confirmed in the fourth trial product was 8 μm, and the height H was 2 μm.

[0165] The number N of voids per square unit area D was 135 in the fifth trial product.

[0166] The maximum width L of the largest void in the voids confirmed in the fifth trial product was 25 μm, and the height H was 2.5 μm.

[0167] In the sixth trial product, the number N of voids per reference unit area D was zero.

[0168] The number N of voids per reference unit area D was evaluated in four levels of A to D. Among the four levels, A or B was good as the evaluation result. The evaluation results are shown below.

[0169] [Table 1]

[0170]

[0171] A: The number N of voids was 5 or less

[0172] B: The number N of voids was more than 6 and 10 or less

[0173] C: The number N of voids was more than 11 and 100 or less

[0174] D: The number N of voids was more than 101

[0175] The first, second, and third trial products were less in the number of voids than the fourth and fifth trial products, and thus were preferable in that they could suppress circuit failure in a printed circuit having a fine pattern. In particular, the fifth trial product was disadvantageous in that the number of voids was very large and the size of the voids was also large, so that circuit failure was likely to occur.

[0176] [Evaluation of the amount of Pd]

[0177] In the first, second, third, and sixth trial products in which electrolysis-assisted electroless plating was performed, the amount of Pd was 7 ppm or less. These were Pd that was unintentionally contained in each production line (plating bath), and were unavoidably introduced. On the other hand, the fourth trial product and the fifth trial product in which electroless plating was performed using a Pd catalyst had 291 ppm and 1485 ppm of Pd, respectively.

[0178] [Evaluation of the adhesion of the trial products]

[0179] A sample obtained by forming a copper plating layer having an average thickness of 20 μm on the second conductor layer of each of the first to sixth trial products by copper plating was used as a sample for evaluation of adhesion. The adhesion was evaluated by measuring the peel strength between the base film composed of polyimide and the conductor layer in accordance with JIS-K-6854-2 (1999) "Adhesives - Peel adhesion strength test method - Part 2: 180 degree peel". Specifically, the evaluation was performed using a force sensor of 50 N in a table precision tester AGS-X series manufactured by Shimadzu Corporation. The measurement conditions were that the copper foil side drawn out was gripped at a stroke length of 50 mm and a speed of 50 mm / min, and 180 degree peeling was performed. The average value in the range of a stroke length of 10 to 50 mm was used as the peel strength, and the measurement result was calculated. Based on the obtained measurement result, the adhesion between the base film and the conductor layer was evaluated in five levels of A to E as follows. Among the five levels, A or B was good as the evaluation result. The evaluation results are shown in Table 1.

[0180] A: peel strength of 9 N / cm or more

[0181] B: peel strength of 7 N / cm or more and less than 9 N / cm

[0182] C: peel strength of 5 N / cm or more and less than 7 N / cm

[0183] D: peel strength of 3 N / cm or more and less than 5 N / cm

[0184] E: peel strength of less than 3 N / cm

[0185] [Overall evaluation of void number and adhesion]

[0186] An overall evaluation of the void number and the adhesion was performed in four levels of A to D. A was the best, and the evaluation became lower in the order of B, C, and D.

[0187] The void number N per reference unit area D of the first and second trial products was small, which was good (evaluation: A), and the adhesion was also very good (evaluation: A), and as an overall evaluation of the void number and the adhesion, it was determined that the evaluation was A (see Table 1).

[0188] The void number N per reference unit area D of the third trial product was small, which was good (evaluation: B), and the adhesion was also good (evaluation: A), and as an overall evaluation of the void number and the adhesion, it was determined that the evaluation was B (see Table 1).

[0189] The fourth trial product had low adhesion (evaluation: C) and a large void number (evaluation: C), and thus as an overall evaluation, it was determined that the evaluation was C (see Table 1).

[0190] The fifth trial product had low adhesion (evaluation: D) and a very large number of voids (evaluation: D), and thus was evaluated as D (see Table 1) as a comprehensive evaluation.

[0191] The sixth trial product had a small number of voids N in each unit area D, which was very good (evaluation: A), but had very low adhesion (evaluation: E), and thus was evaluated as D (see Table 1) as a comprehensive evaluation.

[0192] Note that the embodiments and examples disclosed herein should be considered illustrative in all respects, and are not limited thereto. The scope of the present application is not the above-described meaning, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0193] Explanation of Reference Signs

[0194] 1: base film; 1A: portion in which voids are not present; 1B: portion in which voids are present; 2: conductor layer; 3: dispersed portion; 4: first conductor layer (sintered layer of metal particles, metal sintered layer); 5: second conductor layer (electroless plating layer); 6: third conductor layer; 7: fourth conductor layer; 8: via hole; 10: void; 11: interface; 100: electroless plating device; 101: electroless plating treatment tank; 102: roller (first electrode); 103: counter electrode (second electrode); 105: power supply; 200: base material for printed circuit; 300: printed circuit; 110: base film on which first conductor layer is formed; S11: preparation of conductive ink; S12: conductive ink application and baking; S13: pretreatment; S14: electroless plating; S14-1: electrolytic assistance; S14A: electroless plating (without electrolytic assistance); S15: heat treatment; S16: plating; 2A, 2B, 2C: conductive pattern.

Claims

1. A base material for a printed circuit, The base material for a printed circuit is provided with a base film having polyimide as a main component and a conductor layer formed on at least one side of the base film, The conductor layer has a metal sintered layer formed on the base film and an electrolysis-free plating layer formed on the metal sintered layer, In the base film, the number of voids having a maximum width of 5 μm or more in plan view is 10 or less per 0.25 mm 2 of reference unit area on the surface of the base film, The voids are formed at the interface of the base film and the conductor layer, The base film does not contain palladium, The electrolysis-free plating layer is formed by an electrolysis-free plating process in which a catalyst generated by electrolysis assistance is used instead of a palladium metal catalyst.

2. The base material for a printed circuit according to claim 1, wherein The conductor layer further has a plating layer or a metal foil layer on the electrolysis-free plating layer.

3. The base material for a printed circuit according to claim 1 or 2, wherein The number of the voids is 5 or less per the reference unit area.

4. The base material for a printed circuit according to claim 1 or 2, wherein The height of the base film surface at the site where the voids exist with respect to the base film surface at the site where the voids do not exist is 1.5 μm or more in the base film.

5. A printed circuit, The printed circuit is provided with a base film having polyimide as a main component and a conductive pattern formed on at least one side of the base film, The conductive pattern has a minimum conductor width and a minimum conductor interval, Either or both of the minimum conductor width and the minimum conductor interval is 20 μm or less, The conductive pattern includes a metal sintered layer formed on the base film and an electrolysis-free plating layer formed on the metal sintered layer, In the base film, the number of voids having a maximum width of 5 μm or more in plan view is 10 or less per 0.25 mm 2 of the reference unit area on the surface of the base film, The voids are formed at the interface of the base film and the conductive pattern, The base film does not contain palladium, The electrolysis-free plating layer is formed by an electrolysis-free plating process in which a catalyst generated by electrolysis assistance is used instead of a palladium metal catalyst.

6. The printed circuit according to claim 5, wherein Either or both of the minimum conductor width and the minimum conductor interval is 15 μm or less.

7. The printed circuit according to claim 5 or 6, wherein The base film is provided with a through-hole that penetrates in the thickness direction.

8. A method for manufacturing a base material for a printed circuit, The method for manufacturing a base material for a printed circuit includes a process of forming a first conductor layer as a metal sintered layer on one side of a base film having polyimide as a main component and a process of forming a second conductor layer on the first conductor layer by electrolysis-free plating using a catalyst that does not contain palladium, The process of forming the second conductor layer includes: The conductor that becomes the catalyst is precipitated from an electrolysis-free plating solution onto the first conductor layer by electrolysis assistance in which an electric potential is applied to the first conductor layer.

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