Display panel and display device

Abstract

A display panel and a display device provided by the embodiments of the present disclosure include: a base substrate having multiple rows and columns of sub-pixels; a pixel electrode layer located on the base substrate, the pixel electrode layer including multiple pixel electrodes spaced apart from each other, and one sub-pixel including one pixel electrode; wherein the pixel electrode includes: a first electrode strip, and a comb-like structure respectively connected to both sides of the first electrode strip; the comb-like structure is composed of a plurality of second electrode strips and a plurality of slits arranged alternately.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In recent years, the field of 3D display has developed rapidly. Among them, grating type 3D display devices have attracted much attention due to their advantages such as simple process and low crosstalk. Generally, grating type 3D display devices include a display panel and a grating. The left eye and right eye of the viewer obtain the left eye view and right eye view displayed by the display panel through the grating respectively to form a 3D display image. Summary of the invention

[0003] Embodiments of the present disclosure provide a display panel and a display device to improve display effects.

[0004] A display panel provided by an embodiment of the present disclosure includes:

[0005] A substrate having a plurality of rows and columns of sub-pixels;

[0006] A pixel electrode layer is located on the base substrate, the pixel electrode layer includes a plurality of pixel electrodes arranged at intervals from each other, and one sub-pixel includes one pixel electrode; wherein,

[0007] The pixel electrode comprises: a first electrode strip, and a comb-shaped structure respectively connected to two sides of the first electrode strip; the comb-shaped structure is composed of a plurality of second electrode strips and a plurality of slits arranged alternately.

[0008] Optionally, in the above-mentioned display panel provided by an embodiment of the present disclosure, the shape of the first electrode strip is a zigzag line.

[0009] Optionally, in the above display panel provided by an embodiment of the present disclosure, the first electrode strip is divided into a first sub-electrode strip and a second sub-electrode strip along the bending point;

[0010] The second electrode strips on both sides of the first sub-electrode strip correspond to each other and are located on the same straight line, and the second electrode strips on both sides of the second sub-electrode strip correspond to each other and are located on the same straight line.

[0011] Optionally, in the above-mentioned display panel provided by the embodiment of the present disclosure, the second electrode strips connected to the first sub-electrode strips are substantially parallel, and the second electrode strips connected to the second sub-electrode strips are substantially parallel.

[0012] Optionally, in the above-mentioned display panel provided by the embodiment of the present disclosure, the second electrode strip connected to the first sub-electrode strip has a first inclination angle with respect to the row direction, the second electrode strip connected to the second sub-electrode strip has a second inclination angle with respect to the row direction, and the first inclination angle and the second inclination angle are complementary.

[0013] Optionally, in the above-mentioned display panel provided by an embodiment of the present disclosure, the pixel electrode has a center line extending along a row direction, and the bending point is approximately located on the center line.

[0014] Optionally, in the above display panel provided by an embodiment of the present disclosure, the first electrode strip has a bending angle at a position corresponding to the bending point, and at one side of the bending angle and at a position close to the bending point, the first sub-electrode strip and the second sub-electrode strip are electrically connected to a plurality of second electrode strips correspondingly connected thereto;

[0015] On the opposite side of the bending angle and at the two side edges away from the bending point, the plurality of second electrode strips corresponding to the first sub-electrode strips are electrically connected, and the plurality of second electrode strips corresponding to the second sub-electrode strips are electrically connected;

[0016] The ends of the second electrode strips at the remaining positions that are away from the first electrode strips are independent of each other.

[0017] Optionally, the above-mentioned display panel provided in the embodiment of the present disclosure further includes a data line located between the base substrate and the pixel electrode layer, and the orthographic projection of the data line on the base substrate and the orthographic projection of the effective light-emitting area of ​​each sub-pixel on the base substrate have an overlapping area, and the shape of the overlapping area is a broken line.

[0018] Optionally, in the above-mentioned display panel provided by an embodiment of the present disclosure, the orthographic projection of the first electrode strip on the base substrate substantially overlaps with the orthographic projection of the overlapping area on the base substrate.

[0019] Optionally, in the above-mentioned display panel provided by an embodiment of the present disclosure, the overlapping area and the column direction form an isosceles triangle.

[0020] Optionally, in the above-mentioned display panel provided by the embodiment of the present disclosure, the bending angle of the overlapping area is greater than 90° and less than 180°.

[0021] Optionally, in the display panel provided by the embodiment of the present disclosure, one data line is correspondingly arranged for one column of sub-pixels;

[0022] Each of the data lines comprises a first sub-data line and a second sub-data line electrically connected to each other;

[0023] The orthographic projection of the first sub-data line on the base substrate and the orthographic projection of the effective light-emitting area of ​​the corresponding sub-pixel on the base substrate form the overlapping area;

[0024] The orthographic projection of the second sub-data line on the base substrate does not overlap with the orthographic projection of each of the effective light-emitting areas on the base substrate.

[0025] Optionally, in the above-mentioned display panel provided in the embodiment of the present disclosure, the display panel also includes: a first insulating layer located between the data line and the pixel electrode layer, a common electrode layer located between the first insulating layer and the pixel electrode layer, and a second insulating layer located between the common electrode layer and the pixel electrode layer; wherein the common electrode layer is a planar structure.

[0026] Optionally, in the above display panel provided by the embodiment of the present disclosure, the plurality of data lines include a plurality of first-type data lines and a plurality of second-type data lines; the first-type data lines and the second-type data lines are alternately arranged along the row direction of the sub-pixels;

[0027] Two adjacent columns of sub-pixels form a column group, and each two adjacent column groups correspond to one first-category data line; wherein the odd-numbered rows of sub-pixels in the first column group of each two adjacent column groups are all electrically connected to the corresponding first-category data lines, and the even-numbered rows of sub-pixels in the second column group are all electrically connected to the corresponding first-category data lines.

[0028] Optionally, in the above-mentioned display panel provided by the embodiment of the present disclosure, the display panel further comprises: a plurality of gate lines located between the data lines and the base substrate and insulated and cross-arranged with the data lines, a third insulating layer located between the data lines and the gate lines, and common electrode connection lines that are in the same layer as the gate lines and are arranged at intervals; wherein the gate lines extend along the row direction of the sub-pixels, and a row of the sub-pixels corresponds to two gate lines; the common electrode connection lines extend along the row direction of the sub-pixels, and the orthographic projection of the common electrode connection lines on the base substrate does not overlap with the orthographic projection of the effective light-emitting area on the base substrate;

[0029] The common electrode connection line is electrically connected to each of the second-type data lines through a via hole penetrating the third insulating layer, and the second-type data lines are electrically connected to the common electrode layer through a via hole penetrating the first insulating layer.

[0030] Optionally, the display panel provided in the embodiment of the present disclosure further includes a color resist layer located between the data line and the first insulating layer, and the color resist layer includes a plurality of color resists arranged corresponding to each of the sub-pixels.

[0031] Optionally, in the above-mentioned display panel provided by the embodiment of the present disclosure, the sub-pixels located in the same column are electrically connected to the same data line, and the sub-pixels located in different columns are electrically connected to different data lines.

[0032] Optionally, in the above-mentioned display panel provided by the embodiment of the present disclosure, the display panel further comprises: a plurality of gate lines located between the data lines and the base substrate and insulated and cross-arranged with the data lines, a third insulating layer located between the data lines and the gate lines, and common electrode connection lines that are in the same layer as the gate lines and are arranged at intervals; wherein the gate lines extend along the row direction of the sub-pixels, and one row of the sub-pixels corresponds to one gate line; the common electrode connection lines extend along the row direction of the sub-pixels, and the orthographic projection of the common electrode connection lines on the base substrate does not overlap with the orthographic projection of the effective light-emitting area on the base substrate;

[0033] The common electrode layer is electrically connected to each of the common electrode connection lines through via holes that sequentially penetrate the first insulating layer and the third insulating layer.

[0034] Optionally, in the above-mentioned display panel provided in the embodiment of the present disclosure, the display panel also includes: an opposing substrate arranged opposite to the base substrate, and a liquid crystal layer encapsulated between the base substrate and the opposing substrate; a color resist layer is arranged on the opposing substrate, and the color resist layer includes a plurality of color resists arranged corresponding to each of the sub-pixels.

[0035] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising any one of the display panels described above provided by the embodiment of the present disclosure.

[0036] Optionally, the above-mentioned display device provided in the embodiment of the present disclosure further includes: a grating located on the light emitting side of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a structural schematic diagram of a naked-eye 3D display device;

[0039] Figure 2 is a schematic diagram of the structure of a display panel in an embodiment of the present disclosure;

[0040] Figure 3 is a schematic diagram of a specific structure of a pixel electrode of a display panel in an embodiment of the present disclosure;

[0041] Figure 4 A schematic diagram of a specific structure of a pixel electrode in the related art;

[0042] Figure 5is a schematic diagram of the inclination angle of the second electrode strip according to an embodiment of the present disclosure;

[0043] Fig. 6A Some specific structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0044] Figure 6B for Fig. 6A Some structural diagrams of the layers where the data lines are located;

[0045] Figure 6C for Fig. 6A Some further structural schematic diagrams of the pixel electrode layer in FIG.

[0046] Fig. 7A Some further specific structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0047] Figure 7B for Fig. 7A Some structural diagrams of the layers where the data lines are located;

[0048] Figure 7C for Fig. 7A Some further structural schematic diagrams of the pixel electrode layer in FIG.

[0049] Figure 8A-8H for Fig. 6A Some structural schematic diagrams of the superposition of various film layers;

[0050] Figure 9A-9G for Fig. 7A Some other structural schematic diagrams of the superposition of the film layers. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0053] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0054] like Figure 1 As shown, the naked-eye 3D display device adopts a combined superposition mode of a light source 10, a display panel 20 and a grating 30, wherein the display panel 20 receives an external signal and displays a two-dimensional picture; and then refracts through the grating 30 in front of the screen to achieve parallax, form a three-dimensional effect, and allow the viewer 40 to see a 3D image.

[0055] When using a grating-type naked-eye 3D display device, due to the influence of the process of the display panel or other factors, the formed 3D display image may produce moiré patterns, thereby affecting the 3D display effect.

[0056] The present disclosure provides a display panel. Figure 2 and Figure 3 As shown, this may include:

[0057] A base substrate 1 having a plurality of rows and columns of sub-pixels P;

[0058] The pixel electrode layer 2 is located on the base substrate 1. The pixel electrode layer 2 includes a plurality of pixel electrodes 21 spaced apart from each other. One sub-pixel P includes one pixel electrode 21.

[0059] The pixel electrode 21 includes: a first electrode strip 211 and a comb-shaped structure 212 respectively connected to two sides of the first electrode strip 211; the comb-shaped structure 212 is composed of a plurality of second electrode strips 2121 and a plurality of slits 2122 arranged alternately.

[0060] Liquid Crystal Display (LCD) panels have the characteristics of being thin and light, power-saving, and radiation-free, and are widely used. The working principle of the LCD panel is to change the arrangement state of the liquid crystal molecules in the liquid crystal layer by changing the voltage difference across the liquid crystal layer, so as to change the light transmittance of the liquid crystal layer to display images. In specific implementation, the display panel in the embodiment of the present disclosure can be a liquid crystal display panel. For a liquid crystal display panel, the traditional pixel electrode structure design is as follows: Figure 4 As shown, the edge of the pixel electrode is an electrode skeleton (for transmitting signals), and the pixel electrode has a plurality of transverse slits 50 inside, and the liquid crystal is arranged along the slits 50; but when it reaches the edge of the pixel electrode, the liquid crystal at the edge of the pixel electrode is arranged disorderly due to the structure of the electrode skeleton to form a display dark area; therefore, there is a large display dark area between adjacent sub-pixels. The inventor of this case has found that the average width of the display dark area between adjacent sub-pixels is currently about 21 μm, which is not conducive to the elimination of moiré; the above-mentioned display panel provided by the embodiment of the present disclosure, by setting the pixel electrode to include a first electrode strip and a comb-like structure respectively connected to both sides of the first electrode strip, and the comb-like structure is composed of a plurality of second electrode strips and a plurality of slits arranged alternately, so that there is no electrode skeleton at the edge of the pixel electrode structure provided by the present disclosure, but the electrode skeleton (first electrode strip) is moved to the inside of the sub-pixel, that is, the edge of the pixel electrode structure is an open comb-like structure, so that the liquid crystal at the edge of the pixel electrode can be arranged in an orderly manner, so that the display dark area between the sub-pixels can be reduced. When the display panel provided by the embodiment of the present disclosure is applied to a 3D display device, the moiré can be improved and the display effect can be improved.

[0061] In a specific implementation, in an embodiment of the present disclosure, the display panel may include a display area, and the display area may include a plurality of pixel units arranged in an array. Each pixel unit includes a plurality of sub-pixels P. Exemplarily, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that a color display may be achieved by mixing red, green, and blue. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that a color display may be achieved by mixing red, green, blue, and white. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit may be designed and determined according to the actual application environment, and is not limited here.

[0062] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 3 As shown, the first electrode strip 211 is in a zigzag shape, which can avoid moiré caused by interference with the grating of the 3D display device, further eliminate moiré in the display image, and improve the display effect.

[0063] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 3 As shown, the first electrode strip 211 is divided into a first sub-electrode strip 2111 and a second sub-electrode strip 2112 along the bending point A;

[0064] The second electrode strips 2121 on both sides of the first sub-electrode strips 2111 correspond to each other and are located on the same straight line, and the second electrode strips 2121 on both sides of the second sub-electrode strips 2112 correspond to each other and are located on the same straight line. This is conducive to the regular arrangement of liquid crystal molecules and improves the display effect.

[0065] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 3 As shown, the second electrode strips 2121 connected to the first sub-electrode strips 2111 are substantially parallel, and the second electrode strips 2121 connected to the second sub-electrode strips 2112 are substantially parallel. In this way, when the liquid crystal display panel is displaying, all liquid crystal molecules can be arranged regularly, thereby improving the display effect.

[0066] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 5 As shown, the first sub-electrode strip 2111 is connected to the second electrode strip 2121 ( Figure 5 The second electrode strip 2121 (denoted by 2121' in the figure) has a first inclination angle α1 with the row direction F2, and the second sub-electrode strip 2112 is connected to the second electrode strip 2121 ( Figure 5 The pixel electrodes in the same sub-pixel have second electrode strips 2121 with complementary inclination angles. Under this arrangement, the brightness of the same sub-pixel can be complementary, thereby avoiding the occurrence of horizontal stripes.

[0067] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 3 As shown, the pixel electrode 21 has a center line L extending along the row direction F2, and the bending point A is approximately located on the center line L. Due to the influence of the manufacturing process, the position of the bending point A and the center line L may have a certain error. This structure can maximize the improvement of moiré defects.

[0068] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 3 As shown, the first electrode strip 211 has a bending angle β at a position corresponding to the bending point A, and at one side of the bending angle β and at a position close to the bending point A (at the elliptical dotted frame T1), the first sub-electrode strip 2111 and the second sub-electrode strip 2112 are electrically connected to a plurality of second electrode strips 2121 correspondingly connected thereto;

[0069] On the opposite side of the bending angle β and at the two side edges away from the bending point A (at the elliptical dotted frame T2), the plurality of second electrode strips 2121 correspondingly connected to the first sub-electrode strip 2111 are electrically connected, and the plurality of second electrode strips 2121 correspondingly connected to the second sub-electrode strip 2112 are electrically connected;

[0070] The ends of the second electrode strips 2121 at the remaining positions that are away from the first electrode strip 211 are independent of each other, that is, the edge of the pixel electrode structure is set as an open comb structure, so that the liquid crystal at the edge of the pixel electrode can be arranged in an orderly manner, the dark area displayed between sub-pixels can be reduced, the moiré pattern can be improved, and the display effect can be improved.

[0071] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Fig. 6A and Fig. 7A As shown, Fig. 6A A top view of a display panel with a dual-gate structure and RGB color resistance on the array substrate side. Fig. 7A A schematic top view of a display panel having a single-gate structure and no RGB color resistance (mainly used for precise light control) on the array substrate side, the display panel further includes a data line 3 located between the base substrate 1 and the pixel electrode layer 2, the orthographic projection of the data line 3 on the base substrate 1 and the orthographic projection of the effective light-emitting area AA of each sub-pixel on the base substrate 1 have an overlapping area DD, and the shape of the overlapping area DD is a zigzag shape. Such a zigzag-shaped data line 3 can avoid moiré caused by interference with the grating of the 3D display device, can further eliminate moiré in the display image, and improve the display effect.

[0072] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 6B , Figure 6C , Figure 7B and Figure 7C As shown, Figure 6B for Fig. 6A The data line 3 structure in Figure 6C for Fig. 6A The pixel electrode 21 structure in Figure 7B for Fig. 7A The data line 3 structure in Figure 7C for Fig. 7A In the structure of the pixel electrode 21 in FIG. 1 , the orthographic projection of the first electrode strip 211 on the base substrate 1 roughly overlaps with the orthographic projection of the overlapping area DD on the base substrate 1. In this way, the skeleton of the pixel electrode 21 (the first electrode strip 211) is arranged along the data line 3, so that the liquid crystal disorder area overlaps with the metal light shielding area (overlapping area DD), and the rest of the pixel electrode 21 adopts a transverse open comb structure, ultimately achieving the ultimate minimization of the dark area between sub-pixels.

[0073] In order to improve the serious moiré defect, the inventor of this case designed a variety of shading patterns (overlapping area DD patterns) on the mask, and evaluated the effect of eliminating moiré with the grating of the client, and finally verified an optimal overlapping area DD pattern: an obtuse isosceles triangle. Therefore, in the specific implementation, in the above-mentioned display panel provided in the embodiment of the present disclosure, if Figure 6B and Figure 7B As shown, the overlapping area DD forms an isosceles triangle with the column direction F1, and the bending angle β of the overlapping area DD is greater than 90° and less than 180°. For example, the bending angle β of the overlapping area DD can be set to 114°, and an angle θ1 between the zigzag overlapping area DD and the column direction F1 of the sub-pixel P can be set to 32°, and another angle θ2 between the zigzag overlapping area DD and the column direction F1 of the sub-pixel P can be set to 32°. The long side of the bending angle β is arranged along the long side of the sub-pixel (column direction F1), and the width of the shading area (the long side of β) is as small as 2μm as possible to eliminate moiré, and the width of the other two sides is unlimited.

[0074] Of course, in practical applications, the specific values ​​of β, θ1 and θ2 can be designed according to the requirements of the practical application and are not limited here.

[0075] In specific implementation, Figure 6B and Figure 7B As shown, considering that the width of the long side shading area of ​​the obtuse triangle is only 2μm, and the long side of the obtuse triangle is arranged along the long side of the sub-pixel, the width of 2μm is currently difficult to achieve through the production of the black matrix (BM). Therefore, the long side shading area of ​​the obtuse triangle in the embodiment of the present disclosure can be made of the metal layer where the gate line is located or the metal layer where the data line is located, to achieve the shading effect; the other two sides of the obtuse triangle can be wider data lines, which can transmit data signals and achieve the shading effect. It should be noted that the embodiment of the present disclosure Figure 6B and Figure 7B The shading area of ​​the long side of the obtuse triangle is not set, but it can be set.

[0076] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 2 , Fig. 6A , Figure 6B , Fig. 7A and Figure 7B As shown, one column of sub-pixels P is correspondingly provided with one data line (D1 or D2);

[0077] Each data line (D1, D2) includes a first sub-data line D01 and a second sub-data line D02 electrically connected to each other;

[0078] The orthographic projection of the first sub-data line D01 on the base substrate 1 and the orthographic projection of the effective light emitting area AA of the corresponding sub-pixel P on the base substrate 1 form an overlapping area DD;

[0079] The orthographic projection of the second sub-data line D02 on the base substrate 1 does not overlap with the orthographic projection of each effective light-emitting area AA on the base substrate 1. Exemplarily, the orthographic projection of the second sub-data line D02 on the base substrate 1 is located between the orthographic projections of adjacent effective light-emitting areas AA on the base substrate 1. In this way, the data line can be reused as a light-shielding pattern to avoid interference with the grating, which can reduce the difficulty of process preparation and reduce the thickness of the display panel.

[0080] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Fig. 6A and Fig. 7A As shown, the display panel further includes: a first insulating layer 4 between the data line 3 and the pixel electrode layer 2, a common electrode layer 5 between the first insulating layer 4 and the pixel electrode layer 2, and a second insulating layer 6 between the common electrode layer 5 and the pixel electrode layer 2; wherein the common electrode layer 5 is a planar structure. The planar structure of the common electrode layer 5 covers the signal line (such as the data line) in the column direction F1, which can shield the constantly changing electric field below. There is no light leakage between adjacent pixels in the column direction F1, and no vertical light shielding layer (BM) is required to cover. The simulation light effect results show that the width of the dark area displayed in the column direction F1 between sub-pixels can be as small as 3.5μm.

[0081] Specifically, an electric field is formed through the pixel electrode 21 and the common electrode layer 5 to drive the liquid crystal molecules of the liquid crystal display to deflect.

[0082] Fig. 6A The dual-gate display panel can minimize the dark area between sub-pixels, so the RGB color resistance can be placed on the array substrate side, which can more effectively avoid the risk of cross-color caused by the box (array substrate + color film substrate). Considering that the basic aperture ratio of the dual-gate product is lower than that of the single-gate, the solution of the embodiment of the present disclosure is more meaningful for the improvement of the dual-gate product.

[0083] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 2 and Fig. 6AAs shown, the plurality of data lines 3 include a plurality of first-type data lines D1 and a plurality of second-type data lines D2; the first-type data lines D1 and the second-type data lines D2 are alternately arranged along the row direction F2 of the sub-pixels P. The first-type data lines D1 are electrically connected to the thin-film transistors TFT in the sub-pixels P, and the second-type data lines D2 are not electrically connected to the thin-film transistors TFT in the sub-pixels P. Exemplarily, the first-type data lines D1 may be arranged corresponding to the sub-pixels P in the odd columns, and the second-type data lines D2 may be arranged corresponding to the sub-pixels P in the even columns. Alternatively, the second-type data lines D2 may be arranged corresponding to the sub-pixels P in the odd columns, and the first-type data lines D1 may be arranged corresponding to the sub-pixels P in the even columns.

[0084] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 2 and Fig. 6A As shown, two adjacent columns of sub-pixels P form a column group, and each two adjacent column groups correspond to a first-type data line D1; wherein, the odd-numbered rows of sub-pixels P in the first column group of each two adjacent column groups are electrically connected to the corresponding first-type data line D1, and the even-numbered rows of sub-pixels P in the second column group are electrically connected to the corresponding first-type data line D1.

[0085] Exemplarily, the first column of sub-pixels P and the second column of sub-pixels P form a column group B1, the third column of sub-pixels P and the fourth column of sub-pixels P form a column group B2, and the fifth column of sub-pixels P and the sixth column of sub-pixels P form a column group B3. The column group B1 corresponds to the first second-category data line D2, the column group B2 corresponds to the second second-category data line D2, the column group B3 corresponds to the third second-category data line D2, the adjacent column group B1 and column group B2 correspond to the first first-category data line D1, and the adjacent column group B2 and column group B3 correspond to the second first-category data line D1. In the adjacent column group B1 and column group B2, the column group B1 serves as the first column group, the column group B2 serves as the second column group, and the odd-numbered row sub-pixels P of the column group B1 are all electrically connected to the corresponding first-category data line D1, and the even-numbered row sub-pixels P of the column group B2 are all electrically connected to the corresponding first-category data line D1. In the adjacent column group B2 and column group B3, the column group B2 is used as the first column group, the column group B3 is used as the second column group, and the odd-numbered sub-pixels P of the column group B2 are all electrically connected to the corresponding first-type data lines D1, and the even-numbered sub-pixels P of the column group B3 are all electrically connected to the corresponding first-type data lines D1. The rest is similar, and so on, which will not be described here.

[0086] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if FIG. 8A to FIG. 8H As shown, FIG. 8A to FIG. 8H for Fig. 6AA schematic diagram of the superimposed layout of each film layer, wherein the display panel further comprises: a plurality of gate lines (G1, G2) located between the data line 3 and the base substrate 1 and insulated and cross-arranged with the data line 3, a third insulating layer (not shown) located between the data line 3 and the gate line (G1, G2), and a common electrode connection line 7 which is in the same layer as the gate line (G1, G2) and is arranged at intervals; wherein the gate lines (G1, G2) extend along the row direction F2 of the sub-pixels, and one row of sub-pixels corresponds to two gate lines (G1, G2); the common electrode connection line 7 extends along the row direction F2 of the sub-pixels P, and the orthographic projection of the common electrode connection line 7 on the base substrate 1 does not overlap with the orthographic projection of the effective light-emitting area AA on the base substrate 1;

[0087] The common electrode connection line 7 is electrically connected to each second-class data line D2 through a via hole penetrating the third insulating layer, so that the spaced common electrode connection lines 7 can be electrically connected through the second-class data line D2. The second-class data line D2 and the common electrode connection line 7 transmit the same voltage, which can avoid signal interference between the second-class data line D2 and the common electrode layer 5; the second-class data line D2 is electrically connected to the common electrode layer 5 through a via hole penetrating the first insulating layer 4, so that the common electrode connection line 7, the second-class data line D2 and the common electrode layer 5 can be electrically connected to form a parallel effect, thereby also achieving the effect of reducing resistance.

[0088] For example, FIG. 8A to FIG. 8H As shown, the orthographic projections of the gate lines (G1, G2) on the substrate 1 are located between the orthographic projections of the effective light-emitting areas AA of the two adjacent rows of sub-pixels P on the substrate 1. In addition, the two gate lines (G1, G2) corresponding to the sub-pixels P in the same row are respectively located on both sides of the sub-pixels P in the corresponding row. For example, one of the two gate lines (G1, G2) corresponding to the sub-pixels P in the same row (such as GA1) is electrically connected to the thin film transistors in the sub-pixels P in the odd columns of the row, and the other gate line (such as GA2) is electrically connected to the thin film transistors in the sub-pixels P in the even columns of the row. The gate line (such as GA1) electrically connected to the thin film transistors in the sub-pixels P in the odd columns of the row can be set above the row, and the gate line (such as GA2) electrically connected to the thin film transistors in the sub-pixels P in the even columns of the row can be set below the row.

[0089] Exemplarily, one row of sub-pixels P corresponds to one common electrode connection line 7 , and the common electrode connection line 7 is located between the sub-pixels P in the corresponding row and the gate line arranged above the sub-pixels P in the row.

[0090] Exemplarily, the orthographic projection of the via hole penetrating the third insulating layer on the substrate substrate 1 may be located inside the orthographic projection of the via hole penetrating the first insulating layer 4 on the substrate substrate 1. Alternatively, the orthographic projection of the via hole penetrating the first insulating layer 4 on the substrate substrate 1 may be located inside the orthographic projection of the via hole penetrating the third insulating layer on the substrate substrate 1. Alternatively, the orthographic projection of the via hole penetrating the third insulating layer on the substrate substrate 1 may only partially overlap with the orthographic projection of the via hole penetrating the first insulating layer 4 on the substrate substrate 1. Alternatively, the orthographic projection of the via hole penetrating the third insulating layer on the substrate substrate 1 may not overlap with the orthographic projection of the via hole penetrating the first insulating layer 4 on the substrate substrate 1.

[0091] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if FIG. 8A to FIG. 8H As shown, a color resist layer is also included between the data line 3 and the first insulating layer 4 , and the color resist layer includes a plurality of color resists (R, G, B) arranged corresponding to each sub-pixel P.

[0092] Fig. 7A The array substrate in the display panel of the single-gate structure shown is mainly used for precise light control without the need for color resistance. On the one hand, the pixel should have the highest possible aperture ratio and transmittance; on the other hand, considering the moiré pattern, the data line is usually required to be bent at a specific angle. Based on this, the sub-pixel using a single-gate structure has a larger aperture ratio, and the moiré pattern can be reduced by bending the data line at a specific angle. The design structure disclosed in the present invention is further adopted, in which the skeleton of the pixel electrode 21 (the first electrode strip 211) is arranged along the data line, so that the liquid crystal disorder area coincides with the metal shading area; the rest of the pixel electrode 21 adopts a transverse open comb structure, which ultimately achieves the ultimate minimization of the dark area between pixels.

[0093] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Fig. 7A As shown, the sub-pixels P in the same column are electrically connected to the same data line D1 , and the sub-pixels P in different columns are electrically connected to different data lines D1 .

[0094] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if FIG. 9A to FIG. 9G As shown, FIG. 9A to FIG. 9G for Fig. 7ASchematic diagram of the superimposed layout of each film layer, the display panel further includes: a plurality of gate lines G1 located between the data line 3 and the base substrate 1 and insulated and cross-arranged with the data line 3, a third insulating layer (not shown) located between the data line 3 and the gate line G1, and a common electrode connection line 7 arranged in the same layer as the gate line G1 and spaced apart; wherein the gate line G1 extends along the row direction F2 of the sub-pixel, and one row of sub-pixels corresponds to one gate line G1; the common electrode connection line 7 extends along the row direction F2 of the sub-pixel P, and the orthographic projection of the common electrode connection line 7 on the base substrate 1 does not overlap with the orthographic projection of the effective light-emitting area AA on the base substrate 1;

[0095] The common electrode layer 5 is electrically connected to each common electrode connection line 7 through via holes that sequentially penetrate the first insulating layer 4 and the third insulating layer.

[0096] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if FIG. 9A to FIG. 9G As shown, the display panel also includes: an opposing substrate (not shown) arranged opposite to the base substrate 1, and a liquid crystal layer (not shown) encapsulated between the base substrate 1 and the opposing substrate; a color resist layer (not shown) is arranged on the opposing substrate, and the color resist layer includes a plurality of color resists arranged corresponding to each sub-pixel P. The color of the color resist is consistent with the luminous color of the corresponding sub-pixel P. In addition, the sub-pixel P may also include a thin film transistor TFT electrically connected to the pixel electrode 21. A gate scan signal is input to the TFT through the gate line G1 to control the TFT to be turned on, so that the data signal transmitted on the data line 3 is input to the pixel electrode 21, so that the pixel electrode is input with a voltage, and a common voltage is input to the common electrode layer 5 to drive the liquid crystal molecules to rotate to display an image.

[0097] In specific implementation, FIG. 8A to FIG. 8H , FIG. 9A to FIG. 9G As shown, the pixel electrode 21 and the common electrode layer 5 are generally made of transparent conductive material ITO. Since the pixel electrode 21 provided in the embodiment of the present disclosure is designed as the top layer of ITO, it is far away from the film layer where the data line and the film layer where the gate line are located below, thereby reducing signal crosstalk.

[0098] In specific implementation, FIG. 8A to FIG. 8H , FIG. 9A to FIG. 9G As shown, a gate insulating layer may be disposed between the layer where the gate lines ( G1 and G2 ) are located and the base substrate 1 , and an active layer 8 of the thin film transistor may be disposed between the gate insulating layer and the base substrate 1 .

[0099] In specific implementation, FIG. 8A to FIG. 8H , FIG. 9A to FIG. 9GAs shown, in the embodiment of the present disclosure, the overlapping area with the pixel electrode 21 and the common electrode layer 5 increases due to the bending of the data line 3. By placing a first insulating layer 4 between the data line 3 and the pixel electrode layer 2, the material of the first insulating layer 4 can be an organic material. The use of an organic film process can reduce the coupling capacitance and ensure the pixel charging rate and picture quality.

[0100] The inventor of this case conducted a light efficiency simulation on the pixel electrode structure provided in the embodiment of the present disclosure. The simulation results show that the minimum width of the dark area displayed in the vertical direction between sub-pixels can be as low as 3.5μm, and the average width of the dark area displayed between sub-pixels is only 7μm. The level of moiré defects is significantly reduced, accumulating a technical foundation for subsequent product development.

[0101] Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, including the display panel provided by the embodiment of the present disclosure. The principle of solving the problem by the display device is similar to that of the display panel, so the implementation of the display device can refer to the implementation of the display panel, and the repeated parts will not be repeated here.

[0102] In specific implementation, in the embodiment of the present disclosure, the display device may further include: a grating located on the light-emitting side of the display panel, wherein the grating is used to enable the display device to achieve a 3D display effect, so that the display device in the embodiment of the present disclosure can achieve a 3D display effect.

[0103] The display panel and display device provided by the embodiments of the present disclosure, by setting the pixel electrode to include a first electrode strip and a comb-like structure respectively connected to both sides of the first electrode strip, and the comb-like structure is composed of a plurality of second electrode strips and a plurality of slits arranged alternately, so that there is no electrode skeleton at the edge of the pixel electrode structure provided by the present disclosure, but the electrode skeleton (first electrode strip) is moved to the inside of the sub-pixel, that is, the edge of the pixel electrode structure is an open comb-like structure, so that the liquid crystal at the edge of the pixel electrode can be arranged in an orderly manner, so that the displayed dark area between the sub-pixels can be reduced. When the display panel provided by the embodiments of the present disclosure is applied to a 3D display device, the moiré pattern can be improved and the display effect can be enhanced.

[0104] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: include: A substrate having a plurality of rows and columns of sub-pixels; A pixel electrode layer, located on the base substrate, the pixel electrode layer includes a plurality of pixel electrodes arranged at intervals from each other, and one sub-pixel includes one pixel electrode; The data line is located between the base substrate and the pixel electrode layer; the data line includes a plurality of first-type data lines and a plurality of second-type data lines; wherein, The first type of data lines and the second type of data lines are alternately arranged along the row direction of the sub-pixels; Two adjacent columns of sub-pixels are formed into a column group, and each of the two adjacent column groups corresponds to one of the first-type data lines; wherein the odd-numbered rows of sub-pixels in the first column group of each of the two adjacent column groups are all electrically connected to the corresponding first-type data lines, and the even-numbered rows of sub-pixels in the second column group are all electrically connected to the corresponding first-type data lines; The pixel electrode comprises: a first electrode strip, and a comb-shaped structure respectively connected to two sides of the first electrode strip; the comb-shaped structure is composed of a plurality of second electrode strips and a plurality of slits arranged alternately.

2. The display panel according to claim 1, wherein: The first electrode strip is in a zigzag shape.

3. The display panel according to claim 2, wherein: The first electrode strip is divided into a first sub-electrode strip and a second sub-electrode strip along a bending point; The second electrode strips on both sides of the first sub-electrode strip correspond to each other and are located on the same straight line, and the second electrode strips on both sides of the second sub-electrode strip correspond to each other and are located on the same straight line.

4. The display panel according to claim 3, wherein: The second electrode strips connected to the first sub-electrode strips are substantially parallel, and the second electrode strips connected to the second sub-electrode strips are substantially parallel.

5. The display panel according to claim 4, wherein: The second electrode strips connected to the first sub-electrode strips have a first tilt angle with respect to the row direction, and the second electrode strips connected to the second sub-electrode strips have a second tilt angle with respect to the row direction, and the first tilt angle and the second tilt angle are complementary.

6. The display panel according to claim 3, wherein: The pixel electrode has a center line extending along a row direction, and the bending point is substantially located on the center line.

7. The display panel according to claim 6, wherein: The first electrode strip has a bending angle at a position corresponding to the bending point, and at one side of the bending angle and close to the bending point, the first sub-electrode strip and the second sub-electrode strip are electrically connected to a plurality of second electrode strips correspondingly connected thereto; On the opposite side of the bending angle and at the two side edges away from the bending point, the plurality of second electrode strips corresponding to the first sub-electrode strips are electrically connected, and the plurality of second electrode strips corresponding to the second sub-electrode strips are electrically connected; The ends of the second electrode strips at the remaining positions that are away from the first electrode strips are independent of each other.

8. The display panel according to claim 1, wherein: The orthographic projection of the data line on the base substrate and the orthographic projection of the effective light emitting area of ​​each sub-pixel on the base substrate have an overlapping area, and the shape of the overlapping area is a broken line.

9. The display panel according to claim 8, wherein: An orthographic projection of the first electrode strip on the base substrate substantially overlaps with an orthographic projection of the overlapping region on the base substrate.

10. The display panel according to claim 9, wherein: The overlapping area and the column direction form an isosceles triangle.

11. The display panel according to claim 10, wherein: The bending angle of the overlapping area is greater than 90° and less than 180°.

12. The display panel according to claim 8, wherein: One column of the sub-pixels is correspondingly provided with one data line; Each of the data lines comprises a first sub-data line and a second sub-data line electrically connected to each other; The orthographic projection of the first sub-data line on the base substrate and the orthographic projection of the effective light-emitting area of ​​the corresponding sub-pixel on the base substrate form the overlapping area; The orthographic projection of the second sub-data line on the base substrate does not overlap with the orthographic projection of each of the effective light-emitting areas on the base substrate.

13. The display panel according to claim 8, wherein: The display panel further includes: a first insulating layer located between the data line and the pixel electrode layer, a common electrode layer located between the first insulating layer and the pixel electrode layer, and a second insulating layer located between the common electrode layer and the pixel electrode layer; wherein the common electrode layer is a planar structure.

14. The display panel according to claim 13, wherein: The display panel further comprises: a plurality of gate lines located between the data lines and the base substrate and insulated and cross-arranged with the data lines, a third insulating layer located between the data lines and the gate lines, and common electrode connection lines which are in the same layer as the gate lines and are arranged at intervals; wherein the gate lines extend along the row direction of the sub-pixels, and a row of the sub-pixels corresponds to two gate lines; the common electrode connection lines extend along the row direction of the sub-pixels, and the orthographic projection of the common electrode connection lines on the base substrate does not overlap with the orthographic projection of the effective light-emitting area on the base substrate; The common electrode connection line is electrically connected to each of the second-type data lines through a via hole penetrating the third insulating layer, and the second-type data lines are electrically connected to the common electrode layer through a via hole penetrating the first insulating layer.

15. The display panel according to claim 14, wherein: It also includes a color resist layer located between the data line and the first insulating layer, and the color resist layer includes a plurality of color resists arranged corresponding to each of the sub-pixels.

16. The display panel according to claim 13, wherein: The sub-pixels in the same column are electrically connected to the same data line, and the sub-pixels in different columns are electrically connected to different data lines.

17. The display panel according to claim 16, wherein: The display panel further comprises: a plurality of gate lines located between the data lines and the base substrate and insulated and cross-arranged with the data lines, a third insulating layer located between the data lines and the gate lines, and common electrode connection lines that are in the same layer as the gate lines and are spaced apart; wherein the gate lines extend along the row direction of the sub-pixels, and a row of the sub-pixels corresponds to one gate line; the common electrode connection lines extend along the row direction of the sub-pixels, and the orthographic projection of the common electrode connection lines on the base substrate does not overlap with the orthographic projection of the effective light-emitting area on the base substrate; The common electrode layer is electrically connected to each of the common electrode connection lines through via holes that sequentially penetrate the first insulating layer and the third insulating layer.

18. The display panel according to claim 17, wherein: The display panel further includes: an opposing substrate arranged opposite to the base substrate, and a liquid crystal layer encapsulated between the base substrate and the opposing substrate; a color resist layer is arranged on the opposing substrate, and the color resist layer includes a plurality of color resists arranged corresponding to each of the sub-pixels.

19. A display device, wherein: Comprising a display panel as described in any one of claims 1-18.

20. The display device according to claim 19, wherein: Also includes: A grating is located on the light-emitting side of the display panel.

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