Wiring data generating device, drawing system, and wiring data generating method

Abstract

The design wiring data acquisition unit (820) of the present invention acquires design wiring data for showing a design wiring (411D), the design wiring (411D) being used to connect a component electrode (311) located at a design position (311pd) on a substrate (W) and a connection target electrode (321). The local wiring data generation unit (830) generates local wiring data for showing a local wiring (411R), the local wiring (411R) being obtained by deleting a portion surrounding the design position (311pd) of the component electrode (311) in the design wiring (411D). The actual position data acquisition unit (860) acquires actual position data, the actual position data showing an actual position (311pr) of the component electrode (311) on the substrate (W). A correction wiring data generating unit (880) generates correction wiring data for indicating a correction wiring (411C) for connecting a local wiring (411R) and an element electrode (311) located at an actual position (311pr).

Description

Technical Field

[0001] The present invention relates to a wiring data generating device, a drawing system and a wiring data generating method. Background Art

[0002] In chip-first SIP (System in Package) or WLP (Wafer Level Package) manufacturing processes, wiring between integrated circuits (ICs) or between IC pads and bumps is performed using a rewiring layer. This requires accounting for placement errors within the ICs bonded to a substrate, which serves as a support.

[0003] When performing exposure processing to form a rewiring layer using a mask-based stepper, the position and angle of the exposure overlap are fine-tuned to account for configuration errors. However, there are limits to how well these fine-tuning adjustments can accommodate these errors. In particular, when performing a single exposure to form a rewiring layer for multiple ICs arranged on a substrate, since each IC typically has its own configuration errors, it is difficult to fully accommodate these configuration errors simply by fine-tuning the overlap during a single exposure. Insufficient alignment with these configuration errors can lead to poor connections in the rewiring layer.

[0004] In contrast, there is a known technique for performing direct exposure by scanning the exposure light beam without using a mask. This technique is easier to cope with IC configuration errors than with methods using a mask. That is, when there is a configuration error, the wiring pattern is redesigned from the beginning to correspond to the configuration error, thereby generating wiring data to show the corrected wiring pattern. The wiring data generated is usually in a format used for mask CAD (Computer Aided Design), and in this case is subjected to RIP (Raster Image Processing) for the drawing device, thereby being converted into drawing data in the form of raster data. The drawing device uses the drawing data for direct exposure. However, the generation of wiring data caused by this redesign requires a huge computational burden. Therefore, a technique has been proposed to shorten the time required to generate wiring data corresponding to the configuration error in the direct exposure technique.

[0005] For example, Japanese Patent Publication No. 2016-71022 (Patent Document 1) discloses a method for generating connection wiring data for showing a connection wiring pattern. The connection wiring pattern electrically connects the various electrodes of the semiconductor chip configured on the substrate and the connection target electrodes provided on the substrate based on the predetermined connection relationship specified by the network online table (netlist). In this method, the reference chip is defined by the chip state, and the chip state is a state in which the semiconductor chip is configured on the substrate at a predetermined reference position and a predetermined reference angle. In the state in which the reference chip is configured at the reference position at the reference angle, a reference fan-out wiring of the reference chip area is generated. In addition, a network online table is generated for the object wiring pattern of the rewiring area adjacent to the chip area. Moreover, in response to the configuration error of the semiconductor chip, a fan-out wiring for the semiconductor chip on the substrate is generated from the reference fan-out wiring; based on the network online table, the error rewiring object wiring pattern is configured in a manner connected to the fan-out wiring of the semiconductor chip, thereby generating a new wiring pattern. According to this technology, since it is not necessary to redesign the wiring pattern from the beginning, wiring data corresponding to the layout error can be efficiently generated.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-71022 Summary of the Invention

[0009] Problems to be solved by the invention

[0010] The premise of the technology in the above-mentioned publication is that the connection wiring pattern has: one end, which is composed of fan-out wiring in the reference chip area; and the other end, which is composed of the target wiring pattern in the rewiring area outside the reference chip area. The above-mentioned one end of the connection wiring pattern is connected to the electrode of the semiconductor chip, and the above-mentioned other end of the connection wiring pattern is connected to the connection target electrode. Therefore, the position of the connection target electrode is taken as the position of the other end of the connection wiring pattern, that is, as the position outside the reference chip area in the planar layout. On the other hand, in recent years, a wiring pattern in which the connection target electrode at least partially overlaps with the semiconductor chip (more broadly speaking, an electrical component) has also been required in the planar layout. However, since the technology in the above-mentioned publication is based on the premise that the connection target electrode is located outside the area of ​​the semiconductor chip, it cannot meet the needs.

[0011] The present invention has been developed to solve the above-mentioned problems, and its purpose is to provide a wiring data generation device, a drawing system and a wiring data generation method, which can correspond to the position offset of the electrical components on the substrate and efficiently generate wiring data for showing wiring, which is used to connect the electrodes of the electrical components arranged on the substrate and the connection target electrodes arranged in a manner that at least partially overlaps with the electrical components in the planar layout.

[0012] Means used to solve problems

[0013] A first embodiment provides a wiring data generation device that generates wiring data representing wiring that electrically connects a component electrode of an electrical component already arranged on a substrate and a connection target electrode arranged so as to at least partially overlap the electrical component in a planar layout. The wiring data generation device includes a design wiring data acquisition unit, a local wiring data generation unit, an actual position data acquisition unit, and a corrected wiring data generation unit. The design wiring data acquisition unit acquires design wiring data representing design wiring that connects the component electrode and the connection target electrode at their designed positions on the substrate. The local wiring data generation unit generates local wiring data representing local wiring that is obtained by deleting portions of the design wiring surrounding the designed positions of the component electrodes. The actual position data acquisition unit acquires actual position data representing the actual positions of the component electrodes on the substrate. The correction wiring data generating unit generates correction wiring data indicating correction wiring for connecting the local wiring and the element electrode located at the actual position to each other.

[0014] The wiring data generating device of the second embodiment is the wiring data generating device described in the first embodiment, wherein the correction wiring data generating unit includes a via position obtaining unit for obtaining a via position; the correction wiring data generating unit generates the correction wiring data in a manner such that the correction wiring passes through the via position obtained by the via position obtaining unit.

[0015] The wiring data generating device of the third embodiment is the wiring data generating device described in the first embodiment or the second embodiment, which further comprises: a design wiring generating unit that generates the design wiring data based on the design position of the element electrode of the electrical element and the assumed position for configuring the connection target electrode; and the design wiring data acquiring unit that acquires the design wiring data generated by the design wiring generating unit.

[0016] The wiring data generating device of the fourth embodiment is the wiring data generating device described in any one of the first to third embodiments, wherein the correction wiring data generating unit includes a determination unit that determines whether the correction wiring data can be normally generated.

[0017] The wiring data generating device of the fifth embodiment is the wiring data generating device described in the fourth embodiment, further comprising: an error position generating unit, which generates an error position based on a predetermined rule, and the error position has an error of the element electrode from the design position; the judgment unit assumes that the actual position is located at the error position to judge whether the corrected wiring data can be generated normally.

[0018] The sixth embodiment is a drawing system, which comprises: a wiring data generating device as described in any one of the first to fifth embodiments; a table for holding the substrate; a shooting unit for shooting the electrical component in order to calculate actual position data, the actual position data indicating the actual position of the component electrode of the electrical component on the substrate held on the table; and an optical head for directly exposing the substrate based on the wiring data generated by the wiring data generating device.

[0019] A seventh embodiment is a wiring data generation method for generating wiring data representing wiring that electrically connects a component electrode of an electrical component already arranged on a substrate and a connection target electrode arranged so as to at least partially overlap the electrical component in a planar layout. The wiring data generation method comprises a design wiring data acquisition step, a local wiring data generation step, an actual position data acquisition step, and a corrected wiring data generation step. The design wiring data acquisition step acquires design wiring data representing design wiring that connects the component electrode and the connection target electrode at the designed position on the substrate. The local wiring data generation step generates local wiring data representing local wiring that is obtained by deleting a portion of the design wiring surrounding the designed position of the component electrode. The actual position data acquisition step acquires actual position data representing the actual position of the component electrode on the substrate. The correction wiring data generating step generates correction wiring data indicating correction wiring for connecting the local wiring and the element electrode located at the actual position to each other.

[0020] The wiring data generation method of the eighth embodiment is the wiring data generation method described in the seventh embodiment, wherein the correction wiring data generation step includes a via position acquisition step for obtaining a via position; the correction wiring data generation step generates the correction wiring data in a manner such that the correction wiring passes through the via position obtained by the via position acquisition step.

[0021] The wiring data generation method of the ninth embodiment is the wiring data generation method described in the seventh embodiment or the eighth embodiment, which further comprises: a design wiring generation step for generating the design wiring data based on the design position of the component electrode of the electrical component and the assumed position for configuring the connection target electrode; and the design wiring data acquisition step for acquiring the design wiring data generated by the design wiring generation step.

[0022] Effects of the Invention

[0023] According to the first embodiment, the wiring data generation device uses the local wiring corresponding to the portion of the designed wiring outside the periphery of the designed position of the component electrode of the electrical component as part of the generated wiring data. Therefore, the wiring data can be generated efficiently. Furthermore, the wiring data generation device generates, as another part of the generated wiring data, correction wiring data for indicating the correction wiring, which is used to connect the local wiring and the component electrode at the actual position, thereby making it possible to perform corrections corresponding to the offset between the designed position and the actual position of the electrical component on the substrate. As described above, corrections corresponding to the offset of the electrical component on the substrate from the designed position can be performed, and the wiring data can be generated efficiently.

[0024] According to the second embodiment, the wiring data generation device generates the correction wiring data so that the correction wiring passes through the route position obtained by the route position acquisition unit. This avoids unnecessary expansion of the design freedom of the correction wiring. Consequently, the automatic generation of the correction wiring can be made more efficient.

[0025] According to the third embodiment, the design wiring data acquisition unit of the wiring data generation device acquires the design wiring data generated by the design wiring generation unit of the wiring data generation device. Therefore, the design wiring data can be prepared in the wiring data generation device itself.

[0026] According to the fourth embodiment, the correction wiring data generating unit of the wiring data generating device includes a determination unit that determines whether the correction wiring data can be generated normally. Therefore, it is possible to avoid using abnormal correction wiring data during the process.

[0027] According to the fifth embodiment, the wiring data generating device determines whether the corrected wiring data can be generated normally, assuming that the actual position is at the error position. Therefore, the determination can be made before the actual position is obtained. Therefore, the determination can be made at an earlier stage.

[0028] According to the sixth embodiment, the substrate can be directly exposed using the wiring data generating device.

[0029] According to the seventh embodiment, the wiring data generation method utilizes the local wiring corresponding to the portion of the designed wiring outside the periphery of the designed position of the component electrode of the electrical component as part of the generated wiring data. Therefore, the wiring data can be generated efficiently. Furthermore, the wiring data generation method generates, as another part of the generated wiring data, correction wiring data indicating the correction wiring that connects the local wiring and the component electrode at the actual position, thereby enabling corrections to be made corresponding to the offset between the designed position and the actual position of the electrical component on the substrate. As described above, corrections can be made corresponding to the offset of the electrical component on the substrate from the designed position, and the wiring data can be generated efficiently.

[0030] According to the eighth embodiment, the wiring data generation method generates corrected wiring data so that the corrected wiring passes through the route position obtained in the route position acquisition step. This avoids unnecessary expansion of the design freedom of the corrected wiring. Consequently, the automatic generation of corrected wiring can be made more efficient.

[0031] According to the ninth embodiment, the design wiring data acquisition step of the wiring data generation method acquires the design wiring data generated by the design wiring generation step of the wiring data generation method. Therefore, the design wiring data can be prepared in the wiring data generation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a side view schematically showing the configuration of the drawing system.

[0033] Figure 2 This is a plan view schematically showing the configuration of the drawing system.

[0034] Figure 3 This is a block diagram schematically showing the configuration of a control unit of a rendering device included in a rendering system.

[0035] Figure 4 This is a partial plan view schematically showing a first step of an example of forming a rewiring layer when the arrangement positions of electrical components are accurate.

[0036] Figure 5 This is a partial plan view schematically showing a second step of an example of forming a rewiring layer when the arrangement positions of electrical components are accurate.

[0037] Figure 6 This is a partial plan view schematically showing a third step of an example of forming a rewiring layer when the arrangement positions of electrical components are accurate.

[0038] Figure 7 for Figure 6 A partial enlarged view of .

[0039] Figure 8 This is a partial plan view schematically showing a fourth step of an example of forming a rewiring layer when the arrangement positions of electrical components are accurate.

[0040] Figure 9 This is a partial plan view schematically showing a fourth step of an example of forming a rewiring layer when the arrangement positions of electrical components are accurate.

[0041] Figure 10 This is a partial plan view schematically showing a first step of forming an example of a rewiring layer having a defect due to an error in the arrangement of electrical components.

[0042] Figure 11 This is a partial plan view schematically showing a second step of forming an example of a rewiring layer having a defect due to an error in the arrangement of electrical components.

[0043] Figure 12 This is a partial plan view schematically showing a third step of forming an example of a rewiring layer having a defect due to an error in the arrangement of electrical components.

[0044] Figure 13 This is a block diagram schematically showing the configuration of a drawing system in an embodiment.

[0045] Figure 14 It is a partial top view showing the contents of design data in the embodiment.

[0046] Figure 15 It is a partial top view showing the contents of local wiring data in the embodiment.

[0047] Figure 16 It is a partial top view showing the content of actual position data in the embodiment.

[0048] Figure 17 It is a partial top view showing the contents of the corrected wiring data in the embodiment.

[0049] Figure 18 This is a flowchart schematically showing a wiring data generation method in the embodiment.

[0050] Figure 19It is a partial top view showing the contents of design data in a modified example.

[0051] Figure 20 It is a partial plan view showing the contents of local wiring data in a modified example.

[0052] Figure 21 It is a partial top view showing the content of the actual position data in a modification example.

[0053] Figure 22 It is a partial plan view showing the contents of the corrected wiring data in a modified example. DETAILED DESCRIPTION

[0054] Hereinafter, the embodiment will be described based on the drawings. In addition, the same or corresponding parts in the drawings are denoted by the same reference numerals and the description thereof will not be repeated.

[0055] [1. Preliminary Notes]

[0056] Before describing the specifics of the embodiment, a preliminary explanation for easy understanding will be given below.

[0057] [1-1. Description system structure]

[0058] Figure 1 as well as Figure 2 The figures are a side view and a top view respectively showing an example of the configuration of the drawing system 1. The drawing system 1 includes a basic CAD system 150 and a drawing device 100 having a control unit 70. The basic CAD system 150 is connected to the control unit 70 of the drawing device 100 via a communication line, and various data can be sent and received between the basic CAD system 150 and the control unit 70. The basic CAD system 150 ( Figure 3 ) can also be configured using a general system for wiring pattern design. The following describes the configuration of the drawing device 100.

[0059] The drawing device 100 is a direct drawing device that irradiates a light beam toward a photosensitive resist layer provided on the substrate W for photolithography on the substrate W, thereby drawing a pattern. In addition, other structures may be sandwiched between the substrate W and the resist layer. The substrate W is used to support the semiconductor chip during the step of forming a rewiring layer on the semiconductor chip (electrical component). Therefore, the substrate W may also be removed before the final product (typically a multi-chip module) containing the semiconductor chip and the rewiring layer is completed. The substrate W is, for example, a semiconductor substrate or a glass substrate. The drawing device 100 mainly includes: a stage 10 for holding the substrate W; a stage moving mechanism 20 for moving the stage 10; a position parameter measuring mechanism 30 for measuring position parameters corresponding to the position of the stage 10; an optical head 50 for irradiating pulse light toward the upper surface of the substrate W; an alignment camera 60 (shooting unit); and a control unit 70.

[0060] In addition, the drawing device 100 has a main body frame 101 and a shell 102 installed on the main body frame 101. The main body of the drawing device 100 is composed of the main body frame 101, the shell 102, and the components surrounded by the main body frame 101 and the shell 102. A substrate storage box 110 is arranged on the outside of the main body. Unprocessed substrates W that should be subjected to exposure processing can be stored in the substrate storage box 110. The unprocessed substrates W are loaded into the main body by a transport robot 120 arranged inside the main body. In addition, after the unprocessed substrates W are subjected to exposure processing (pattern drawing processing), the substrates W are unloaded from the main body by the transport robot 120 and returned to the substrate storage box 110.

[0061] The base 130 is arranged in a range in the main body that the transfer robot 120 can access. Figure 1 as well as Figure 2 The right-hand side area of ​​the base 130 is a substrate receiving and transferring area for receiving and transferring the substrate W between the one end side area of ​​the base 130 and the transfer robot 120. The other end side area of ​​the base 130 ( Figure 1 as well as Figure 2 The left-hand side area of ​​the base 130 is a pattern drawing area for drawing a pattern on the substrate W. A head support portion 140 is provided on the base 130. The head support portion 140 includes two leg members 141 and two leg members 142, which are arranged upright upward from the pattern drawing area of ​​the base 130. The head support portion 140 includes a beam member 143 bridging between the tops of the two leg members 141 and a beam member 144 bridging between the tops of the two leg members 142. In addition, an alignment camera 60 is fixed to the pattern drawing area side of the beam member 143. The alignment camera 60 images the upper surface side of the substrate W.

[0062] The stage 10 has a cylindrical shape in the XY plane. A plurality of suction holes (not shown) are formed on the upper surface of the stage 10. Therefore, when the substrate W is placed on the upper surface of the stage 10 in a horizontal position, the substrate W is adsorbed and fixed to the upper surface of the stage 10 by the suction pressure of the plurality of suction holes. Therefore, the substrate W is held on the stage 10. The stage 10 is moved in the X direction, the Y direction, and the θ direction on the base 130 by the stage moving mechanism 20. The θ direction is the direction of rotation around the Z axis. The stage moving mechanism 20 causes the stage 10 to move two-dimensionally in parallel in the XY plane (horizontal plane) and rotate in the θ direction. Therefore, the stage 10 moves relative to the optical head 50. The stage moving mechanism 20 positions the stage 10 relative to the optical head 50 described later through this relative movement.

[0063] The stage moving mechanism 20 moves the stage 10 in the main scanning direction (Y-axis), the sub-scanning direction (X-axis), and the rotational direction (rotational direction about the Z-axis) relative to the base 130 of the drawing apparatus 100. The stage moving mechanism 20 includes a rotation mechanism 21 for rotating the stage 10; a support plate 22 for rotatably supporting the stage 10; a sub-scanning mechanism 23 for moving the support plate 22 in the sub-scanning direction; a base plate 24 for supporting the support plate 22 via the sub-scanning mechanism 23; and a main scanning mechanism 25 for moving the base plate 24 in the main scanning direction. The rotation mechanism 21 includes a motor composed of a rotor mounted inside the stage 10. Furthermore, a rotary bearing mechanism is provided between the lower surface of the center portion of the stage 10 and the support plate 22. When the motor is operated, the rotor moves in the θ direction. Consequently, the stage 10 rotates within a predetermined angular range about the rotation axis of the rotary bearing mechanism. The sub-scanning mechanism 23 includes a linear motor 23a and a pair of guide rails 23b. The linear motor 23a generates propulsion in the secondary scanning direction through a movable member mounted on the lower surface of the support plate 22 and a fixed member mounted on the upper surface of the base plate 24. A pair of guide rails 23b guide the support plate 22 in the secondary scanning direction relative to the base plate 24. With this configuration, when the linear motor 23a operates, the support plate 22 and the stage 10 move in the secondary scanning direction along the guide rails 23b on the base plate 24. The main scanning mechanism 25 includes a linear motor 25a and a pair of guide rails 25b. The linear motor 25a generates propulsion in the primary scanning direction through a movable member mounted on the lower surface of the base plate 24 and a fixed member mounted on the upper surface of the head support 140. The pair of guide rails 25b guide the base plate 24 in the primary scanning direction relative to the head support 140. With this configuration, when the linear motor 25a operates, the base plate 24, the support plate 22, and the stage 10 move in the primary scanning direction along the guide rails 25b on the base 130. In addition, as such a stage moving mechanism 20 , a conventionally commonly used XY-θ axis moving mechanism can be used.

[0064] The position parameter measuring mechanism 30 uses the interference of laser to measure the position parameters of the stage 10. The position parameter measuring mechanism 30 mainly includes a laser emitting section 31, a spectroscope 32, a beam bending mirror 33, a first interferometer 34 and a second interferometer 35. The laser emitting section 31 is a light source device for emitting laser light for measurement (refer to the dotted line in the figure). The laser emitting section 31 is set at a fixed position (a position fixed relative to the base 130). The laser light emitted from the laser emitting section 31 first enters the spectroscope 32, and is thereby branched into a first branched light from the spectroscope 32 toward the beam bending mirror 33 and a second branched light from the spectroscope 32 toward the second interferometer 35. The first branched light is reflected by the beam bending mirror 33 and enters the first interferometer 34, and is irradiated from the first interferometer 34 to the first part (here, the center part of the end side on the -Y side) 10a of the end side on the -Y side of the stage 10. Next, the first branched light reflected in the first portion 10a is incident again on the first interferometer 34. The first interferometer 34 measures a position parameter corresponding to the position of the first portion 10a of the stage 10 based on the interference between the first branched light directed toward the stage 10 and the first branched light reflected from the stage 10. On the other hand, the second branched light is incident on the second interferometer 35 and irradiated from the second interferometer 35 to the second portion 10b (a portion different from the first portion 10a) on the -Y side of the end edge of the stage 10. Next, the second branched light reflected in the second portion 10b is incident again on the second interferometer 35. The second interferometer 35 measures a position parameter corresponding to the position of the second portion 10b of the stage 10 based on the interference between the second branched light directed toward the stage 10 and the second branched light reflected from the stage 10. The first interferometer 34 and the second interferometer 35 transmit the position parameters obtained by their respective measurements to the control unit 70. The control unit 70 uses these position parameters to control the position and movement speed of the stage 10, etc.

[0065] The optical head 50 is fixed relative to the alignment camera 60 in the XY plane. Furthermore, the optical head 50 is mounted so as to be freely movable in the Z direction (vertical direction) relative to the head support 140 via a head movement mechanism (not shown). Vertical movement of the optical head 50 allows for highly precise adjustment of the distance between the optical head 50 and the substrate W on the stage 10. A box 172 housing the optical system of the optical head 50 and other components is installed to bridge the tops of the beam members 143 and 144. The box 172 covers the pattern drawing area of ​​the base 130 from above.

[0066] In order to pattern the photosensitive resist layer on the substrate W, the optical head 50 irradiates the upper surface of the substrate W held on the stage 10 with pulsed light for exposure processing. Therefore, the optical head 50 can expose the substrate W without using an exposure mask. In more detail, the optical head 50 directly exposes the photosensitive resist layer on the substrate W placed on the stage 10 based on the drawing data generated by the wiring data generating device 80. The optical head 50 is mounted on the beam member 143, and the beam member 143 is mounted above the base 130 in a manner spanning the stage 10 and the stage moving mechanism 20. The optical head 50 is arranged in the approximately central part of the base 130 in the Y direction. The optical head 50 is connected to a laser oscillator 54 via an illumination optical system 53. A laser driving unit 55 is connected to the laser oscillator 54, and the laser driving unit 55 is used to drive the laser oscillator 54. The laser oscillator 54 emits light of a wavelength contained in the wavelength band to which the photosensitive resist layer is sensitive. Typically, the photoresist layer is sensitive to ultraviolet light. In this case, the laser oscillator 54 is, for example, a tripled-wave solid-state laser that emits ultraviolet light with a wavelength of 355 nm. The laser driver 55, the laser oscillator 54, and the illumination optical system 53 are located within the housing 172. When the laser driver 55 is in operation, pulsed light is emitted from the laser oscillator 54, which is then guided into the interior of the optical head 50 via the illumination optical system 53.

[0067] The following components (none of which are shown in the figure) are mainly provided inside the optical head 50: a spatial light modulator for spatially modulating the irradiated light; a drawing control unit for controlling the spatial light modulator; and an optical system for irradiating the pulsed light introduced into the optical head 50 toward the upper surface of the substrate W via the spatial light modulator. As the spatial light modulator, for example, a GLV (Grating Light Valve) (registered trademark) which is a diffraction grating type spatial light modulator is used. The pulsed light introduced into the optical head 50 is irradiated toward the upper surface of the substrate W as a light beam formed into a predetermined pattern shape through the spatial light modulator. As a result, the photosensitive resist layer on the substrate W is exposed. Therefore, a pattern is drawn on the upper surface of the substrate W. The optical head 50 moves the substrate W in the sub-scanning direction by one exposure width at a time, and repeatedly draws the pattern a predetermined number of times in the main scanning direction, thereby forming a pattern on the entire drawing area of ​​the substrate W.

[0068] The alignment camera 60 captures the substrate W, generating a monitoring image. The monitoring image includes images of alignment marks (not shown) pre-formed at multiple locations on the upper surface of the substrate W, as well as alignment marks formed on the upper surface of a semiconductor chip already positioned on the substrate W. The monitoring image is used to detect the position and angle of the substrate W and the position and angle of the semiconductor chip. The alignment camera 60 can also capture wiring patterns such as electrodes covered by a photoresist layer. The alignment camera 60 is comprised of, for example, a digital camera and is secured to the base 130 via a beam member 143.

[0069] In order to make the alignment camera 60 photograph the alignment mark, first, the stage 10 moves to the position on the most -Y side ( Figure 1 as well as Figure 2 The monitoring illumination unit (not shown) then irradiates monitoring light toward the substrate W, while the alignment camera 60 acquires a monitoring image including images of each alignment mark. The acquired monitoring image is transmitted from the alignment camera 60 to the control unit 70. The transmitted monitoring image is used by the control unit 70 to adjust the position and angle of the substrate W relative to the optical head 50 and detect placement errors of semiconductor chips relative to predetermined reference positions and angles.

[0070] When the electrodes of the semiconductor chip arranged on the substrate W are irradiated with monitoring illumination light, the infrared component in the reflected light of the monitoring illumination light is incident on the alignment camera 60. Since the infrared component hardly helps to pass through the photosensitive resist layer, the alignment camera 60 having sensitivity in the infrared region can photograph the electrodes covered by the photosensitive resist layer. Therefore, it is preferable that the monitoring illumination light contains a large amount of infrared component. Therefore, the configuration of the electrodes of the semiconductor chip can be directly measured. In addition, instead of such direct measurement, the configuration of the semiconductor chip can be measured by detecting the alignment mark, and the configuration of the electrodes in the semiconductor chip can be indirectly measured by referring to the design data of the configuration of the electrodes.

[0071] The control unit 70 is an information processing unit that controls the operation of various components within the drawing apparatus 100 while performing various computations. The control unit 70 includes a wiring data generator 800 and an exposure control unit 980. The wiring data generator 800 generates wiring data representing the wiring provided in the secondary wiring layer of the semiconductor chip. The exposure control unit 980 uses this wiring data to control the panel moving mechanism 20, the optical head 50, and other components, thereby performing direct exposure processing.

[0072] Reference Figure 3The control unit 70 can also be composed of one or more general computers with circuits. When using multiple computers, these computers are connected so that they can communicate with each other. The control unit 70 can also be configured in an electrical equipment rack (not shown). Specifically, the control unit 70 includes a CPU (Central Processing Unit) 71, a ROM (Read Only Memory) 72, a RAM (Random Access Memory) 73, a storage device 74, an input unit 76, a display unit 77, a communication unit 78, and a bus line 75 for connecting these components to each other. The ROM 72 stores basic programs. The RAM 73 is used as an operating area when the CPU 71 performs predetermined processing. The storage device 74 is composed of a non-volatile storage device such as a flash memory or a hard disk device. The input unit 76 is composed of various switches or a touch panel, etc., and receives input setting instructions such as processing recipes from the operator. The display unit 77 is composed of, for example, a liquid crystal display device and a lamp, and displays various information under the control of the CPU 71. The communication unit 78 has a data communication function via a LAN (Local Area Network) or the like. Multiple control modes for the various components of the rendering apparatus 100 are pre-set in the storage device 74. The CPU 71 executes a processing program 74P, thereby selecting one of these multiple modes and controlling the various components in that mode. Alternatively, the processing program 74P may be stored on a recording medium. Using this recording medium, the processing program 74P can be installed in the control unit 70. Furthermore, some or all of the functions performed by the control unit 70 do not necessarily need to be implemented using software; they may also be implemented using hardware such as dedicated logic circuits.

[0073] [1-2. Example of Forming a Rewiring Layer When the Chip Arrangement Position is Accurate]

[0074] Reference Figure 4 , the semiconductor chip 310 (electrical component) is arranged at a predetermined position on the substrate W by a bonding machine. In this example, it is assumed that the arrangement is error-free. In addition, although only one semiconductor chip 310 is shown in the figure, in mass production, a plurality of semiconductor chips 310 are usually arranged at different positions in the in-plane direction on the substrate W. The semiconductor chip 310 is arranged on the surface ( Figure 4 The substrate W on which the semiconductor chip 310 is mounted has an electrode 311 (element electrode 311) on the surface shown. In the example shown, the electrode 311 has a circular shape and a diameter of, for example, approximately 25 μm. Next, a secondary wiring layer is formed on the substrate W on which the semiconductor chip 310 is mounted through the following steps.

[0075] Reference Figure 5An interlayer insulating film 402 and a through-hole 401 penetrating the interlayer insulating film 402 are formed as the lower layer of the rewiring layer. Through-hole 401 is made of metal and is located above electrode 311. In the example shown, through-hole 401 has a square shape, with a side of approximately 45 μm. To impart the pattern shape shown in the figure to through-hole 401, photolithography using an exposure process using a drawing system 1 is performed.

[0076] Reference Figure 6 , a metal layer 410 having wiring 411 and solder pad 412 is formed as a middle layer of the re-wiring layer. The wiring 411 has one end in contact with the through-hole 401 and the other end in contact with the solder pad 412. The width dimension of the wiring 411 (the dimension in the direction perpendicular to the extension direction) is, for example, greater than about 15 μm and less than about 20 μm. In order to impart the pattern shape as shown in the figure to the metal layer 410, photolithography using an exposure process of the drawing system 1 is performed. When viewed from above, the solder pad 412 is configured in a manner that at least partially overlaps with the semiconductor chip 310. Specifically, when viewed from above, at least one of the multiple solder pads 412 is configured in a manner that overlaps with the semiconductor chip 310. Figure 7 for Figure 6 In this example, since the semiconductor chip 310 ( Figure 6 ) is precisely arranged, so the electrode 311 of the semiconductor chip 310 is located at the designed position 311pd. Furthermore, the through hole 401 and the wiring 411 are formed correspondingly. The designed position 311pd is a representative position of the electrode 311 in design, and may be, for example, the center position of the electrode 311 in design.

[0077] Reference Figure 8 A cover insulating film 420 is formed as the upper layer of the rewiring layer. Cover insulating film 420 has openings 420n, which partially expose pads 412. Thus, a rewiring layer is obtained that includes through-holes 401, interlayer insulating film 402, metal layer 410, and cover insulating film 420. In other words, the formation of the rewiring layer is completed through the steps thus far.

[0078] Next, an example of the use of the rewiring layer formed in the above manner will be described below. First, a solder ball (not shown) is mounted on the pad 412 in the opening 420n. Figure 9, the component 320 is mounted on the rewiring layer via the above-mentioned solder balls. Therefore, the solder balls and the electrode 321 of the component 320 are connected (the connection target electrode 321). In other words, the electrode 321 and the pad 412 are connected to each other via the solder balls. In this connection, when viewed from above, each electrode 321 is configured in a manner that at least partially overlaps with the pad 412 corresponding to each electrode 321. Here, for example, the component 320 is a semiconductor chip, and the electrode 321 is a pad electrode of the semiconductor chip. When viewed from above, the electrode 321 (with respect to the electrode 311 ( Figure 5 ) is configured to partially overlap with the semiconductor chip 310. Specifically, when viewed from above, at least one electrode 321 among the plurality of electrodes 321 is configured to overlap with the semiconductor chip 310. Figure 9 In the example shown, all the electrodes 321 are arranged so as to overlap with the semiconductor chip 310 when viewed from above. However, as a modification, only a portion of the electrodes 321 may be arranged so as to overlap with the semiconductor chip 310 .

[0079] In this manner, a laminated body is obtained in which the semiconductor chip 310 and the component 320 are stacked on the substrate W via the rewiring layer. The semiconductor chip 310 and the component 320 are stacked so that they at least partially overlap in a planar layout. The electrodes 311 of the semiconductor chip 310 and the electrodes 321 of the component 320 are electrically connected to each other via the rewiring layer. The substrate W can then be removed. As long as multiple laminated bodies are formed on the substrate W, multiple laminated bodies can be obtained at once.

[0080] [1-3. Example of Formation of a Defective Rewiring Layer Due to Chip Arrangement Error]

[0081] Next, a case will be described where, in a situation where the semiconductor chip 310 has a non-negligible placement error, the placement error is not corrected, and a rewiring layer is formed using the same method as described above. This example is a comparative example with respect to the embodiment described below.

[0082] Reference Figure 10, the semiconductor chip 310 (first electrical component) is arranged at a predetermined position 310d on the substrate W by a bonding machine. Here, it is set so that there is an error in this arrangement. As a result, the position of the semiconductor chip 310 has an error relative to the predetermined position 310d. Correspondingly, the actual position 311pr of the electrode 311 of the semiconductor chip 310 has an error relative to the designed position 311pd. The main causes of the error of the actual position 311pr relative to the designed position 311pd may be the mounting error when the semiconductor chip 310 is mounted on the substrate W and the thermal expansion and contraction of the substrate W on which the semiconductor chip 310 is mounted. In addition, although only one semiconductor chip 310 is shown in the figure, a plurality of semiconductor chips 310 are arranged at different positions in the in-plane direction on the substrate W in mass production. Next, a rewiring layer is formed on the substrate W on which the semiconductor chip 310 is arranged through the following steps.

[0083] Reference Figure 11 An interlayer insulating film 402 and a through-hole 401 penetrating the interlayer insulating film 402 are formed as the lower portion of the rewiring layer. To impart the pattern shape shown in the figure to through-hole 401, photolithography using a drawing system 1 is performed using an exposure process. The exposure process is performed regardless of the placement errors of electrodes 311 on semiconductor chip 310. Due to these errors, through-hole 401 is offset from electrode 311, resulting in a lack of electrical connection between the two.

[0084] Reference Figure 12 , forming a metal layer 410 having wiring 411 and pads 412 as the middle layer of the rewiring layer. In order to impart the pattern shape shown in the figure to the metal layer 410, photolithography using an exposure process of the drawing system 1 is performed. Here, compared with the configuration error of the semiconductor chip 310, the superposition error of the photolithography is very small. Therefore, the metal layer 410 is very accurately configured relative to the through hole 401. Here, as described above, the actual position 311pr of the electrode 311 has an error relative to the designed position 311pd, resulting in the through hole 401 not being connected to the electrode 311. Therefore, the electrode 311 and the metal layer 410 are not electrically connected. Therefore, in this example, the rewiring layer has a defect.

[0085] [2. Detailed Description of Embodiments]

[0086] In order to avoid the above-mentioned defect of the rewiring layer, the drawing system 1 in this embodiment has the following features in addition to the configuration described in the above preliminary description.

[0087] [2-1. Structure]

[0088] Figure 13This is a block diagram schematically illustrating the functional configuration of the drawing system 1. As described in the above preliminary explanation, the drawing system 1 includes a basic CAD system 150 and a drawing device 100. Furthermore, the drawing device 100 includes a control unit 70 and a functional component group 5. The control unit 70 includes a wiring data generation device 800 and an exposure control unit 980. The exposure control unit 980 controls the functional component group 5. As described above, the functional component group 5 includes the stage moving mechanism 20, the optical head 50, and the alignment camera 60.

[0089] The wiring data generating device 800 generates data indicating a rewiring layer. Figure 4 ) and a member 320 ( Figure 9 ) are electrically connected to each other, and the secondary wiring layer is sandwiched between the semiconductor chip 310 and the member 320 in the stacking direction. As part of the above data generation, the wiring data generation device 800 generates a data indicating the wiring 411 ( Figure 7 To achieve the above description, the wiring data generating device 800 includes a design wiring data acquiring unit 820, a local wiring data generating unit 830, an actual position data acquiring unit 860, and a correction wiring data generating unit 880.

[0090] In order to form a rewiring layer, the wiring data acquisition unit 820 ( Figure 13 ) obtains design data that does not take into account the arrangement error of the semiconductor chip 310 on the substrate W. Specifically, Figure 14 As shown, the design wiring data acquisition unit 820 acquires the design wiring data 501, which shows the design through hole 401D, the design wiring 411D and the design pad 412D. The design through hole 401D, the design wiring 411D and the design pad 412D are used to connect the electrode 321 ( Figure 9) and the electrode 311 located at the design position 311pd on the substrate W (depicted with a dotted line for reference) are connected to each other. The design wiring data 501 can also be obtained from the basic CAD system 150, and in this case, the design wiring generation unit 810 can also be omitted. Alternatively, the design wiring data 501 generated by the design wiring generation unit 810 can also be obtained. In this case, the design wiring generation unit 810 generates the design wiring data 501 based on the design position 311pd of the electrode 311 of the semiconductor chip 310 and the assumed position for the configuration of the electrode 321 of the component 320. For this purpose, the design wiring generation unit 810 obtains information on the design position 311pd of the electrode 311 of the semiconductor chip 310, the assumed position for the configuration of the electrode 321 of the component 320, and the design position of the electrode 321 in the component 320 from the basic CAD system 150 or the control unit 70. Then, based on this information, the design wiring data 501 is generated using a general automatic wiring technology.

[0091] like Figure 15 As shown, the local wiring data generating unit 830 ( Figure 13 ) generates local wiring data 502 showing the local wiring 411R, which is obtained by deleting the design wiring 411D ( Figure 14 ) is obtained by the peripheral portion of the designed position 311pd of the electrode 311 in the local wiring 411R. The local wiring 411R has a connected position 311qd at the boundary between the local wiring 411R and the peripheral portion removed in the above description. Here, the "peripheral portion" is, for example, a portion included in the distance determined by a predetermined rule from the designed position 311pd. This distance can also be calculated from the designed dimension D of the electrode 311. For example, when the electrode 311 has a circular shape, the dimension D is the diameter of the electrode 311; when the electrode 311 has a square shape, the dimension D is the length of one side of the electrode 311; when the electrode 311 has a rectangular shape that is not a square shape, the dimension D is the length of the short side or the long side of the electrode 311. The above distance is preferably greater than D / 4, and more preferably greater than D / 2. In addition, the above distance is preferably less than 5D, and more preferably less than 3D. Alternatively, the control unit 70 can also receive information about the above distance from the outside. When it is assumed that the size of the arrangement deviation of the electrode 311 is approximately the dimension E, the above distance can also be calculated from the dimension E. Specifically, the distance can be calculated by multiplying the dimension E by a constant (for example, approximately 1.5).

[0092] like Figure 16 As shown, the actual position data acquisition unit 860 ( Figure 13 ) obtains actual position data 503, which indicates that the actual position data 503 is held on the table 10 ( Figure 1) on the substrate W. Specifically, the actual position data acquisition unit 860 calculates the actual position 311pr of the electrode 311 of the semiconductor chip 310 from a monitoring image obtained by imaging the semiconductor chip 310 with the alignment camera 60. This calculation can be based on the measurement results of the alignment mark of the semiconductor chip 310 or the measurement results of the electrode 311 itself. Furthermore, the position in the monitoring image can be detected based on an edge signal obtained by, for example, performing a second derivative of a pixel value distribution.

[0093] exist Figure 16 In FIG. 4 , the dotted line between the actual position 311pr of the electrode 311 and the connected position 311qd of the local wiring 411R connected to the designed pad 412D shows the connection relationship specified by the network connection table. The network connection table is a table predetermined as a type of design information. The network connection table can be obtained from the basic CAD system 150 ( Figure 13 ) or may be received from the outside by the control unit 70.

[0094] like Figure 17 As shown, the correction wiring data generating unit 880 ( Figure 13 ) will design through hole 401D ( Figure 14 ) from the design position 311pd( Figure 14 ) moves to the actual position 311pr( Figure 17 ), thereby generating the correction wiring data 504 ( Figure 17 ). In addition, if Figure 17 As shown, the correction wiring data generating unit 880 ( Figure 13 ) generates correction wiring data 504 showing the correction wiring 411C, which is a wiring for connecting the local wiring 411R and the electrode 311 (drawn with a dotted line for reference) at the actual position 311pr to each other through the correction through hole 401C. For example, based on the network connection table (refer to Figure 16 The actual position 311pr and the connected position 311qd to be electrically connected are selected using the dashed line in the figure (see FIG. 1 ), and data for the correction wiring 411C is generated to linearly connect the actual position 311pr and the connected position 311qd. By setting the generated pattern shape to a linear shape, the computational burden required for data generation can be reduced.

[0095] The drawing data generating unit 890 generates drawing data (rasterized wiring data) by performing RIP on the corrected wiring data 504. The drawing data generating unit 890 also sends the drawing data to the exposure control unit 980 ( Figure 13The exposure control unit 980 controls the functional component group 5 based on the drawing data. Therefore, the optical head 50 performs direct exposure of the substrate W based on the drawing data.

[0096] [2-2. Wiring data generation method]

[0097] With the above configuration, a wiring data generating method including the following steps can be implemented.

[0098] In the design wiring generation step ST10 ( Figure 18 ), by designing the wiring generation unit 810 ( Figure 13 ) Generate design wiring data 501( Figure 14 In the design wiring data acquisition step ST20 ( Figure 18 ), the design wiring data acquisition unit 820 ( Figure 13 ) obtains the design wiring data 501 generated in the above manner ( Figure 14 ). In addition, as a modified example, the design wiring data 501 can also be obtained from the basic CAD system 150. In this case, the design wiring generation step ST10 ( Figure 18 ). In the local wiring data generation step ST30 ( Figure 18 ), by the local wiring data generation unit ( Figure 13 ) Generate local wiring data 502 ( Figure 15 ). In the actual position data acquisition step ST40 ( Figure 18 ), through the actual position data acquisition unit 860 ( Figure 13 ) Get the actual position 311pr ( Figure 16 ) actual position data 503. In the correction wiring data generation step ST50 ( Figure 18 ), by correcting the wiring data generating unit ( Figure 13 ) Generates corrected wiring data 504.

[0099] [2-3. Determination of whether the corrected wiring data can be generated normally]

[0100] Correction wiring data generation unit 880 ( Figure 13 ) may also include: a determination unit 882 that determines whether the corrected wiring data 504 can be normally generated ( Figure 17 ). This determination may also be performed based on the actual position 311pr calculated from the monitoring image obtained by the alignment camera 60. Instead of or in addition to this determination, the determination of the modified example described below may be performed.

[0101] In order to be able to determine the modified example, the wiring data generating device 800 includes an error position generating unit 850. The error position generating unit 850 generates an error position having an error between the electrode 311 and the design position 311pd based on a predetermined rule. The determining unit 882 determines whether the corrected wiring data 504 can be generated normally, assuming that the actual position 311pr is at the error position. Figure 17 ).

[0102] [2-4. Designation of route location]

[0103] In reference Figure 16 as well as Figure 17 The above description details the case of generating data for linear correction wiring 411C based on a network connection table. However, there are also cases where more complex correction wiring is required. In such cases, automatic wiring technology can also be used to generate correction wiring data. On the other hand, when the correction wiring is complex, the computational burden of automatic wiring may become enormous, and it may not be possible to generate an appropriate correction wiring.

[0104] The above problem is alleviated by specifying the passing position of the correction wiring before starting the automatic wiring. When the passing position is required to be specified, the correction wiring data generating unit 880 ( Figure 13 ) includes a route position acquisition unit 881 for acquiring a route position. The route position information may be automatically set by the control unit 70 or may be received from the outside by the control unit 70. The correction wiring data generation unit 880 ( Figure 13 ) is to generate the correction wiring data in such a manner that the correction wiring 411C passes through the via position acquired by the via position acquisition unit 881. In other words, the correction wiring data generation step ST50 ( Figure 18 ) includes a route position acquisition step ST51 for acquiring a route position. A correction wiring data generation step ST50 generates correction wiring data so that the correction wiring 411C passes through the route position acquired in the route position acquisition step ST51. This technique will be specifically described below using a modified example in which the rewiring layer has a more complex structure than described above.

[0105] Reference Figure 19 , by comparing with the design wiring data 501 ( Figure 14 ) is performed in the same manner as in the case of , the design wiring data 501L is obtained.

[0106] Next, refer to Figure 20 , by comparing with the local wiring data 502 ( Figure 15) is generated in the same manner as in the case of . At this time or thereafter, the above-mentioned via position is specified by the position of the intermediate pin 419. The position of the intermediate pin 419 may be automatically set by the control unit 70 when the local wiring data 502L is generated, or the control unit 70 may receive the position from the outside after the local wiring data 502L is generated. In the latter case, for example, the operator operates the input unit 76 ( Figure 3 ) to adjust the display on the display unit 77 ( Figure 3 ) of the middle pin 419.

[0107] Reference Figure 21 , by comparing with the actual position data 503 ( Figure 16 ) is performed in the same manner as in the case of the present invention to obtain the actual position data 503L.

[0108] Next, refer to Figure 22 , by correcting the wiring data 504 ( Figure 17 ) is generated in the same manner as in the case of . The correction wiring 411C in this example includes, for example, correction wirings 411C1 to 411C3. Figure 17 ) Similarly, the correction wiring 411C1 has a linear pattern shape. Figure 17 ) Differently, the correction wiring 411C2 has a curved pattern shape. The correction wiring 411C3 is connected to the intermediate pin 419 ( Figure 21 ) location.

[0109] [2-5. Technical Effect]

[0110] According to this embodiment, the design wiring 411D ( Figure 14 ) corresponding to the portion other than the peripheral portion of the designed position 311pd of the electrode 311 of the semiconductor chip 310 ( Figure 15 ) as a part of the generated wiring data. Therefore, the wiring data can be generated efficiently. Furthermore, since the wiring data generating device 800 generates the wiring data for showing the correction wiring 411C ( Figure 17 ) as another part of the generated wiring data, and the correction wiring 411C is used to connect the local wiring 411R and the electrode 311 located at the actual position 311pr. Therefore, correction can be performed corresponding to the offset between the design position 311pd and the actual position 311pr of the semiconductor chip 310 on the substrate W. As described above, correction can be performed corresponding to the offset of the semiconductor chip 310 from the design position 311pd on the substrate W, and wiring data can be generated efficiently.

[0111] The design wiring data acquisition unit 820 ( Figure 13 ) can also obtain the design wiring data 501 generated by the design wiring generating unit 810 of the wiring data generating device 800 ( Figure 14 In this case, the wiring data generating device 800 ( Figure 13 ) itself prepares the design wiring data 501. In other words, the design wiring data acquisition step ST20 ( Figure 18 ) can also obtain the design wiring data generated in the design wiring generation step ST10 ( Figure 14 ). In this case, the design wiring data 501 can be prepared in the wiring data generating method.

[0112] The modified wiring data generating unit 880 ( Figure 13 ) may also include a determination unit 882 that determines whether the corrected wiring data can be generated normally. In this case, it is possible to avoid using abnormal corrected wiring data during the process. This determination may also be performed based on the actual position 311pr calculated from the monitoring image acquired by the alignment camera 60. Alternatively, or in parallel with the determination based on the actual position 311pr, a determination may be performed assuming that the actual position 311pr is located at the error position generated by the error position generating unit 850. Therefore, the determination can be performed before the actual position 311pr is acquired, allowing for an earlier determination.

[0113] Wiring data generating device 800 ( Figure 13 ) You can also modify the wiring 411C3 ( Figure 22 ) via the via position (intermediate pin 419 ( Figure 21 ) position) to generate the corrected wiring data 504L ( Figure 22 In other words, the wiring data generation step ST50 ( Figure 18 ) You can also modify the wiring 411C3 through the middle pin 419 ( Figure 21 ) position to generate the corrected wiring data 504L ( Figure 22 ). Therefore, unnecessary expansion of the design freedom of the correction wiring 411C3 is avoided. Therefore, the automatic generation of the correction wiring 411C3 can be made more efficient.

[0114] While the present invention has been described in detail, the above description is merely illustrative of all embodiments, and the present invention is not limited to these embodiments. It should be understood that numerous variations not illustrated are conceivable without departing from the scope of the present invention. The various configurations described in the above embodiments and variations may be appropriately combined or omitted as long as they do not conflict with each other.

[0115] Description of Reference Numerals

[0116] 1: Describing the system

[0117] 5: Functional component group

[0118] 10: Taiwan

[0119] 20: Mobile mechanism

[0120] 50: Optical head

[0121] 60: Aim at the camera (photography unit)

[0122] 70: Control Department

[0123] 310: Semiconductor chips (electrical components)

[0124] 311: Electrode (component electrode)

[0125] 311pd: Design Location

[0126] 311pr: Actual location

[0127] 311qd: connected location

[0128] 320: Component

[0129] 321: Electrode (connect to target electrode)

[0130] 401: Through hole

[0131] 401C: Correction of through-holes

[0132] 401D: Design through hole

[0133] 402: Interlayer insulation film

[0134] 410: Metal layer

[0135] 411: Wiring

[0136] 411C: Correction wiring

[0137] 411D: Design Wiring

[0138] 411R: Local wiring

[0139] 412: Solder pad

[0140] 412D: Design solder pad

[0141] 419: Middle pin

[0142] 420: Insulation film coating

[0143] W: substrate

Claims

1. A wiring data generating device for generating wiring data for showing wiring for electrically connecting an element electrode of an electrical element arranged on a substrate and a connection target electrode arranged so as to at least partially overlap the electrical element in a planar layout, wherein: The wiring data generating device comprises: a design wiring data acquisition unit that acquires design wiring data indicating design wiring for connecting the element electrode and the connection target electrode at a design position on the substrate; a local wiring data generating unit that generates local wiring data indicating local wiring obtained by deleting a portion around the designed position of the element electrode in the designed wiring; an actual position data acquisition unit that acquires actual position data indicating an actual position of the element electrode on the substrate; as well as The correction wiring data generating unit generates correction wiring data indicating correction wiring for connecting the local wiring and the element electrode located at the actual position to each other.

2. The wiring data generating device according to claim 1, wherein The correction wiring data generating unit includes a route position acquiring unit for acquiring a route position; The correction wiring data generating unit generates the correction wiring data so that the correction wiring passes through the route position acquired by the route position acquiring unit.

3. The wiring data generating device according to claim 1 or 2, wherein: The device further comprises: a design wiring generating unit configured to generate the design wiring data based on the design position of the element electrode of the electrical element and an assumed position where the connection target electrode is to be arranged; The design wiring data acquisition unit acquires the design wiring data generated by the design wiring generation unit.

4. The wiring data generating device according to claim 1 or 2, wherein: The correction wiring data generating unit includes a determining unit that determines whether the correction wiring data can be normally generated.

5. The wiring data generating device according to claim 4, wherein The device further comprises: an error position generating unit for generating an error position based on a predetermined rule, wherein the error position has an error between the element electrode and the designed position; The determination unit determines whether the corrected wiring data can be normally generated assuming that the actual position is located at the error position.

6. A depiction system, wherein: have: The wiring data generating device according to any one of claims 1 to 5; a stage for holding the substrate; an imaging unit that images the electrical component in order to calculate actual position data indicating the actual position of the component electrode of the electrical component held on the substrate of the stage; as well as The optical head performs direct exposure of the substrate based on the wiring data generated by the wiring data generating device.

7. A wiring data generation method for generating wiring data for showing wiring for electrically connecting a component electrode of an electrical component arranged on a substrate and a connection target electrode arranged so as to at least partially overlap the electrical component in a planar layout, wherein: The wiring data generation method comprises: a design wiring data acquisition step of acquiring design wiring data indicating design wiring for connecting the element electrode and the connection target electrode at the design position on the substrate; a local wiring data generating step of generating local wiring data showing local wiring obtained by deleting a portion around the designed position of the element electrode in the designed wiring; an actual position data obtaining step of obtaining actual position data, wherein the actual position data indicates an actual position of the element electrode on the substrate; as well as The correction wiring data generating step generates correction wiring data indicating correction wiring for connecting the local wiring and the element electrode located at the actual position to each other.

8. The wiring data generating method according to claim 7, wherein: The correction wiring data generating step includes a route position obtaining step for obtaining a route position; The correction wiring data generating step generates the correction wiring data so that the correction wiring passes through the route position acquired in the route position acquiring step.

9. The wiring data generating method according to claim 7 or 8, wherein: The method further comprises: a design wiring generating step of generating the design wiring data based on the design position of the element electrode of the electrical element and an assumed position for arranging the connection target electrode; The design wiring data acquisition step acquires the design wiring data generated in the design wiring generation step.

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