Semiconductor devices

Abstract

This invention prevents the ceramic circuit board from cracking. The ceramic circuit board (30, 40, 50) includes a ceramic substrate (31, 41, 51), high-potential circuit patterns (32a, 42a, 52a) disposed on the front side of the ceramic substrate (31, 41, 51) and mounting semiconductor chips (60a-62a), intermediate-potential circuit patterns (32b, 42b, 52b) mounting semiconductor chips (60b-62b), low-potential circuit patterns (32c, 42c, 52c), and control circuit patterns (32d, 42d, 52d). The ceramic circuit board (30, 40, 50) is disposed across a center line (XL) on the front side of a cooling substrate (70). The control circuit patterns (32d, 42d, 52d) are disposed across the center line (XL) on the opening side of the recessed portion.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Semiconductor devices include power devices and are used as power conversion devices. Examples of power devices include IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Furthermore, the semiconductor device includes a semiconductor chip containing the power device and multiple ceramic circuit boards, each on which the semiconductor chip is disposed. The multiple ceramic circuit boards are disposed on a cooling substrate. Heat from the semiconductor chip is conducted through the ceramic circuit boards and dissipated from the cooling substrate. Thus, the semiconductor chip is cooled. Additionally, the four corners of the cooling substrate of the semiconductor device are fastened to predetermined mounting areas by screws.

[0003] Existing technical documents

[0004] Patent Document 1: International Publication No. 2020 / 059285 Summary of the Invention

[0005] Technical issues

[0006] However, due to the heat generated by the semiconductor chip, warping occurs in both the ceramic circuit board and the cooling substrate, corresponding to the difference in their coefficients of linear expansion. In particular, because the cooling substrate is fixed to a predetermined mounting area, stress concentrates on the warped portion of the cooling substrate. The ceramic circuit board on the cooling substrate cannot follow the warping of the cooling substrate and is thus subjected to this stress, leading to cracking. If the ceramic circuit board suffers such damage, the reliability of the semiconductor device decreases.

[0007] The present invention was made in view of the following problem, and its object is to provide a semiconductor device that prevents damage to the ceramic circuit board.

[0008] Technical solution

[0009] According to one aspect of the present invention, a semiconductor device is provided, comprising: a first semiconductor chip, a second semiconductor chip; a cooling substrate, which is rectangular in shape when viewed from above, having a first side surface, a second side surface, a third side surface, and a fourth side surface arranged sequentially, and having a center line parallel to the first side surface and the third side surface and passing through its center; and an insulating circuit substrate, comprising an insulating plate, a high-potential circuit pattern disposed on the front side of the insulating plate and mounting the first semiconductor chip, an intermediate-potential circuit pattern mounting the second semiconductor chip, a low-potential circuit pattern mounting the second semiconductor chip, and a control circuit pattern, wherein the insulating circuit substrate is disposed across the center line on the front side of the cooling substrate, and the high-potential circuit pattern is... The first side of the center line has a first chip mounting area on which the first semiconductor chip is mounted. The intermediate potential circuit pattern is in the shape of a concave opening on the fourth side and has a recess surrounding at least a portion of the first chip mounting area, a second chip mounting area on which the second semiconductor chip is mounted and disposed on the third side of the center line, an output wiring connection area opposite to the second chip mounting area across the recess, and a connecting wiring area that connects the second chip mounting area and the output wiring connection area and is disposed across the center line. The control circuit pattern is disposed across the center line on the opening side of the recess.

[0010] Invention Effects

[0011] According to the disclosed technology, damage to the ceramic circuit board is prevented, and the reliability of the semiconductor device is prevented from decreasing.

[0012] The above and other objects, features and advantages of the present invention will become clear from the following description in conjunction with the accompanying drawings, which illustrate preferred embodiments as examples of the present invention. Attached Figure Description

[0013] Figure 1 This is a top view of the semiconductor device according to the embodiment.

[0014] Figure 2 This is a top view of the interior of the semiconductor device in the embodiment.

[0015] Figure 3 This is a side cross-sectional view of the semiconductor device according to the embodiment.

[0016] Figure 4 This is a top view of the cooling substrate included in the semiconductor device of the embodiment.

[0017] Figure 5 It is a top view (1) of the circuit pattern of the ceramic circuit board included in the semiconductor device of the embodiment.

[0018] Figure 6 This is a top view (2) showing the circuit pattern of the ceramic circuit board included in the semiconductor device of the embodiment.

[0019] Figure 7 This is a diagram illustrating the wiring layout included in a semiconductor device according to an embodiment.

[0020] Figure 8 This is a circuit diagram showing the equivalent circuit of the semiconductor device according to the embodiment.

[0021] Symbol Explanation

[0022] 10: Semiconductor devices

[0023] 20: Shell

[0024] 21: Side wall portion

[0025] 21a~21d: First wall~Fourth wall

[0026] 22a1: Gx terminal

[0027] 22a2: Gu terminal

[0028] 22a3: Gy terminal

[0029] 22a4: Gv terminal

[0030] 22a5: Gz terminal

[0031] 22a6: GW terminal

[0032] 22b1: U-terminal

[0033] 22b2: V terminal

[0034] 22b3: W terminal

[0035] 22c1: Second P terminal

[0036] 22c2: Second N-terminal

[0037] 22d1: First P terminal

[0038] 22d2: First N-terminal

[0039] 23: cover

[0040] 24a~24d: Fastening holes

[0041] 25: Storage Department

[0042] 26: Frame

[0043] 27b, 27d: Protrusions

[0044] 30, 40, 50: Ceramic circuit board

[0045] 30a~30d, 50a~50d: First side~Fourth side

[0046] 31, 41, 51: Ceramic substrate

[0047] 32, 42, 52: Circuit patterns

[0048] 32a, 42a, 52a: High-potential circuit patterns

[0049] 32a1, 52a1: First incision area

[0050] 32a2, 32a3, 52a2, 52a3: Wiring connection areas

[0051] 32a4, 32b4, 52a4, 52b4: Chip mounting areas

[0052] 32a5, 32a6, 52a6, 52b8: Incision area

[0053] 32a7, 32b7, 32c7, 52a7, 52b7, 52c7: End caps

[0054] 32b, 42b, 52b: Intermediate potential circuit pattern

[0055] 32b1, 52b1: Depression

[0056] 32b2, 52b2: Output wiring connection area

[0057] 32b3, 52b3: Connecting cabling areas

[0058] 32b5, 52b5: Second incision area

[0059] 32b6, 52b6: Third incision area

[0060] 32c, 42c, 52c: Low-potential circuit patterns

[0061] 32c1, 52c1, 52c3: Emphasis on the area

[0062] 32C2, 52C2: Conductive area

[0063] 32d, 42d, 52d: Control circuit patterns

[0064] 32d1, 52d1: First longitudinal extension

[0065] 32d2, 52d2: First lateral extension

[0066] 32d3: Second longitudinal extension

[0067] 33, 43, 53: Metal plates

[0068] 60a~62a, 60b~62b: Semiconductor chips

[0069] 60a1, 60b1: Control electrodes

[0070] 60a2, 60b2: Output electrodes

[0071] 70: Cooling substrate

[0072] 70a~70d: First lateral aspect to fourth lateral aspect

[0073] 74a~74d: Through holes

[0074] 80: Wire

[0075] 81a~81e: Main current conductors

[0076] 82a~82d: Control wires

[0077] 85: Packaging components

[0078] 86: Adhesive Detailed Implementation

[0079] The embodiments will now be described with reference to the accompanying drawings. It should be noted that in the following description, "front" and "upper surface" refer to the surfaces in the semiconductor device 10 facing the +Z direction. Similarly, "upper" in the semiconductor device 10 indicates the direction of the +Z direction. "Back" and "lower surface" refer to the surfaces in the semiconductor device 10 facing the -Z direction. Similarly, "lower" in the semiconductor device 10 indicates the direction of the -Z direction. "Side" refers to the surface in the semiconductor device 10 that connects the "front" or "upper surface" to the "back" and "lower surface." For example, "side" refers to the surface in the semiconductor device 10 facing the ±X and ±Y directions. Such directionality is shown in all the drawings. "Front," "upper surface," "upper," "back," "lower surface," "lower," and "side" are merely convenient expressions for determining relative positional relationships and do not limit the technical concept of the invention. For example, "upper" and "lower" do not necessarily mean the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity. Furthermore, in the following description, "main ingredient" means that it contains 80% or more by volume.

[0080] The semiconductor device in the embodiment will now be described. First, using... Figure 1 The appearance of the semiconductor device is described. Figure 1This is a top view of the semiconductor device according to the embodiment. The semiconductor device 10 includes a semiconductor chip (described later), a ceramic circuit substrate (described later), and a housing 20 that houses the semiconductor chip and the ceramic circuit substrate. It should be noted that the semiconductor chip includes diode elements and switching elements. Furthermore, a cooling substrate 70 (see reference...) Figure 3 It protrudes downwards (in the -Z direction) from the back of the housing 20 of the semiconductor device 10. The housing 20 is rectangular in shape when viewed from above. The housing 20 includes a side wall portion 21, a cover portion 23, and four fastening holes 24a to 24d.

[0081] The side wall portion 21 is rectangular (frame-shaped) when viewed from above. The side wall portion 21 has a storage section (described later) in its central part, including a first wall 21a, a second wall 21b, a third wall 21c, and a fourth wall 21d that sequentially surround the storage section. Specifically, the third wall 21c is positioned on the -Y side opposite to the first wall 21a. Furthermore, the fourth wall 21d is positioned on the -X side opposite to the second wall 21b. The first wall 21a and the third wall 21c are the longer sides, while the second wall 21b and the fourth wall 21d are the shorter sides. Furthermore, the side wall portion 21 can have only straight first walls 21a to fourth walls 21d on its four rectangular sides, or it can have curved (surface) sections at the corners.

[0082] Furthermore, the sidewall portion 21 is provided with a plurality of terminals extending upward (in the +Z direction) along the periphery of the front surface of the sidewall portion 21. These terminals include external connection terminals for the main electrode, control, and output of the ceramic circuit board (inverter), as described later. The external connection terminals for the main electrode are a second P terminal 22c1, a second N terminal 22c2, a first P terminal 22d1, and a first N terminal 22d2. The second P terminal 22c1 and the second N terminal 22c2 are formed on the second wall 21b from the first wall 21a toward the third wall 21c. The first P terminal 22d1 and the first N terminal 22d2 are formed on the fourth wall 21d from the first wall 21a toward the third wall 21c.

[0083] The external connection terminals for control are Gx terminal 22a1, Gu terminal 22a2, Gy terminal 22a3, Gv terminal 22a4, Gz terminal 22a5, and Gw terminal 22a6. These external connection terminals for control are formed on the third wall 21c from the fourth wall 21d toward the second wall 21b. The external connection terminals for output are U terminal 22b1, V terminal 22b2, and W terminal 22b3. These external connection terminals for output are formed on the first wall 21a from the fourth wall 21d toward the second wall 21b.

[0084] The cover 23 is provided in such a way that it blocks the opening of the storage section for the components (semiconductor chips, etc.) of the semiconductor device 10 (see reference). Figure 3The fastening holes 24a to 24d are respectively provided at the four corners of the side wall portion 21 when viewed from above. The fastening holes 24a to 24d are for screw mounting. When the semiconductor device 10 is mounted at a predetermined position, screws are installed in the fastening holes 24a to 24d to fasten it to the predetermined position. In addition, the screws pass through the fastening holes 24a to 24d and are also installed in the through holes (described later) of the cooling substrate 70, and the cooling substrate 70 is also fastened in the same way as the housing 20.

[0085] Such a housing 20 includes multiple terminals and is formed integrally using resin. This resin is primarily composed of a thermoplastic resin. Examples of thermoplastic resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin. Furthermore, the cover 23 is also separately formed from the same material.

[0086] The cooling substrate 70 is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these. Furthermore, to improve corrosion resistance, materials such as nickel can be formed on the surface of the cooling substrate 70 through processes such as plating. Specifically, in addition to nickel, nickel-phosphorus alloys, nickel-boron alloys, etc., are also used. This cooling substrate 70 is rectangular in top view and is formed in the order of the first side surface 70a to the fourth side surface 70d (see reference). Figure 4 That is, a third side surface 70c is disposed on the -Y side opposite to the first side surface 70a. Furthermore, a fourth side surface 70d is disposed on the -X side opposite to the second side surface 70b. The first side surface 70a and the third side surface 70c are long sides, while the second side surface 70b and the fourth side surface 70d are short sides. Furthermore, the cooling base substrate 70 only needs to have straight first side surface 70a to fourth side surface 70d on its four rectangular sides, but it may also have curved (curved) portions at the corners. The first side surface 70a to fourth side surface 70d of the cooling base substrate 70 are respectively opposite to the first wall 21a to fourth wall 21d of the housing 20. Furthermore, the cooling base substrate 70 has through holes 74a to 74d formed at its four corners. The positions and inner diameters of the through holes 74a to 74d correspond to the fastening holes 24a to 24d of the housing 20. When the semiconductor device 10 is installed at a predetermined location, the screw is inserted into the fastening holes 24a to 24d of the housing 20, and also into the through holes 74a to 74d.

[0087] It should be noted that a cooler (not shown) can also be mounted on the back side of the cooling substrate 70 to improve heat dissipation. The cooler can be mounted using fastening holes 24a to 24d via threaded fastening, or it can be mounted via solder or silver solder. In this case, the cooler is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of them. Furthermore, as a cooler, a heat sink consisting of multiple heat sinks and a water-based cooling device can be used, for example. In addition, the cooling substrate 70 can also be integrally formed with such a cooler. In this case, it is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of them. Moreover, to improve corrosion resistance, a material such as nickel can be formed on the surface of the cooling substrate 70 integrated with the cooler, for example, through a plating process. Specifically, in addition to nickel, nickel-phosphorus alloys, nickel-boron alloys, etc., are also used.

[0088] Next, using Figures 2-4 The internal structure of the semiconductor device 10 will be described. Figure 2 This is a top view of the interior of the semiconductor device in the embodiment. Figure 3 This is a side cross-sectional view of the semiconductor device according to the embodiment. Furthermore, Figure 4 This is a top view of the cooling substrate included in the semiconductor device of the embodiment. It should be noted that... Figure 3 yes Figure 1 and Figure 2 The cross-sectional view at the dashed line XX in the diagram. Furthermore, in Figure 2 The description of the encapsulation components and the cover is omitted. Figure 4 In this paper, only the cooling substrate 70 on which the ceramic circuit board is disposed is shown in planar view; other structures are omitted. Figure 4 The center line XL shown is a line passing through the center point of the cooled substrate 70 and parallel to the length direction. The center line YL is a line passing through the center point of the cooled substrate 70 and parallel to the short side direction.

[0089] As described above, the semiconductor device 10 includes a housing 20, semiconductor chips 60a-62a, 60b-62b housed in the housing 20, and ceramic circuit boards 30, 40, and 50. It should be noted that, hereinafter, the semiconductor chips 60a-62a and 60b-62b are sometimes simply referred to collectively as semiconductor chips.

[0090] As described above, the sidewall portion 21 of the housing 20 is rectangular in shape when viewed from above, including a first wall 21a, a second wall 21b, a third wall 21c, and a fourth wall 21d (see reference). Figure 2 The housing 20 includes a storage section 25 surrounded by a side wall portion 21.

[0091] like Figure 3As shown, an encapsulation component 85 is disposed in the receiving portion 25 of the housing 20. The encapsulation component 85 encapsulates the front sides of the ceramic circuit substrates 30, 40, and 50, the semiconductor chips 60a-62a, 60b-62b, and the wires 80. The encapsulation component 85 used here comprises a thermosetting resin and a filler contained in the thermosetting resin. The thermosetting resin is, for example, epoxy resin, phenolic resin, or maleimide resin. As an example of such an encapsulation component 85, there is epoxy resin containing a filler. The filler is an inorganic material. Examples of inorganic materials include silicon oxide, aluminum oxide, boron nitride, or aluminum nitride. In addition, the encapsulation component 85 may also be a silicone gel. It should be noted that the wires used in the semiconductor device 10 are collectively referred to as wires 80. The wires used for each function will be described later.

[0092] The semiconductor device 10 includes an inverter circuit. The inverter circuit is a circuit that converts direct current (DC) to alternating current (AC). Multiple semiconductor chips 60a-62a and 60b-62b are used to convert DC current input from the high-potential second P terminal 22c1 and first P terminal 22d1, and the low-potential second N terminal 22c2 and first N terminal 22d2, and output three-phase AC current from the U terminal 22b1, V terminal 22b2, and W terminal 22b3.

[0093] like Figure 2 As shown, the sidewall portion 21 has external connection terminals for the main electrode on the side of the second wall 21b (+X side). These external connection terminals are a second P terminal 22c1 and a second N terminal 22c2. The second P terminal 22c1 and the second N terminal 22c2 are respectively located on the side of the first wall 21a and the side of the third wall 21c with respect to the second wall 21b. The sidewall portion 21 also has external connection terminals for the main electrode on the side of the fourth wall 21d (-X side). These external connection terminals are a first P terminal 22d1 and a first N terminal 22d2. The first P terminal 22d1 and the first N terminal 22d2 are respectively located on the side of the first wall 21a and the side of the third wall 21c with respect to the fourth wall 21d.

[0094] The side wall portion 21 has external connection terminals for control on the third wall 21c side (-Y side). These external connection terminals are Gx terminals 22a1 and Gu terminals 22a2, Gy terminals 22a3 and Gv terminals 22a4, Gz terminals 22a5 and Gw terminals 22a6. These external connection terminals for control are respectively provided from the fourth wall 21d toward the second wall 21b with respect to the third wall 21c. Furthermore, Gx terminals 22a1 and Gu terminals 22a2 correspond to the ceramic circuit board 30. Gy terminals 22a3 and Gv terminals 22a4 correspond to the ceramic circuit board 40. Gz terminals 22a5 and Gw terminals 22a6 correspond to the ceramic circuit board 50.

[0095] The sidewall portion 21 is provided with external connection terminals for output on the side of the first wall 21a (+Y side). These external connection terminals are U terminal 22b1, V terminal 22b2, and W terminal 22b3. They are respectively provided from the fourth wall 21d toward the second wall 21b on the first wall 21a. Furthermore, U terminal 22b1, V terminal 22b2, and W terminal 22b3 correspond to ceramic circuit boards 30, 40, and 50, respectively.

[0096] In addition, such as Figure 3 As shown, the receiving portion 25 of the housing 20 extends through in the vertical direction (±Z direction). The first wall 21a, second wall 21b, third wall 21c, and fourth wall 21d have protrusions that project towards the receiving portion 25 along the first wall 21a, second wall 21b, third wall 21c, and fourth wall 21d, respectively. It should be noted that in... Figure 3 The image shows the protrusion 27d of the fourth wall 21d and the protrusion 27b of the second wall 21b. Thus, each protrusion has a main surface perpendicular to the inner wall of the side wall portion 21 and facing in the vertical direction (±Z direction).

[0097] Furthermore, a frame portion 26 is formed on the back side of the side wall portion 21 of the housing 20. More specifically, the cooling base plate 70 is fixed to the protrusion of the side wall portion 21 by an adhesive 86 (in Figure 3 The back side of the protrusions 27d and 27b is shown in the middle. Ceramic circuit boards 30, 40, and 50 (described later) are disposed on the cooling substrate 70. Figure 3 The diagram shows a first P-terminal 22d1 and a second P-terminal 22c1. The first P-terminal 22d1 and the second P-terminal 22c1 are L-shaped when viewed from the side and are embedded in the fourth wall 21d and the second wall 21b, respectively. One end of each of the first P-terminal 22d1 and the second P-terminal 22c1 extends upwards (in the +Z direction) from the front of the housing 20, while the other end protrudes upwards (in the +Z direction) from the protrusions of the second wall 21b and the fourth wall 21d. Multiple terminals other than the first P-terminal 22d1 and the second P-terminal 22c1 are also integrally formed with the first wall 21a, the second wall 21b, the third wall 21c, and the fourth wall 21d.

[0098] These terminals are made of copper, aluminum, iron, or an alloy containing at least one of these materials, which have excellent electrical conductivity. In addition, to improve corrosion resistance, the surfaces of the terminals may be plated with materials such as nickel, gold, tin, or an alloy containing at least one of these materials.

[0099] like Figures 2-4As shown, the ceramic circuit boards 30, 40, and 50 are rectangular in shape when viewed from above. The ceramic circuit boards 30, 40, and 50 are arranged from the fourth wall 21d toward the second wall 21b on the cooling substrate 70 within the housing portion 25. The ceramic circuit boards 30, 40, and 50 have ceramic substrates 31, 41, and 51 and metal plates 33, 43, and 53 formed on the back side of the ceramic substrates 31, 41, and 51. Furthermore, the ceramic circuit boards 30, 40, and 50 each have circuit patterns 32, 42, and 52 formed on the front side of the ceramic substrates 31, 41, and 51, respectively. It should be noted that circuit patterns 32, 42, and 52 are a collective term for the multiple circuit patterns included in each of the ceramic circuit boards 30, 40, and 50. Details regarding circuit patterns 32, 42, and 52 will be described later. The ceramic substrates 31, 41, and 51 and the metal plates 33, 43, and 53 are rectangular in shape when viewed from above. Furthermore, the corners of the ceramic substrates 31, 41, 51 and the metal plates 33, 43, 53 formed on their back sides can be chamfered with radius (R) or radius (C). The metal plates 33, 43, 53 are smaller than the ceramic substrates 31, 41, 51 when viewed from above, and are formed on the inner side of the ceramic substrates 31, 41, 51.

[0100] The ceramic substrates 31, 41, and 51 are mainly composed of ceramics with good thermal conductivity. Such ceramics are, for example, made of materials mainly composed of alumina, aluminum nitride, or silicon nitride. Furthermore, the thickness of the ceramic substrates 31, 41, and 51 is 0.2 mm or more and 2.5 mm or less.

[0101] Metal plates 33, 43, and 53 are primarily composed of metals with excellent thermal conductivity. Such metals are, for example, copper, aluminum, or alloys containing at least one of these. Furthermore, the thickness of metal plates 33, 43, and 53 is 0.1 mm or more and 5.0 mm or less. To improve corrosion resistance, the surfaces of metal plates 33, 43, and 53 may be plated. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0102] The circuit patterns 32, 42, and 52 are primarily composed of a metal with excellent electrical conductivity. Examples of such metals include copper, aluminum, or alloys containing at least one of these. Furthermore, the thickness of the circuit patterns 32, 42, and 52 is 0.1 mm or more and 5.0 mm or less. To improve corrosion resistance, the surfaces of the circuit patterns 32, 42, and 52 may be plated. Examples of plating materials used include nickel, nickel-phosphorus alloys, and nickel-boron alloys. The circuit patterns 32, 42, and 52 are obtained by forming a metal layer on the front side of the ceramic substrates 31, 41, and 51 and then etching that metal layer. Alternatively, the circuit patterns 32, 42, and 52, pre-cut from the metal layer, may be pressed onto the front side of the ceramic substrates 31, 41, and 51.

[0103] Circuit patterns 32, 42, and 52 also include high-potential circuit patterns 32a, 42a, and 52a; intermediate-potential circuit patterns 32b, 42b, and 52b; low-potential circuit patterns 32c, 42c, and 52c; and control circuit patterns 32d, 42d, and 52d. High-potential circuit patterns 32a, 42a, and 52a are disposed on the side of the first side 70a of the center line XL. Semiconductor chips 60a, 61a, and 62a are bonded to the high-potential circuit patterns 32a, 42a, and 52a.

[0104] Intermediate potential circuit patterns 32b, 42b, and 52b form a U-shape through portions parallel to the first side 70a, the second side 70b, and the third side 70c, respectively, and surround the high potential circuit patterns 32a, 42a, and 52a. Semiconductor chips 60b, 61b, and 62b are joined to the side portion of the center line XL of the intermediate potential circuit patterns 32b, 42b, and 52b on the third side 70c side. It should be noted that, in top view, semiconductor chips 60a, 61a, and 62a are offset towards the fourth side 70d compared to semiconductor chips 60b, 61b, and 62b.

[0105] Low-potential circuit patterns 32c, 42c, and 52c are disposed on the third side 70c side of the semiconductor chips 60b, 61b, and 62b of the intermediate-potential circuit patterns 32b, 42b, and 52b. Control circuit patterns 32d, 42d, and 52d are disposed on the fourth side 70d side, crossing the center line XL. Further details regarding the aforementioned circuit patterns 32, 42, and 52 will be described later.

[0106] As ceramic circuit substrates 30, 40, and 50 with such structures, DCB (Direct Copper Bonding) substrates and AMB (Active Metal Brazed) substrates can be used, for example. The ceramic circuit substrates 30, 40, and 50 enable heat generated in the semiconductor chip to be conducted to the outside via circuit patterns 32, 42, and 52, ceramic substrates 31, 41, and 51, and metal plates 33, 43, and 53.

[0107] Semiconductor chips 60a-62a and 60b-62b are primarily composed of silicon. These semiconductor chips 60a-62a and 60b-62b include RC (Reverse-Conducting) IGBTs. The RC-IGBT combines the functions of an IGBT and a FWD (Free Wheeling Diode). These semiconductor chips 60a-62a and 60b-62b have an input electrode (collector) as the main electrode on the back side, a gate as the control electrode on the front side, and an output electrode (emitter) as the main electrode on the front side. Alternatively, semiconductor chips 60a-62a and 60b-62b can also be power MOSFETs primarily composed of silicon carbide. These semiconductor chips 60a-62a and 60b-62b have an input electrode (drain) as the main electrode on the back side, a gate as the control electrode on the front side, and an output electrode (source) as the main electrode on the front side.

[0108] It should be noted that the switching element and diode element can also be provided in place of the semiconductor chips 60a-62a and 60b-62b, respectively. In this case, the switching element is, for example, an IGBT or a power MOSFET. When the switching element is an IGBT, it has an input electrode (collector) as the main electrode on the back side, a gate as the control electrode on the front side, and an output electrode (emitter) as the main electrode on the front side. When the switching element is a power MOSFET, it has an input electrode (drain) as the main electrode on the back side, a gate as the control electrode on the front side, and an output electrode (source) as the main electrode on the front side.

[0109] Diode elements are, for example, SBD (Schottky Barrier Diode) and PiN (P-intrinsic-N) diodes. Such diode elements have a cathode as the main electrode on the back side and an anode as the main electrode on the front side. The back side of the aforementioned diode element is bonded to a circuit pattern (symbol omitted) using solder (illustration omitted). It should be noted that electronic components may also be appropriately mounted according to the design and specifications of the semiconductor device 10. Electronic components include, for example, resistors, capacitors, and thermistors.

[0110] Semiconductor chips 60a-62a and 60b-62b are bonded to circuit patterns 32, 42, and 52 using solder. Lead-free solder is used. Lead-free solder may have at least one alloy selected from the following as its main component: an alloy composed of tin-silver-copper, an alloy composed of tin-zinc-bismuth, an alloy composed of tin-copper, or an alloy composed of tin-silver-indium-bismuth. Additionally, the solder may contain additives. Alternatively, a sintered metal body may be used instead of solder. The material of the sintered metal body is primarily composed of silver or a silver alloy.

[0111] Ceramic circuit boards 30, 40, and 50 and semiconductor chips 60a-62a and 60b-62b are housed within a storage section 25 on the side wall portion 21 of the housing 20. Within the storage section 25, circuit patterns 32, 42, and 52, semiconductor chips 60a-62a and 60b-62b, and multiple terminals are appropriately electrically and mechanically connected via wires 80. Thus, an inverter circuit is included within the storage section 25. It should be noted that the wires 80 are primarily composed of a metal with excellent conductivity. Examples of such metals include gold, silver, copper, aluminum, or alloys containing at least one of these. The diameter of the wire 80 connected to the control electrodes of the semiconductor chips 60a-62a and 60b-62b can be smaller than the diameter of the other wires 80. This reduces the bonding area and facilitates wiring to smaller areas. The diameter of the control wire 80 is, for example, 50 μm or more and 250 μm or less, while the diameter of the wire 80 used for other purposes is 300 μm or more and 600 μm or less.

[0112] Next, using Figure 5 and Figure 6 The details of the circuit patterns 32, 42, and 52 contained in the ceramic circuit boards 30, 40, and 50 are explained. Figure 5 and Figure 6 This is a top view of the circuit pattern of the ceramic circuit board included in the semiconductor device according to the embodiment. Circuit patterns 32 and 42 have the same shape; therefore, circuit pattern 32 will be described here, and the description of circuit pattern 42 will be omitted. Figure 5 and Figure 6 The circuit patterns 32 and 52 of the ceramic circuit boards 30 and 50 are shown.

[0113] like Figure 5As shown, the ceramic substrate 31 included in the ceramic circuit board 30 is rectangular in shape when viewed from above, and is formed in the order of first side 30a to fourth side 30d. That is, the third side 30c is arranged on the -Y side opposite to the first side 30a. Furthermore, the fourth side 30d is arranged on the -X side opposite to the second side 30b. The first side 30a and the third side 30c are the short sides, and the second side 30b and the fourth side 30d are the long sides. The first side 30a to the fourth side 30d of the ceramic substrate 31 are respectively opposite to the first side surface 70a to the fourth side surface 70d of the cooling substrate 70 and the first wall 21a to the fourth wall 21d of the housing 20.

[0114] As described above, a high-potential circuit pattern 32a, an intermediate-potential circuit pattern 32b, a low-potential circuit pattern 32c, and a control circuit pattern 32d are formed on the ceramic substrate 31.

[0115] The high-potential circuit pattern 32a includes wiring connection regions 32a2 and 32a3 and a chip mounting region 32a4, and forms a first cutout region 32a1. The wiring connection region 32a2 is separated from the center line XL towards the first side 30a, and the end 32a7 (high-potential edge portion) of the wiring connection region 32a2 on the fourth side 30d side is arranged along the fourth side 30d. Furthermore, the wiring connection region 32a2 is offset from the chip mounting region 32a4 towards the first side 30a side. The wiring connection region 32a3 is separated from the center line XL towards the first side 30a side, and is arranged parallel to the second side 30b, separated from the second side 30b side. The chip mounting region 32a4 is located on the side of the center line XL on the first side 30a side. For this chip mounting region 32a4, the semiconductor chip 60a is arranged with the control electrode 60a1 facing the fourth side 30d side (see reference). Figure 7 ).

[0116] Furthermore, the first cut-out region 32a1 is formed at the corner of the third side 30c on the fourth side 30d side of the high-potential circuit pattern 32a. That is, the first cut-out region 32a1 is formed by the edge of the wiring connection region 32a2 on the third side 30c side and the edge of the chip mounting region 32a4 on the fourth side 30d side. The first cut-out region 32a1 is rectangular in shape when viewed from above. The length of the first cut-out region 32a1 in the +Y direction is only required to ensure that the area where the wiring connection region 32a2 can be connected to the wire 80 is sufficient.

[0117] It should be noted that in this embodiment, cutout regions 32a5 and 32a6 are formed at the corners of the edge portion of the high-potential circuit pattern 32a opposite to the first edge 30a on the second side 30b side and at the corners of the edge portion of the high-potential circuit pattern 32a opposite to the second side 30b side on the third side 30c side, respectively. In other words, the cutout region 32a5 at the corner of the edge portion of the high-potential circuit pattern 32a opposite to the first side 30a on the second side 30b side is formed by the wiring connection region 32a2 protruding towards the first side 30a side. Furthermore, the cutout region 32a6 at the corner of the edge portion of the high-potential circuit pattern 32a opposite to the second side 30b side on the third side 30c side is formed by the edge portion of the chip mounting region 32a4 being offset towards the third side 30c side.

[0118] The intermediate potential circuit pattern 32b is a recessed portion with an opening on the fourth side 30d. The intermediate potential circuit pattern 32b includes an output wiring connection area 32b2, a connecting wiring area 32b3, and a chip mounting area 32b4. The output wiring connection area 32b2 is disposed on the first side 30a, separated from the center line XL by the high potential circuit pattern 32a. Furthermore, the output wiring connection area 32b2 extends along the first side 30a from the second side 30b to the fourth side 30d. A third cutout area 32b6 is formed on the edge of the output wiring connection area 32b2 on the third side 30c and near the fourth side 30d.

[0119] The chip mounting region 32b4 is disposed on the side of the third side 30c of the center line XL. That is, the chip mounting region 32b4 is adjacent to the third side 30c of the chip mounting region 32a4 of the high-potential circuit pattern 32a. The end 32b7 (medium-potential edge) of the fourth side 30d of the chip mounting region 32b4 is separated from the fourth side 30d towards the second side 30b. A second cutout region 32b5 is formed at the edge of the third side 30c and the corner of the fourth side 30d of the chip mounting region 32b4. The output wiring connection region 32b2 is opposite to the chip mounting region 32b4 across the high-potential circuit pattern 32a. For the chip mounting region 32b4, the semiconductor chip 60b is disposed with the control electrode 60b1 facing the fourth side 30d (see reference). Figure 7 Therefore, when viewed in the +Y direction, the control electrode 60a1 of semiconductor chip 60a is offset from the control electrode 60b1 of semiconductor chip 60b towards the fourth side 30d.

[0120] The connecting wiring region 32b3 is provided along the second side 30b, crossing the center line XL. Furthermore, the connecting wiring region 32b3 is opposite to the third side 30c of the output wiring connection region 32b2, and opposite to the first side 30a of the chip mounting region 32b4, and the corners of these sides on the second side 30b are integrally connected. The edge portion of the connecting wiring region 32b3 on the third side 30c includes a region protruding towards the fourth side 30d from its corner. That is, the first side 30a of the fourth side 30d of the connecting wiring region 32b3 is recessed.

[0121] The recessed portion 32b1 of the intermediate potential circuit pattern 32b is surrounded by the output wiring connection region 32b2, the connecting wiring region 32b3, and the chip mounting region 32b4. The recessed portion 32b1 surrounds at least a portion of the high potential circuit pattern 32a. At this time, the chip mounting region 32a4 of the high potential circuit pattern 32a is sandwiched between the output wiring connection region 32b2 and the chip mounting region 32b4. Furthermore, the edge of the wiring connection region 32a2 on the first side 30a enters the third cutout region 32b6, and the wiring connection region 32a3 enters the recess of the connecting wiring region 32b3.

[0122] Therefore, the intermediate potential circuit pattern 32b has a structure in which the output wiring connection area 32b2, the recessed portion 32b1 (configured for the chip mounting area 32a4), and the chip mounting area 32b4 are arranged in a direction parallel to the second side 30b and the fourth side 30d. Furthermore, at this time, the center line XL passes between the chip mounting areas 32a4 and 32b4.

[0123] The low-potential circuit pattern 32c includes a protruding region 32c1 and a conductive region 32c2. The conductive region 32c2 extends from the fourth side 30d to the second side 30b along the third side 30c. A recess may also be formed at the edge of the conductive region 32c2 on the third side 30c side, and other circuit patterns may be formed in this recess. Furthermore, the protruding region 32c1 protrudes from the corner of the fourth side 30d towards the first side 30a at the edge of the conductive region 32c2. Additionally, the end portion 32c7 (low-potential edge portion) of the low-potential circuit pattern 32c on the fourth side 30d side is disposed on the fourth side 30d side.

[0124] The control circuit pattern 32d is arranged across the center line XL on the opening side of the recess 32b1. That is, in the ceramic circuit board 30, a connecting wiring region 32b3 is arranged across the center line XL on the second side 30b, which is one end of the center line XL, and a control circuit pattern 32d is arranged across the center line XL on the fourth side 30d, which is the other end of the center line XL. In other words, an intermediate potential circuit pattern 32b and a control circuit pattern 32d are formed across the center line XL at both ends. Therefore, cracking of the ceramic circuit board 30 can be suppressed. Such a control circuit pattern 32d includes a first longitudinal extension 32d1, a first lateral extension 32d2, and a second longitudinal extension 32d3, and is crank-shaped.

[0125] The first longitudinal extension 32d1 is disposed along the fourth side 30d, crossing the center line XL. Specifically, the first longitudinal extension 32d1 is disposed in the area surrounded by the first cutout region 32a1 of the high-potential circuit pattern 32a, the edge portion of the chip mounting region 32b4 of the intermediate-potential circuit pattern 32b on the fourth side 30d, and the edge portion of the protruding region 32c1 of the low-potential circuit pattern 32c on the first side 30a. Furthermore, the first longitudinal extension 32d1 is adjacent to the end portion 32b7 of the chip mounting region 32b4 of the intermediate-potential circuit pattern 32b. The end portion 32a7 of the high-potential circuit pattern 32a, the first longitudinal extension 32d1, and the end portion 32c7 (low-potential edge portion) of the low-potential circuit pattern 32c are disposed along the fourth side 30d in this order. The end 32a7 of the high-potential circuit pattern 32a, the first longitudinal extension 32d1, and the end 32c7 (low-potential edge) of the low-potential circuit pattern 32c are configured to be aligned in a straight line in a direction parallel to the fourth side 30d when viewed from above.

[0126] The first lateral extension 32d2 extends vertically from the end of the first longitudinal extension 32d1 on the third side 30c side toward the second side 30b side. That is, the first lateral extension 32d2 is parallel to the center line XL and enters the gap (first part) between the second cut region 32b5 and the protruding region 32c1. In detail, the first lateral extension 32d2 is disposed between the edge of the second cut region 32b5 of the chip mounting region 32b4 of the intermediate potential circuit pattern 32b opposite to the third side 30c and the edge of the protruding region 32c1 of the low potential circuit pattern 32c on the first side 30a side.

[0127] The second longitudinal extension 32d3 extends vertically from the end of the first transverse extension 32d2 on the second side 30b side toward the third side 30c side. That is, the second longitudinal extension 32d3 is disposed in the gap (second part) between the edge of the second cut region 32b5 opposite to the fourth side 30d and the edge of the protruding region 32c1 on the second side 30b side in a direction orthogonal to the center line XL.

[0128] Furthermore, a connecting wiring region 32b3 with an intermediate potential circuit pattern 32b is arranged on the second side 30b, which intersects the center line XL, and a control circuit pattern 32d is arranged on the fourth side 30d, which intersects the center line XL. Therefore, the gap between the chip mounting region 32a4 (high potential circuit pattern 32a) and the chip mounting region 32b4 does not extend from the second side 30b to the fourth side 30d.

[0129] like Figure 6 As shown, the ceramic substrate 51 included in the ceramic circuit board 50 is rectangular in shape when viewed from above, and is formed in the order of first side 50a to fourth side 50d. That is, relative to the first side 50a, the third side 50c is arranged on the -Y side opposite to the third side. Furthermore, relative to the second side 50b, the fourth side 50d is arranged on the -X side opposite to the second side. The first side 50a and the third side 50c are short sides, and the second side 50b and the fourth side 50d are long sides. The first side 50a to the fourth side 50d of the ceramic substrate 51 are respectively opposite to the first side surface 70a to the fourth side surface 70d of the cooling substrate 70 and the first wall 21a to the fourth wall 21d of the housing 20.

[0130] The ceramic substrate 51 also has a high-potential circuit pattern 52a, an intermediate-potential circuit pattern 52b, a low-potential circuit pattern 52c, and a control circuit pattern 52d, similar to the circuit pattern 32 of the ceramic circuit substrate 30.

[0131] The high-potential circuit pattern 52a includes wiring connection regions 52a2 and 52a3 and a chip mounting region 52a4, and forms a first cutout region 52a1. The wiring connection region 52a2 separates from the center line XL towards the first side 50a. Furthermore, the end 52a7 (high-potential edge portion) of the wiring connection region 52a2 on the fourth side 50d side is disposed along the fourth side 50d. Additionally, the cutout region 52a6 at the corner of the edge portion of the high-potential circuit pattern 52a opposite to the second side 50b on the third side 50c side is formed by offsetting the edge portion of the chip mounting region 52a4 on the third side 50c side towards the third side 50c side. Although the high-potential circuit pattern 52a differs in size from the area included in the high-potential circuit pattern 32a, it has the same area.

[0132] The intermediate potential circuit pattern 52b also has a recessed shape with an opening on the fourth side 50d, including an output wiring connection area 52b2, a connecting wiring area 52b3, and a chip mounting area 52b4. Furthermore, the end 52b7 (intermediate potential edge) of the chip mounting area 52b4 on the fourth side 50d separates from the second side 50b. A second cutout area 52b5 is formed on the edge of the chip mounting area 52b4 on the third side 50c and at the corner of the fourth side 50d. Furthermore, the output wiring connection area 52b2 extends from the second side 50b to the fourth side 50d along the first side 50a. A third cutout area 52b6 is formed on the edge of the output wiring connection area 52b2 on the third side 50c and at the fourth side 50d. Furthermore, a cutout area 52b8 is formed at the corner of the chip mounting area 52b4 on the second side 50b and the third side 50c. Although the intermediate potential circuit pattern 52b differs in size from the intermediate potential circuit pattern 32b in the area it encompasses, it has the same area.

[0133] The low-potential circuit pattern 52c includes protruding regions 52c1 and 52c3 and a conductive region 52c2. The conductive region 52c2, like the conductive region 32c2, extends along the third side 50c from the fourth side 50d to the second side 50b. A recess may also be formed at the edge of the conductive region 52c2 on the third side 50c side, and other circuit patterns may be formed in this recess. Furthermore, the protruding region 52c1 protrudes from the corner of the fourth side 50d towards the first side 50a at the edge of the conductive region 52c2 on the first side 50a side. The protruding region 52c3 protrudes from the corner of the second side 50b towards the first side 50a at the edge of the conductive region 52c2 on the first side 50a side. The protruding region 52c3 enters the cutout region 52b8 of the chip mounting region 52b4. Additionally, the end portion 52c7 of the low-potential circuit pattern 52c on the fourth side 50d side is disposed on the fourth side 50d side.

[0134] The control circuit pattern 52d includes a first vertical extension 52d1 and a first horizontal extension 52d2, and is L-shaped. The first vertical extension 52d1, like the first vertical extension 32d1, is arranged along the fourth side 50d, crossing the center line XL. That is, the first vertical extension 52d1 is disposed in the area surrounded by the first cutout region 52a1 of the high-potential circuit pattern 52a, the edge portion of the chip mounting region 52b4 of the intermediate-potential circuit pattern 52b on the fourth side 50d side, and the edge portion of the protruding region 52c1 of the low-potential circuit pattern 52c on the first side 50a side. Furthermore, the first vertical extension 52d1 is adjacent to the end 52b7 (intermediate-potential edge portion) of the chip mounting region 52b4 of the intermediate-potential circuit pattern 52b. The end 52a7 of the high-potential circuit pattern 52a, the first longitudinal extension 52d1, the protruding area 52c1 of the low-potential circuit pattern 52c, and the end 52c7 (low-potential edge) are arranged along the fourth side 50d in this order. The end 52a7 of the high-potential circuit pattern 52a, the first longitudinal extension 52d1, the protruding area 52c1 of the low-potential circuit pattern 52c, and the end 52c7 (low-potential edge) are arranged to be aligned in a straight line in a direction parallel to the fourth side 50d when viewed from above.

[0135] The first lateral extension 52d2 extends vertically from the end of the first longitudinal extension 52d1 on the third side 50c side toward the second side 50b side. That is, the first lateral extension 52d2 is disposed between the edge of the second cut area 52b5 of the chip mounting area 52b4 of the intermediate potential circuit pattern 52b opposite to the third side 50c and the edge of the protruding area 52c1 of the low potential circuit pattern 52c on the first side 50a side.

[0136] When the semiconductor device 10 heats up with the semiconductor chips 60a-62a and 60b-62b, warping occurs correspondingly to the difference in the coefficients of thermal expansion between the semiconductor device 10 and the ceramic circuit substrates 30, 40, and 50 and the cooling substrate 70. In particular, when the semiconductor device 10 is fixed to a predetermined area via the fastening holes 24a-24d, the cooling substrate 70 is also fixed by the through holes 74a-74d at the four corners. Therefore, the ceramic circuit substrates 30, 40, and 50 are less likely to follow the warping of the cooling substrate 70 and may crack. Specifically, the semiconductor device 10... Figure 4 The center lines XL and YL shown are symmetrically warped. Therefore, the stress on the ceramic circuit boards 30, 40, and 50 is concentrated on the center lines XL and YL, making them prone to cracking along these lines.

[0137] Therefore, in such ceramic circuit boards 30, 40, and 50, control circuit patterns 32d, 42d, and 52d (first longitudinal extensions 32d1 and 52d1) are formed across the center line XL on ceramic substrates 31, 41, and 51. As a result, the strength of the ceramic substrates 31, 41, and 51 to fracture due to stress concentrated on the center line XL is increased, and the ceramic substrates 31, 41, and 51 become less prone to fracture.

[0138] Furthermore, in the ceramic circuit substrate 40, the intermediate potential circuit pattern 42b is formed in a manner that surrounds the high potential circuit pattern 42a. Therefore, the strength of the ceramic substrate 41 to fracture symmetrically about the center line YL is increased, and the ceramic substrate 41 becomes less prone to fracture.

[0139] Furthermore, in the ceramic circuit boards 30 and 50, the control circuit patterns 32d and 52d include first lateral extensions 32d2 and 52d2 that extend vertically from the ends of the first longitudinal extensions 32d1 and 52d1. The first longitudinal extensions 32d1 and 52d1 are strip-shaped with a narrow width (length in the X direction) and a long length (length in the Y direction). Therefore, sometimes breakage occurs between the long sides of the first longitudinal extensions 32d1 and 52d1 and other circuit patterns. By including the first lateral extensions 32d2 and 52d2 that extend vertically from the ends of the first longitudinal extensions 32d1 and 52d1 toward other circuit patterns, breakage can be suppressed.

[0140] The control circuit pattern 52d is L-shaped. The control circuit pattern 32d includes a second longitudinal extension 32d3 extending vertically from the end of the first lateral extension 32d2. The first lateral extension 32d2 and the second longitudinal extension 32d3 can also be narrow strips with long lengths. The control circuit pattern 32d is crank-shaped. Therefore, the strength against breakage of the ceramic substrate 31 along the first lateral extension 32d2 is increased, making the ceramic substrate 31 less prone to breakage. This is also true in ceramic substrate 41 including a control circuit pattern 42d with the same shape as the control circuit pattern 32d. Therefore, the reduction in the reliability of the semiconductor device 10 is suppressed.

[0141] Next, using Figure 7 and Figure 8 (as well as Figure 2 The flow and output of current in the semiconductor device 10 are explained. Figure 7 This is a diagram illustrating the wiring layout included in a semiconductor device according to an embodiment. Figure 8 This is a circuit diagram showing the equivalent circuit of the semiconductor device according to the embodiment. It should be noted that... Figure 7 Will Figure 2 The ceramic circuit board 30 is shown in magnification.

[0142] like Figure 8 As shown, the semiconductor device 10 has three branches A, B, and C. Branches A, B, and C convert the DC current input from the high-potential second P terminal 22c1 and the first P terminal 22d1, and the low-potential second N terminal 22c2 and the first N terminal 22d2, and output the three-phase AC current from the U terminal 22b1, V terminal 22b2, and W terminal 22b3.

[0143] Branch A includes an upper arm A1 and a lower arm A2. Branch A is composed of a ceramic circuit board 30, semiconductor chips 60a and 60b constituting the upper and lower arms A1 and A2, and wires 80 electrically connecting them. This branch A connects from the first P terminal 22d1 on the high-potential side via the main current wire 81a and the high-potential circuit pattern 32a to the input electrode on the back side of the semiconductor chip 60a constituting the upper arm A1. It should be noted that... Figure 2 As shown, the high-potential circuit pattern 32a is connected to the high-potential circuit pattern 42a of the ceramic circuit board 40 via the main current conductor. The high-potential circuit pattern 42a is also connected to the high-potential circuit pattern 52a of the ceramic circuit board 50 via the main current conductor. Furthermore, the high-potential circuit pattern 52a is connected to the second P terminal 22c1 on the high-potential side via the main current conductor. Thus, the first P terminal 22d1 and the second P terminal 22c1 are electrically connected.

[0144] The output electrode 60a2 on the front side of the semiconductor chip 60a is connected to the U terminal 22b1 via the main current wire 81b, the intermediate potential circuit pattern 32b (output wiring connection area 32b2), and the main current wire 81e.

[0145] Furthermore, the U terminal 22b1 is connected to the input electrode on the back side of the semiconductor chip 60b constituting the lower arm portion A2 via the main current conductor 81e and the intermediate potential circuit pattern 32b. Moreover, the output electrode 60b2 on the front side of the semiconductor chip 60b is electrically connected to the first N terminal 22d2 on the low potential side via the main current conductor 81c, the low potential circuit pattern 32c, and the main current conductor 81d connecting the low potential circuit pattern 32c. Furthermore, the main current conductor 81c extends in the opposite direction to the main current conductor 81b. It should be noted that, as... Figure 2 As shown, the low-potential circuit pattern 32c is connected to the low-potential circuit pattern 42c of the ceramic circuit board 40 via the main current conductor. The low-potential circuit pattern 42c is connected to the low-potential circuit pattern 52c of the ceramic circuit board 50 via the main current conductor. Furthermore, the low-potential circuit pattern 52c is connected to the second N terminal 22c2 on the low-potential side via the main current conductor. In this way, the first N terminal 22d2 and the second N terminal 22c2 are electrically connected.

[0146] The Gx terminal 22a1, serving as a control terminal, is connected to the control electrode 60a1 of the semiconductor chip 60a constituting the upper arm portion A1 via control wire 82a, control circuit pattern 32d, and control wire 82b. The Gu terminal 22a2, also serving as a control terminal, is connected to the control electrode 60b1 of the semiconductor chip 60b constituting the lower arm portion A2 via control wires 82c and 82d. It should be noted that the following primarily refers to… Figure 2 Please provide an explanation.

[0147] Branch B includes an upper arm B1 and a lower arm B2. Branch B is composed of a ceramic circuit board 40, semiconductor chips 61a and 61b constituting the upper and lower arms B1 and B2, and wires 80 electrically connecting them. In such a branch B, the first P terminal 22d1 on the high-potential side is connected to the input electrode on the back side of the semiconductor chip 61a constituting the upper arm B1 via the main current wire 81a, the high-potential circuit pattern 32a, the main current wire, and the high-potential circuit pattern 42a. It should be noted that, as described above, the high-potential circuit pattern 42a is connected to the second P terminal 22c1 on the high-potential side (see reference). Figure 2 The output electrode on the front side of semiconductor chip 61a is connected to V terminal 22b2 via main current wire, intermediate potential circuit pattern 42b, and main current wire.

[0148] Furthermore, the V terminal 22b2 is connected to the input electrode on the back side of the semiconductor chip 61b constituting the lower arm portion B2 via the main current conductor and the intermediate potential circuit pattern 42b. Moreover, the output electrode on the front side of the semiconductor chip 61b is electrically connected to the first N terminal 22d2 on the low-potential side via the main current conductor, the low-potential circuit pattern 42c, the main current conductor connecting the low-potential circuit pattern 42c, the low-potential circuit pattern 32c, and the main current conductor 81d. It should be noted that, as described above, the low-potential circuit pattern 42c is electrically connected to the second N terminal 22c2 on the low-potential side.

[0149] The Gy terminal 22a3, serving as a control terminal, is connected to the control electrode of the semiconductor chip 61a constituting the upper arm portion B1 via a control wire, a control circuit pattern 42d, and another control wire. The Gv terminal 22a4, also serving as a control terminal, is connected to the control electrode of the semiconductor chip 61b constituting the lower arm portion B2 via a control wire.

[0150] Branch C includes an upper arm C1 and a lower arm C2. Branch C is composed of a ceramic circuit board 50, semiconductor chips 62a and 62b constituting the upper and lower arms C1 and C2, and wires 80 electrically connecting them. In such branch C, the first P terminal 22d1 on the high-potential side is connected to the input electrode on the back side of the semiconductor chip 62a constituting the upper arm C1 via a main current wire 81a, a high-potential circuit pattern 32a, a main current wire, a high-potential circuit pattern 42a, a main current wire, and a high-potential circuit pattern 52a. It should be noted that, as described above, the high-potential circuit pattern 52a is connected to the second P terminal 22c1 on the high-potential side. The output electrode on the front side of the semiconductor chip 62a is connected to the W terminal 22b3 via a main current wire, an intermediate potential circuit pattern 52b, and a main current wire.

[0151] Furthermore, terminal W22b3 is connected to the input electrode on the back side of semiconductor chip 62b constituting lower arm C2 via main current wire and intermediate potential circuit pattern 52b. Moreover, the output electrode on the front side of semiconductor chip 62b is electrically connected to the first N terminal 22d2 on the low potential side via main current wire, low potential circuit pattern 52c, main current wire connecting low potential circuit pattern 52c, low potential circuit pattern 42c, main current wire, low potential circuit pattern 32c, and main current wire 81d. It should be noted that, as described above, low potential circuit pattern 52c is electrically connected to the second N terminal 22c2 on the low potential side.

[0152] The Gz terminal 22a5, serving as a control terminal, is connected to the control electrode of the semiconductor chip 62a constituting the upper arm portion C1 via a control wire, a control circuit pattern 52d, and another control wire. The Gw terminal 22a6, also serving as a control terminal, is connected to the control electrode of the semiconductor chip 62b constituting the lower arm portion C2 via a control wire.

[0153] In the semiconductor device 10, signals are input from the high-potential second P terminal 22c1 and the first P terminal 22d1, and the low-potential second N terminal 22c2 and the first N terminal 22d2. Signals are input from the Gx, Gu, Gy, Gv, Gz, and Gw terminals 22a1 to 22a6 at predetermined times, thereby outputting three-phase AC signals from the U terminal 22b1, V terminal 22b2, and W terminal 22b3.

[0154] The aforementioned semiconductor device 10 includes semiconductor chips 60a-62a, 60b-62b, a cooling substrate 70, and ceramic circuit boards 30, 40, and 50. The cooling substrate 70 is rectangular in shape when viewed from above, and has first side surfaces 70a to fourth side surfaces 70d arranged sequentially, with a center line XL parallel to and passing through the center of the first side surfaces 70a and third side surfaces 70c. The ceramic circuit boards 30, 40, and 50 include ceramic substrates 31, 41, and 51, and high-potential circuit patterns 32a, 42a, and 52a on the front surface of the ceramic substrates 31, 41, and 51, including intermediate-potential circuit patterns 32b, 42b, and 52b on the semiconductor chips 60a-62a, low-potential circuit patterns 32c, 42c, and 52c, and control circuit patterns 32d, 42d, and 52d. The ceramic circuit boards 30, 40, and 50 are arranged across the center line XL on the front surface of the cooling substrate 70. Furthermore, the high-potential circuit patterns 32a, 42a, and 52a have chip mounting regions 32a4 and 52a4 on the side of the first side 70a of the center line XL, which are for mounting semiconductor chips 60a to 62a. Intermediate potential circuit patterns 32b, 42b, and 52b are concave shapes with openings on the fourth side 70d side, and include recesses 32b1 and 52b1 surrounding at least a portion of chip mounting regions 32a4 and 52a4, chip mounting regions 32b4 and 52b4 mounted on the side of the third side 70c side of the center line XL, output wiring connection regions 32b2 and 52b2 opposite to the chip mounting regions 32b4 and 52b4 across the recesses 32b1 and 52b1, and connecting wiring regions 32b3 and 52b3 connecting the chip mounting regions 32b4 and 52b4 and the output wiring connection regions 32b2 and 52b2 and arranged across the center line XL. Control circuit patterns 32d, 42d, and 52d are arranged across the center line XL on the opening side of the recesses 32b1 and 52b1. Thus, in the ceramic circuit substrates 30, 40, and 50, the control circuit patterns 32d, 42d, and 52d are formed on the ceramic substrates 31, 41, and 51, spanning the center line XL. Therefore, the strength of cracks in the ceramic substrates 31, 41, and 51 symmetrical about the center line XL is increased, making the ceramic substrates 31, 41, and 51 less prone to cracking. This suppresses any decrease in the reliability of the semiconductor device 10.

[0155] The above only illustrates the principle of the invention. Furthermore, those skilled in the art can make various modifications and alterations. The invention is not limited to the precise structures and application examples shown and described above; all corresponding modifications and equivalents are considered to be within the scope of the invention based on the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, have: First semiconductor chip, second semiconductor chip; The cooling substrate is rectangular in shape when viewed from above, and has a first side, a second side, a third side and a fourth side arranged in sequence, and has a center line that is parallel to the first side and the third side and passes through the center. as well as An insulating circuit board includes an insulating plate, a high-potential circuit pattern disposed on the front side of the insulating plate and on which a first semiconductor chip is mounted, an intermediate-potential circuit pattern on which a second semiconductor chip is mounted, a low-potential circuit pattern, and a control circuit pattern. The insulating circuit board is disposed on the front side of a cooling substrate across the center line. The high-potential circuit pattern has a first chip mounting area on the side of the first side of the center line, where the first semiconductor chip is mounted. The intermediate potential circuit pattern is a concave shape with an opening on the fourth side surface, and includes a recessed portion surrounding at least a portion of the first chip mounting region, a second chip mounting region mounted on the third side surface disposed on the center line and mounting the second semiconductor chip, an output wiring connection region opposite to the second chip mounting region across the recessed portion, and a connecting wiring region connecting the second chip mounting region and the output wiring connection region and disposed across the center line. The control circuit pattern is arranged across the center line on the opening side of the recess.

2. The semiconductor device according to claim 1, characterized in that, The low-potential circuit pattern is configured to be opposite the first chip mounting area across the second chip mounting area.

3. The semiconductor device according to claim 1 or 2, characterized in that, The control circuit pattern is configured to be adjacent to the fourth side of the first chip mounting region and the second chip mounting region.

4. The semiconductor device according to claim 3, characterized in that, A first cut-out area is formed at the corner of the edge of the fourth side of the high-potential circuit pattern near the third side, and the control circuit pattern enters the first cut-out area.

5. The semiconductor device according to claim 4, characterized in that, The intermediate potential edge of the fourth side surface of the second chip mounting area of ​​the intermediate potential circuit pattern is located closer to the second side surface than the high potential edge of the fourth side surface of the high potential circuit pattern and the low potential edge of the fourth side surface of the low potential circuit pattern. The control circuit pattern has a first longitudinal extension, which is configured to be adjacent to the intermediate potential edge of the second chip mounting area of ​​the intermediate potential circuit pattern, and aligned in a straight line with the high potential edge of the high potential circuit pattern and the low potential edge of the low potential circuit pattern in a direction parallel to the fourth side when viewed from above.

6. The semiconductor device according to claim 5, characterized in that, A second cutout area is formed at the corner of the third side surface of the intermediate potential edge portion of the second chip mounting area in the intermediate potential circuit pattern. The low-potential circuit pattern has a protruding area that enters the second cut area. The control circuit pattern also includes a first lateral extension that enters the gap between the second cut area and the protruding area.

7. The semiconductor device according to claim 6, characterized in that, The second incision area appears rectangular when viewed from above. The gap between the protruding area of ​​the low-potential circuit pattern and the second cut area includes a first portion parallel to the centerline.

8. The semiconductor device according to claim 7, characterized in that, The gap also includes a second portion that is orthogonal to the centerline and communicates with the first portion. The control circuit pattern also includes a second longitudinal extension that enters the gap along the second portion, and the control circuit pattern is crank-shaped.

9. The semiconductor device according to claim 1, characterized in that, The first semiconductor chip has a first main electrode on its front side. The semiconductor device includes a first main current wiring that connects the first main electrode to the output wiring connection region in a manner that extends parallel to the second side and the fourth side.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor device has an output terminal on the first side. The semiconductor device includes a second main current wiring that connects the output terminal to the output wiring connection area in a manner that extends parallel to the second side and the fourth side.

11. The semiconductor device according to claim 9 or 10, characterized in that, The second semiconductor chip has a second main electrode on the front side. The semiconductor device includes a second main current wiring that connects the second main electrode to the low-potential circuit pattern in a manner that extends parallel to the second side and the fourth side.

12. The semiconductor device according to claim 9, characterized in that, The semiconductor device has a high-potential terminal disposed opposite to the high-potential circuit pattern on the fourth side or the second side. The semiconductor device includes a high-potential main current wiring that connects the high-potential terminal to the high-potential circuit pattern in a manner that extends parallel to the first side and the third side.

13. The semiconductor device according to claim 9, characterized in that, The semiconductor device has a low-potential terminal disposed opposite to the low-potential circuit pattern on the fourth side or the second side. The semiconductor device includes low-potential main current wiring that connects the low-potential terminals to the low-potential circuit pattern in a manner that extends parallel to the first side and the third side.

14. The semiconductor device according to claim 9, characterized in that, The first semiconductor chip has a first control electrode on its front side. The semiconductor device has a first control terminal disposed on the third side opposite to the low-potential circuit pattern. The semiconductor device includes a first control wiring that connects the first control terminal to the first control electrode via the control circuit pattern.

15. The semiconductor device according to claim 9, characterized in that, The second semiconductor chip has a second control electrode on its front side. The semiconductor device has a second control terminal disposed on the third side opposite to the low-potential circuit pattern. The semiconductor device includes a second control wiring that crosses the low-potential circuit pattern to connect the second control terminal to the second control electrode.

16. The semiconductor device according to claim 1, characterized in that, Through holes for fastening are formed at the four corners of the cooling substrate.

17. The semiconductor device according to claim 1, characterized in that, Multiple insulating circuit boards are arranged along the center line on the cooling substrate.

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