Power silicon carbide based semiconductor devices with improved short circuit capability and methods of manufacturing such devices

Abstract

A power semiconductor device has a semiconductor layer structure including a silicon carbide drift region having a first conductivity type, first and second wells doped with a dopant having a second conductivity type in the silicon carbide drift region, and a JFET region between the first and second wells. The first and second wells each include a main well and a side well between the main well and the JFET region, and each side well includes a respective channel region. A doping concentration of the JFET region exceeds a doping concentration of the silicon carbide drift region, and a minimum width of an upper portion of the JFET region is greater than a minimum width of a lower portion of the JFET region.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Patent Application Serial No. 17 / 004,531, filed August 27, 2020, the entirety of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present invention relates to semiconductor devices, and more particularly to power semiconductor devices. BACKGROUND

[0004] Metal oxide semiconductor field effect transistors (“MOSFETs”) are a well-known type of transistor that can be used as switching devices. MOSFETs include a source region and a drain region separated by a channel region, and a gate electrode separated from the channel region by a thin gate insulating layer such as a layer of silicon oxide. A MOSFET can be turned on or off by applying a gate bias voltage to the gate electrode. When a MOSFET is turned on by applying a gate bias voltage greater than or equal to a “threshold” voltage for the device, current is conducted through the channel region between the source and drain regions of the MOSFET. When the bias voltage is removed from the gate electrode (or reduced below the threshold voltage level), current stops being conducted through the channel region. By way of example, an n-type MOSFET has n-type source and drain regions and a p-type channel. The n-type MOSFET can be designed to turn on when a gate bias voltage is applied to the gate electrode sufficient to create a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source and drain regions, thereby allowing majority carrier conduction therebetween. MOSFETs can also be designed as “normally on” devices that are turned off by applying a gate bias voltage to the gate electrode.

[0005] Because the gate electrode of a MOSFET is insulated from the channel region by the gate insulating layer, minimal gate current is required to maintain the MOSFET in its on state or to switch the MOSFET between its on and off states. The gate current remains small during switching because the gate electrode forms a capacitor with the channel region. Thus, only minimal charging and discharging current is required during switching, allowing for less complex gate drive circuitry.

[0006] There is an increasing demand for high power MOSFETs and other gate electrode controlled semiconductor devices that can pass large currents (e.g., hundreds of amperes) in their "on" state and block large voltages (e.g., thousands of volts) in their reverse blocking state. To support high current densities and block such high voltages, power MOSFETs typically have a vertical structure with the source and drain located on opposite sides of a thick semiconductor layer structure. In very high power applications, power MOSFETs are often formed in a wide bandgap semiconductor material system. In this document, the term "wide bandgap semiconductor" encompasses any semiconductor having a bandgap of at least 1.4 eV, such as, for example, silicon carbide (SiC). Silicon carbide has a number of advantageous properties, including, for example, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. Electronic devices formed using silicon carbide can have the ability to operate at higher temperatures, at high power densities, at higher speeds, at higher power levels, and / or at higher radiation densities relative to devices formed using other semiconductor materials, such as, for example, silicon. SUMMARY

[0007] According to some embodiments of the present invention, there is provided a power semiconductor device having a semiconductor layer structure including a silicon carbide drift region having a first conductivity type, a first well located in an upper portion of the silicon carbide drift region, the first well doped with dopants having a second conductivity type different from the first conductivity type, a second well located in the upper portion of the silicon carbide drift region, the second well spaced apart from the first well, the second well doped with dopants having the second conductivity type, and a JFET region in the silicon carbide drift region between the first well and the second well. The JFET region has a doping concentration that exceeds a doping concentration of the silicon carbide drift region, and a maximum width of an upper half of the JFET region is at least 30% greater than a minimum width of a lower half of the JFET region.

[0008] In some embodiments, the first well can include a first main well and a first side well located between the first main well and the JFET region, and the second well can include a second main well and a second side well located between the second main well. The first side well can include a first channel region, and the second side well can include a second channel region.

[0009] In some embodiments, the first side well has a depth from an upper surface of the semiconductor layer structure of at least 1.0 micrometers.

[0010] In some embodiments, the power semiconductor device can further include a first source / drain contact on a lower surface of the silicon carbide drift region, a source / drain region in an upper portion of the first main well having the first conductivity type and extending to an upper surface of the first well, a second source / drain contact on an upper surface of the source / drain region, a gate insulating layer on the JFET region and on the first well, and a gate electrode on the gate insulating layer.

[0011] In some embodiments, a depth of the JFET region from an upper surface of the semiconductor layer structure can be equal to or exceed a depth of the first side well from the upper surface of the semiconductor layer structure.

[0012] In some embodiments, a peak doping concentration of the first side well can exceed 5x10 17 / cm 3 and occurs at a depth between 0.8 and 1.2 microns below the upper surface of the semiconductor layer structure.

[0013] In some embodiments, a depth of the first side well from an upper surface of the semiconductor layer structure can be less than 1.6 microns.

[0014] In some embodiments, a depth of the JFET region from an upper surface of the semiconductor layer structure can be between 1.0 and 1.2 times a depth of the first side well from the upper surface of the semiconductor layer structure.

[0015] In some embodiments, a peak doping concentration of an upper 0.2 microns of the first side well can be at least one order of magnitude less than a peak doping concentration of the first side well.

[0016] In some embodiments, a maximum width of an upper portion of the JFET region can be at least 50% greater than a minimum width of a lower portion of the JFET region.

[0017] In some embodiments, a peak doping concentration of the first side well can occur at a first depth from an upper surface of the semiconductor layer structure, and a doping concentration of the JFET region at the first depth from the upper surface of the semiconductor layer structure can be at least one order of magnitude less than the peak doping concentration of the first side well.

[0018] In some embodiments, a depth of the first side well can be between 1.0 and 1.5 microns from an upper surface of the semiconductor layer structure, a depth of the JFET region from the upper surface of the semiconductor layer structure can be between 1.0 and 1.7 microns, and the depth of the JFET region can be at least as deep as the depth of the first side well.

[0019] In some embodiments, a distance between the first side well and the second side well can be less than 1.5 microns.

[0020] In some embodiments, the JFET region can include an implanted region implanted with dopants having the first conductivity type.

[0021] In some embodiments, a maximum width of an upper half of the JFET region can be between 40% and 80% greater than a minimum width of a lower half of the JFET region.

[0022] In some embodiments, a width of the lower half of the JFET region can be less than 50% of a depth of the JFET region.

[0023] In some embodiments, the JFET region can extend below the first well.

[0024] According to further embodiments of the present application, there is provided a power semiconductor device having a semiconductor layer structure including a silicon carbide drift region having a first conductivity type, a first well located in an upper portion of the silicon carbide drift region, the first well doped with dopants having a second conductivity type different from the first conductivity type, a second well located in the upper portion of the silicon carbide drift region, the second well spaced apart from the first well, the second well doped with dopants having the second conductivity type, and a JFET region in the silicon carbide drift region between the first well and the second well. A depth of the JFET region from an upper surface of the semiconductor layer structure exceeds a depth of the first well from the upper surface of the semiconductor layer structure, and a maximum width of an upper half of the JFET region is greater than a minimum width of a lower half of the JFET region.

[0025] In some embodiments, a doping concentration of the JFET region can exceed a doping concentration of the silicon carbide drift region, and a depth of the first well from an upper surface of the semiconductor layer structure can be at least 1.0 microns, and a peak doping concentration of the first well exceeds a doping concentration of the first well at a depth of 0.2 microns from the upper surface of the semiconductor layer structure by at least one order of magnitude.

[0026] In some embodiments, a peak doping concentration of the first well can exceed 5x10 17 / cm 3 and occurs at a depth between 0.8 and 1.2 microns below the upper surface of the semiconductor layer structure.

[0027] In some embodiments, a depth of the first well from an upper surface of the semiconductor layer structure can be between 1.0 and 1.6 microns.

[0028] In some embodiments, a depth of the JFET region from an upper surface of the semiconductor layer structure can be less than 1.2 times a depth of the first well from the upper surface of the semiconductor layer structure.

[0029] In some embodiments, a maximum width of the upper half of the JFET region can be at least 50% greater than a minimum width of the lower half of the JFET region.

[0030] In some embodiments, a peak doping concentration of the first well can occur at a first depth from an upper surface of the semiconductor layer structure, and a doping concentration of the JFET region at the first depth from the upper surface of the semiconductor layer structure can be at least one order of magnitude lower than the peak doping concentration of the first well.

[0031] In some embodiments, a maximum width of the upper half of the JFET region can be between 40% and 80% greater than a minimum width of the lower half of the JFET region.

[0032] In some embodiments, the JFET region can extend below the first well.

[0033] According to yet another embodiment of the present invention, there is provided a power semiconductor device having a semiconductor layer structure including a silicon carbide drift region having a first conductivity type, a first well located in an upper portion of the silicon carbide drift region, the first well doped with dopants having a second conductivity type different from the first conductivity type, a second well located in the upper portion of the silicon carbide drift region, the second well spaced apart from the first well, the second well doped with dopants having the second conductivity type, and a JFET region in the silicon carbide drift region between the first well and the second well. A doping concentration of the JFET region exceeds a doping concentration of the silicon carbide drift region. A peak doping concentration of the first well occurs at a first depth from an upper surface of the semiconductor layer structure, and a doping concentration of the JFET region at the first depth is at least one order of magnitude lower than the peak doping concentration of the first well. A depth of the JFET region from the upper surface of the semiconductor layer structure exceeds a depth of the first well from the upper surface of the semiconductor layer structure.

[0034] In some embodiments, the peak doping concentration of the first well can exceed 5 x 1018 / cm3. 17 / cm 3 and can occur at a depth between 0.7 and 1.2 microns below the upper surface of the semiconductor layer structure.

[0035] In some embodiments, the depth of the JFET region from the upper surface of the semiconductor layer structure can be less than 1.2 times the depth of the first well from the upper surface of the semiconductor layer structure.

[0036] In some embodiments, a peak doping concentration of an upper 0.2 microns of the first well can be at least one order of magnitude lower than the peak doping concentration of the first well.

[0037] In some embodiments, a maximum width of the upper half of the JFET region can be at least 50% greater than a minimum width of the lower half of the JFET region.

[0038] In some embodiments, the JFET region can include an implanted region implanted with dopants of the first conductivity type.

[0039] In some embodiments, the JFET region can extend below the first well.

[0040] According to additional embodiments of the present invention, methods of forming a power semiconductor device are provided. According to these methods, a silicon carbide drift region having a first conductivity type is provided. Second conductivity type dopants are implanted into an upper portion of the silicon carbide drift region to form a first well and a second well. First conductivity type dopants are implanted into an upper portion of the silicon carbide drift region between the first well and the second well to form a JFET region between the first well and the second well via ion implantation, wherein the silicon carbide drift region and the first and second wells are part of a semiconductor layer structure. A minimum width of an upper half of the JFET region is at least 30% greater than a minimum width of a lower half of the JFET region.

[0041] In some embodiments, the first well can include a first main well and a first side well between the first main well and the JFET region, the first side well including a first channel region, and the second well can include a second main well and a second side well between the second main well and the JFET region, the second side well including a second channel region, and a depth of the first side well from an upper surface of the semiconductor layer structure can be at least 1.0 microns.

[0042] In some embodiments, a peak dopant concentration of the first side well can exceed 5xl0 17 / cm 3 and can occur at a depth between 0.8 and 1.2 microns below the upper surface of the semiconductor layer structure.

[0043] In some embodiments, a depth of the JFET region from the upper surface of the semiconductor layer structure can be between 1.0 and 1.2 times a depth of the first side well from the upper surface of the semiconductor layer structure.

[0044] In some embodiments, a peak dopant concentration of an upper 0.2 microns of the first side well can be at least one order of magnitude less than a peak dopant concentration of the first side well.

[0045] In some embodiments, the JFET region can be formed prior to forming the first well and the second well.

[0046] In some embodiments, the JFET region can extend below the first well and the second well. BRIEF DESCRIPTION OF DRAWINGS

[0047] FIG. 1A is a schematic cross-sectional view of a unit cell of a conventional power MOSFET.

[0048] FIG. IB is a plot showing the doping profile of the side p-well of the unit cell of FIG. 1A as a function of depth.

[0049] FIG. 2A is a schematic cross-sectional view of a unit cell of another conventional power MOSFET.

[0050] FIG. 2B is a plot showing the doping profile of the side p-well of the unit cell of FIG. 2A as a function of depth.

[0051] FIG. 3A is a schematic cross-sectional view of a unit cell of yet another conventional power MOSFET.

[0052] FIG. 3B is a plot showing the doping profile of the side p-well of the unit cell of FIG. 3A as a function of depth.

[0053] Figure 4 is a schematic plan view of a semiconductor wafer including a plurality of power MOSFETs according to an embodiment of the present application.

[0054] Figure 5A is a schematic plan view of one of the power MOSFETs on the semiconductor wafer of Figure 4

[0055] Figure 5B is a schematic plan view of the power MOSFET of Figure 5A

[0056] Figure 6A is a schematic plan view of a portion of the unit cell of the power MOSFET of Figures 5A-5B

[0057] Figure 6B is a schematic cross-sectional view taken along line 6B-6B of Figure 6A

[0058] Figure 6C is a plot showing the doping profile of the channel region of the unit cell of Figures 6A-6B

[0059] Figure 6D is a plot showing the doping profile of the JFET region of the unit cell of Figures 6A-6B

[0060] Figure 6E is a schematic cross-sectional view of a modified version of the unit cell of Figure 6B

[0061] Figure 7 is a circuit diagram illustrating conditions for testing short circuit capability of a power MOSFET.​​​​​​​

[0062] Figure 8 is a plot illustrating simulated drain current and lattice temperature as a function of time for a conventional MOSFET and a MOSFET according to an embodiment of the application.

[0063] Figures 9A-9F is a schematic cross-sectional view illustrating a method of fabricating a power MOSFET according to an embodiment of the application. DETAILED DESCRIPTION

[0064] Power silicon carbide MOSFETs are currently used for applications requiring high voltage blocking, such as blocking thousands of volts. For example, silicon carbide MOSFETs are commercially available with a rated current density of 10 A / cm 2 or higher, which will block a voltage of at least 10 kV. To form such a device, a plurality of "unit cell" MOSFET transistors are typically formed that are electrically connected in parallel. In high power applications, a large number of these unit cells (e.g., hundreds or thousands) are typically provided on a single semiconductor substrate, and a gate electrode pattern is formed on the top side of the semiconductor substrate that serves as the gate electrode for all of the unit cells. The opposite (bottom) side of the semiconductor substrate serves as the common drain for all of the unit cells of the device. A plurality of source contacts are formed on the source regions in the semiconductor layer structure that are exposed within openings of the gate electrode pattern. These source contacts are also electrically connected to one another to serve as the common source. The resulting device has three terminals, namely, a common source terminal, a common drain terminal, and a common gate electrode, which serve as the terminals for all of the individual unit cell transistors. It will be recognized that the above description is for n-type MOSFETs; for p-type MOSFETs, the locations of the drain and source will be reversed.

[0065] There is a continuing need to improve the performance of power MOSFETs and other gate-controlled power semiconductor devices. Several important performance parameters for power MOSFETs are the mobility of the charge carriers in the channel region, the threshold voltage, the on-state resistance, the high frequency switching speed, the device reliability, and the "short circuit capability" of the device.

[0066] FIG. 1A is a schematic cross-sectional view of a unit cell transistor 100 of a conventional silicon carbide power MOSFET (FIG. 1A also shows portions of two adjacent unit cells). FIG. IB is a plot showing the doping profile of the side p-well of the unit cell transistor 100 as a function of depth from the top surface of the semiconductor layer structure of the device.

[0067] As shown in Figure 1A, the unit cell transistor 100 includes an n-type silicon carbide semiconductor substrate 110. A lightly doped n-type (n-) silicon carbide drift region 120 is provided on the substrate 110. The upper portion of the n-type silicon carbide drift region 120 can be p-type doped by ion implantation to form a p-well 130. Each p-well 130 includes a main p-well 132 and a pair of side p-wells 134. The main p-well 132 has a diameter between 5 x 10⁻⁶. 18 / cm 3 and 5x10 19 / cm 3 The doping concentration varies between p-wells. The deeper the p-well 132 extends into the silicon carbide drift region 120, the higher the dopant concentration generally is. The side p-wells 134, which serve as the channel region 136 for the unit cell 100, are lightly doped with p-type dopant than the main p-well 132. The doping concentration profile of each side p-well 134 is shown in Figure 1B (discussed below). Each p-well 130 is formed by ion implantation using two ion implantation steps.

[0068] Heavily doped (n) + An n-type silicon carbide source region 140 is formed in the upper portion of the p-well 130. The n-type source region 140 can also be formed by ion implantation. Heavily doped (n... + The n-type silicon carbide region 140 serves as the source region of the unit cell transistor 100. The drift region 120 and the substrate 110 together serve as the common drain region of the unit cell transistor 100. The n-type silicon carbide substrate 110, the n-type silicon carbide drift region 120, the p-well 130, and the n-type source region 140 formed therein can collectively constitute the semiconductor layer structure 150 of the unit cell transistor 100.

[0069] An n-type epitaxial pattern 160 is formed on the semiconductor layer structure 150. The n-type epitaxial pattern 160 may have a low doping concentration (e.g., between 1 x 10⁻⁶). 16 / cm 3 and 1x10 17 / cm 3 (between). The n-type epitaxial pattern 160 can be, for example, 0.5 to 1.5 micrometers thick. A silicon oxide gate insulating layer 170 is formed on the upper surface of the n-type epitaxial pattern 160. A gate electrode 172 is formed on the gate insulating layer 170 opposite to the n-type epitaxial pattern 160. A source contact 180 is formed in an opening in the n-type epitaxial pattern 160 to contact the heavily doped n-type source region 140. A drain contact 190 is formed on the lower surface of the substrate 110.

[0070] As described above, the channel region 136 is provided in the side p-well 134. When a sufficient bias voltage is applied to the gate electrode 172, the channel region 136 electrically connects the n-type source region 140 to the drift region 120. When such a bias voltage is applied to the gate electrode 172, current can flow from the n-type source region 140 through the channel region 136 to the portion of the drift region 120 under the gate electrode 172, which is referred to as the "JFET region" 122 of the device.

[0071] FIG. IB is a graph showing the doping profile of the side p-well 134 as a function of depth from the upper surface of the semiconductor layer structure 150. The p-well 130 is formed by implanting aluminum ions into the silicon carbide drift region 120. As shown in FIG. IB, the side p-well 134 can have a graded doping profile, in which the aluminum ion doping concentration is approximately 1 x 1019 / cm3at the upper surface of the side p-well 134, increases to approximately 5 x 1019 / cm3at a depth of approximately 0.5 microns from the n-type epitaxial pattern 160, and then decreases rapidly as the depth increases. 18 / cm 3 The doping concentration then increases to approximately 5 x 1019 / cm3at a depth of approximately 0.5 microns from the n-type epitaxial pattern 160, and then decreases rapidly as the depth increases. Because a relatively high doping concentration is provided at the surface of the side p-well 134, a relatively low implant energy (e.g., 300-350 keV) can be used to implant the side p-well 134. 19 / cm 3 The doping concentration then increases to approximately 5 x 1019 / cm3at a depth of approximately 0.5 microns from the n-type epitaxial pattern 160, and then decreases rapidly as the depth increases. Because a relatively high doping concentration is provided at the surface of the side p-well 134, a relatively low implant energy (e.g., 300-350 keV) can be used to implant the side p-well 134.

[0072] As described above, two important performance parameters for a power MOSFET are the mobility of the charge carriers in the channel region of the unit cell transistor and the threshold voltage of the device. The doping profile of the channel region 136 can have a significant impact on both of these performance parameters. In order to have a high channel mobility, it can be desirable to have a low doping concentration directly under the gate insulating layer 170. Thus, providing the relatively lightly doped n-type epitaxial pattern 160 directly under the gate insulating layer 170 can improve the channel mobility. This design also results in a low threshold voltage. Furthermore, because ion implant damage will not be directly under the gate insulating layer 170, damage caused by such ion implantation is removed even further from the gate insulating layer 170 and thus has less impact on the performance of the device.

[0073] The MOSFET formed by the unit cell transistor 100 can exhibit good performance. However, the fabrication of the MOSFET can be expensive because it requires growing a first set of semiconductor layers, removing the structure from the growth reactor to form the p-well 130 and the n-type source region 140 via ion implantation, and then placing the structure back into the growth reactor to form the n-type epitaxial pattern 160.

[0074] Figure 2A is a schematic cross-sectional view of a unit cell 200 (and part of two additional unit cells) of another conventional silicon carbide power MOSFET. As shown in Figure 2A, the unit cell transistor 200 includes an n-type silicon carbide semiconductor substrate 210 and a lightly doped n-type (n - ) silicon carbide drift region 220 provided on an upper surface of the substrate 210. An upper portion of the n-type silicon carbide drift region 220 is p-type doped by ion implantation to form p-wells 230, each p-well 230 including a main p-well 232 and a pair of side p-wells 234. A heavily doped (n + ) n-type silicon carbide source region 240 is formed by ion implantation in an upper portion of the p-wells 230. The substrate 210, the drift region 220, the p-wells 230, and the n-source region 240 can together constitute a semiconductor layer structure 250 of the unit cell transistor 200. A gate insulating pattern 270 is formed on the semiconductor layer structure 250. A gate electrode 272 is formed on the gate insulating layer 270. A source contact 280 is formed on the source region 240, and a drain contact 290 is formed on a lower surface of the substrate 210. When a sufficient bias voltage is applied to the gate electrode 272, a channel region 236 is provided in the side p-wells 234, which electrically connects the source region 240 to the drift region 220.

[0075] The unit cell transistor 200 has a similar structure to that of the unit cell transistor 100 of Figure 1A, except that the n-type epitaxial pattern 160 of the unit cell transistor 100 is omitted in the unit cell transistor 200. In addition, the dimensions and doping concentrations of the various regions of the unit cell transistor 200 are different from those of the corresponding regions in the unit cell transistor 100.

[0076] Figure 2B is a graph showing the doping profile of the side p-well 234 of the unit cell transistor 200 as a function of depth from the upper surface of the semiconductor layer structure 250. As shown in Figure 2B, the dopant concentration of the channel region 236 just below the surface of the semiconductor layer structure 250 is approximately 1 x 1014 / cm3. The dopant concentration increases to a peak doping concentration of approximately 1 x 1016 / cm3at a depth of approximately 0.5 microns below the surface of the semiconductor layer structure 250. The dopant concentration then decreases, dropping to 1 x 1014 / cm3at a depth of approximately 0.7 microns. 17 3 19 3 17 3

[0077] ​​​​​​A power MOSFET formed from unit cell transistor 200 can exhibit good performance, but the performance can not be as good as that of a power MOSFET formed from unit cell transistor 100 of FIG. 1A. The power MOSFET formed from unit cell transistor 200 can result in decreased performance because p-well 230 can be formed via a higher energy ion implant process (e.g., implant energy can be approximately 450 keV), which can result in increased damage to semiconductor layer structure 250. Further, the damage to the semiconductor lattice can be immediately under gate insulating layer 270, where the damage can have the greatest impact on device performance. Further, the doping profile of FIG. 2B can not be as good as that of FIG. IB, and can result in corresponding decreased performance. However, the power MOSFET formed from unit cell transistor 200 can be much less expensive to manufacture than the power MOSFET formed from unit cell transistor 100.

[0078] Another potential problem with the power MOSFET formed from unit cell transistor 200, as compared to the power MOSFET formed from unit cell transistor 100, is that it can exhibit decreased "short circuit capability." The "short circuit capability" of a power MOSFET (or other gate-controlled power semiconductor device) refers to the time the device can operate before the device is damaged or destroyed when subjected to a short circuit condition. Under a short circuit condition, the drain current increases dramatically. The high drain current causes a spike in the internal temperature of the device due to the large amount of power dissipated in the semiconductor layer structure when high current passes through the device. How quickly the device heats up under a short circuit condition depends on the heat dissipation characteristics of the device package and the operating conditions. For example, if the power MOSFET formed from unit cell 200 conducts 500 amperes at 1200 volts, the power is 1200 V * 500 A = 60 kilowatts. A power MOSFET with a typical package can have a thermal impedance of, for example, 0.01 °C / W. Thus, for such a MOSFET, operating at 60 kilowatts would heat the device to approximately 600 °C (60 kilowatts * 0.01 °C / W = 600 °C). Typically, a MOSFET can only sustain such temperatures for a very short period of time, such as, for example, 1 microsecond, without failing. In contrast, the same MOSFET can be able to operate at 200 °C for ten hours without failing.

[0079] To protect MOSFETs from such failures, control circuitry can be provided that senses when a short-circuit condition occurs and, in response, reduces the gate voltage (e.g., to 0 volts). Short-circuit conditions are not normal operating conditions and typically occur because a larger system, including the MOSFET, is not operating as intended. However, the short-circuit capability of a MOSFET is critical because, when a short-circuit condition occurs, the control system must be able to quickly turn off the gate voltage to prevent device failure. The shorter the duration of the short-circuit capability, the faster the control circuitry must be able to operate.

[0080] Figure 3A is a schematic cross-sectional view of a unit cell 300 (and portions of two additional unit cells) of another conventional silicon carbide power MOSFET designed to have improved short-circuit performance.

[0081] As shown in Figure 3A, the unit transistor 300 includes an n-type silicon carbide semiconductor substrate 310 and a lightly doped n-type (n... - Silicon carbide drift region 320, lightly doped n-type (n - A silicon carbide drift region 320 is provided on the upper surface of the substrate 310. The upper portion of the n-type silicon carbide drift region 320 is p-type doped by ion implantation to form p-wells 330, each p-well 330 including a main p-well 332 and a pair of side p-wells 334. Heavily doped (n...) + An n-type silicon carbide source region 340 is formed in the upper portion of the p-well 330 by ion implantation. A JFET region 322 is defined between the p-wells 330 in the upper portion of the drift region 320. The substrate 310, the drift region 320 (including the JFET region 322), the p-wells 330, and the source region 340 together constitute the semiconductor layer structure 350 of the unit transistor 300. A gate insulating layer 370 is formed directly on the upper surface of the semiconductor layer structure 350. A gate electrode 372 is formed on the gate insulating layer 370. A source contact 380 is formed on the heavily doped n-type source region 340 and the p-well 330. A drain contact 390 is formed on the lower surface of the substrate 310.

[0082] The p-well 330 is formed via guided ion implantation, which allows for the formation of a deep p-well 330 while using relatively low implantation energy. The use of guided ion implantation also allows the upper portion of the semiconductor layer structure 350 to be lightly doped with p-type, or even remain n-type. The side wells 334 and the main well 332 can have the same or different doping profiles. If different doping profiles are provided, the main well 332 can be more heavily doped than the side well 334. At least the side well 334 is formed using low-energy guided ion implantation. The p-well 330 can have a depth D of 1.5 μm to 6.0 μm or more. Due to the increased depth of the p-well 330, the width W of the JFET region 322 is larger than normal.

[0083] Figure 3B is a graph showing the (p-type dopant) doping profile of the side well 334 of the unit cell transistor 300 as a function of depth D from the top surface of the semiconductor layer structure 350. As shown in Figure 3B, the p-type dopant concentration just below the surface of the side p-well 334 can be very low, less than 1 x 1010 15 / cm 3 The p-type dopant concentration increases sharply throughout the first 0.9 microns, reaching a peak dopant concentration of approximately 8 x 1010 16 / cm 3 at a depth of approximately 0.9 microns from the top surface of the semiconductor layer structure 350. The dopant concentration then decreases very gradually to a dopant concentration of approximately 3 x 1010 16 / cm 3 at a depth of approximately 2.8 microns. The dopant concentration then decreases rapidly, falling below the detection level by a depth of 3.5 microns.

[0084] While the device of Figure 3A can exhibit improved short circuit capability, the device is formed using guided ion implantation, which requires specialized equipment and increases the manufacturing time. In addition, the maximum dopant concentration that can be achieved using guided ion implantation is approximately 1 x 1010 17 / cm 3 which can not be sufficient to deplete the JFET region 322 of the device under short circuit operating conditions. The MOSFET of Figure 3A also has a widened JFET region 322, which reduces the number of unit cells that can be formed in a given area of a wafer.

[0085] In accordance with embodiments of the present application, power MOSFETs and other gate-controlled devices are provided that can exhibit improved short circuit capability while still providing very high levels of performance in terms of blocking voltage, switching time, and on-state resistance. This improved performance can be achieved by forming a relatively deep p-well with a highly doped bottom portion within the semiconductor layer structure of the device using high energy ion implantation. The high level of doping at the bottom of the p-well causes the lower portion of the p-well to laterally expand, thereby reducing the width of at least a portion of the lower portion of the JFET region. The deeper, highly doped p-well and the reduced width of the lower portion of the JFET region increase the size and width of the depletion region formed in the JFET region, thereby providing a better pinch-off effect, which reduces the saturation drain current. The lower saturation current reduces the power dissipation within the device when operated under short circuit conditions, thus reducing the increase in the internal temperature of the device. As a result, the short circuit capability of the device can be improved as compared to conventional devices.

[0086] The narrowing of the lower portion of the JFET region caused by the higher doping level in the lower portion of the p-well acts to increase the specific on-resistance of the device, which is undesirable. To offset the increase in on-resistance, the doping concentration of the JFET region can be increased above the normal level, and the depth of the JFET region can be increased. For example, the JFET region can be at least as deep as the deep p-well. This deeper, higher doped JFET region can mitigate the increase in the specific on-resistance of the device. The deeper, higher doped JFET region can also reduce the specific on-resistance value at high temperature, which helps to reduce the rate at which the internal temperature of the device increases under short circuit conditions (i.e., the device has a smaller temperature coefficient). This can further improve the short circuit capability of the device.

[0087] Furthermore, the narrowing of the lower portion of the JFET region helps to shield the gate electrode from the drain, resulting in a lower intrinsic gate-drain capacitance level of the device. The ratio of the intrinsic gate-source capacitance to the intrinsic gate-drain capacitance is one of the most important factors in reliable high frequency switching performance, so the reduction in intrinsic gate-drain capacitance can improve the performance of the device. Also, the deeper, higher doped p-well increases the size and width of the depletion region formed within the JFET region of the device, which reduces the electric field values in the JFET region and in the gate insulating layer during operation. Since one known failure mechanism of power MOSFETs and other gate-controlled switching devices is the breakdown of the gate insulating layer due to long exposure to high electric fields, the improved shielding can increase the lifetime of the device according to embodiments of the application, and thus increase the reliability of the device.

[0088] According to some embodiments of the application, there is provided a power semiconductor device comprising a semiconductor layer structure, the semiconductor layer structure comprising a silicon carbide drift region having a first conductivity type (e.g., n-type) and a first well and a second well located in an upper portion of the drift region, wherein the first well and the second well are doped with dopants having a second conductivity type (e.g., p-type). A JFET region is defined in the silicon carbide drift region between the first well and the second well. The first well comprises a first main well and a first side well located between the first main well and the JFET region, and the second well comprises a second main well and a second side well located between the second main well and the JFET region.

[0089] The first and second side wells include respective first and second channel regions. The JFET region has a doping concentration that exceeds a doping concentration of the silicon carbide drift region, and a maximum width of an upper portion of the JFET region is greater than a minimum width of a lower portion of the JFET region. In example embodiments, the maximum width of the upper portion of the JFET region can be at least 30%, at least 40%, at least 50%, at least 60%, at least 80%, or at least 100% greater than the minimum width of the lower portion of the JFET region. In such embodiments, the upper portion of the JFET region can be an upper half of the JFET region and the lower portion of the JFET region can be a lower half of the JFET region. For example, the maximum width of the upper half of the JFET region can be between 40% and 80% greater than the minimum width of the lower half of the JFET region. In each of the above embodiments, the maximum width of the upper portion of the JFET region can be less than three times (i.e., 300%) greater than the minimum width of the lower portion of the JFET region.

[0090] In some embodiments, the depth of the JFET region from the upper surface of the semiconductor layer structure can equal or exceed the depth of the first side well from the upper surface of the semiconductor layer structure. In some embodiments, the depth of the first side well from the upper surface of the semiconductor layer structure can be between 1.0 and 1.6 microns. The depth of the JFET region from the upper surface of the semiconductor layer structure can be between 1.0 and 1.2 times the depth of the first side well. For example, the depth of the first side well can be between 1 and 1.5 microns from the upper surface of the semiconductor layer structure, the depth of the JFET region can be between 1 and 1.7 microns, and can be at least as deep as the depth of the first side well. In some embodiments, the JFET region can extend below the side well.

[0091] The peak doping concentration of the first side well can exceed 5 x 1019 17 / cm 3 or even 1 x 1019 18 / cm 3 and in some embodiments can occur at a depth between 0.8 and 1.2 microns below the upper surface of the semiconductor layer structure. Also, the peak doping concentration of an upper 0.2 microns of the first side well can be at least an order of magnitude less than the peak doping concentration of the first side well.

[0092] The width of the lower portion of the JFET region can be less than the depth of the JFET region. In example embodiments, the width of the lower portion of the JFET region can be less than 40% of the depth of the JFET region, less than 50% of the depth of the JFET region, less than 60% of the depth of the JFET region, less than 70% of the depth of the JFET region, or less than 80% of the depth of the JFET region. The width of the upper portion of the JFET region can be greater than or less than the depth of the JFET region. In example embodiments, the width of the upper portion of the JFET region can be between 70% and 130% of the depth of the JFET region, between 80% and 120% of the depth of the JFET region, or between 90% and 110% of the depth of the JFET region.

[0093] Reference will now be made to Figures 4-9F example embodiments of power semiconductor devices according to embodiments of the present application.

[0094] Figure 4 is a schematic plan view of a wafer 400 including a plurality of power MOSFETs 410 according to embodiments of the present application. The power MOSFETs 410 can be formed in rows and columns and can be spaced apart from one another such that the wafer 400 can later be singulated (e.g., diced) to separate individual power MOSFETs 410 for packaging and testing. In some embodiments, the wafer 400 can include, for example, a 4H silicon carbide substrate having one or more silicon carbide layers formed thereon (e.g., by epitaxial growth). Other semiconductor layers (e.g., polysilicon layers), insulating layers, and / or metal layers can be formed on the silicon carbide semiconductor layer structure to form the power MOSFETs 410.

[0095] Figure 5A is a schematic plan view of one of the power MOSFETs 410 on the wafer 400 of Figure 4 . Figure 5B is a schematic plan view of the power MOSFET 410 of Figure 5A , with the source metallization and gate bond pad removed.

[0096] As shown in Figure 5A , a gate bond pad 420 and one or more source bond pads 430-1, 430-2 can be formed on the upper surface of the semiconductor layer structure of the MOSFET 410. A drain bond pad 440 can be provided on the bottom side of the MOSFET 410 (shown by the dotted box in Figure 5A ). Each of the bond pads 420, 430, 440 can be formed of a metal such as aluminum, to which bond wires can be readily attached via conventional techniques such as thermocompression or soldering.

[0097] As will be discussed in more detail below, a source contact is provided that contacts a source region in the semiconductor layer structure of the MOSFET 410. The source contact can be a lower portion of a source metal pattern 432 that extends across most of the upper surface of the MOSFET 410. Because a significant portion of the source metal pattern 432 is covered by the protective layer 450, the source metal pattern 432 is not exposed to the environment in Figure 5A In Figure 5A the source metal pattern 432 is indicated by the dashed boxes. The source bond pads 430-1, 430-2 are portions of the source metal pattern 432 that are exposed through openings 452 in the protective layer 450. Bond wires 460 can be used to connect the gate bond pad 420 and the source bond pads 430-1, 430-2 to external circuitry, etc.

[0098] As shown in Figure 5B , a gate electrode pattern 422 can be provided that includes a gate pad 424, a plurality of gate fingers 426, and one or more gate buses 428 that electrically connect the gate fingers 426 to the gate pad 424. The gate pad 424 can be located directly below the gate bond pad 420 and electrically connected to the gate bond pad 420, and the gate fingers 426 can extend horizontally across the device. An insulating layer (not shown) can cover the gate fingers 426 and the gate bus(es) 428. A source metal pattern 432 can be formed on the insulating layer over the gate fingers 426. The source contact of the source metal pattern 432 extends downward through openings in the insulating layer (not shown) and between the gate fingers 426 to contact corresponding source regions in the semiconductor layer structure. The MOSFET 410 includes a plurality of unit cell transistors 500 arranged in parallel. Figure 5B The location of one unit cell 500 is shown in

[0099] Figure 6A is a schematic plan view of a unit cell transistor 500 of the power MOSFET 410 of Figures 5A-5B . Figure 6B is a schematic cross-sectional view taken along line 6B-6B in Figure 6A . It should be appreciated that Figure 6B illustrates one complete unit cell 500 and portions of two additional unit cells on either side thereof in order to provide context.

[0100] Referring to Figures 6A-6B , the unit cell transistor 500 can be formed on an n-type silicon carbide semiconductor substrate 510, such as, for example, a single-crystal 4H silicon carbide semiconductor substrate heavily doped with n-type impurities. The doping concentration of the substrate 510 can be, for example, in the range of 1 x 1018atoms / cm3and 1 x 1020atoms / cm3. 18 3 21 3 ​​​The doping concentration can be between [specific values], but other doping concentrations can be used. In this document, the “doping concentration” of a semiconductor material refers to the number of dopant atoms present in one cubic centimeter of semiconductor material that give the semiconductor material a specific conductivity type (i.e., n-type or p-type), as measured using standard measurement techniques such as secondary ion mass spectrometry (“SIMS”). For n-type semiconductor materials, the reference to doping concentration refers to the concentration of n-type dopant, while for p-type semiconductor materials, the reference to doping concentration refers to the concentration of p-type dopant. The substrate 510 can have any suitable thickness (e.g., between 100 and 500 micrometers). In some embodiments, the substrate 510 can be partially or completely removed.

[0101] Lightly doped n-type (n) is provided on substrate 510 - The n-type silicon carbide drift region 520 can be formed, for example, by epitaxial growth on a silicon carbide substrate 510. The n-type silicon carbide drift region 520 can have, for example, a size of 1 x 10⁻⁶. 14 Up to 5x10 16 Dopant / cm 3 The doping concentration. The doping concentration can vary with the voltage blocking rating of the device; devices with higher voltage blocking ratings typically have lower doping concentrations in the drift region 520. For example, a MOSFET with a voltage blocking rating of 10kV or higher might have a lower doping concentration in 1x10... 14 Up to 5x10 14 Dopant / cm 3 The doping concentration in the drift region varies, while MOSFETs with a voltage blocking rating of 500V or higher may have a doping concentration in the 1x10 region. 16 Up to 5x10 16 Dopant / cm 3 The doping concentration of the drift region between [specific parameters]. The n-type silicon carbide drift region 520 can be a thick region with a vertical height of, for example, 3-100 micrometers above the substrate 510. Although Figure 6B Not shown, but in some embodiments, the upper portion of the n-type silicon carbide drift region 520 may be more heavily doped than the rest of the drift region 520 to provide a current diffusion layer in the upper portion of the drift region 520. The doping concentration of this current diffusion layer may, for example, be about 1.5 to 4.0 times higher than the doping concentration of the rest of the drift region 520.

[0102] The p-wells 530 are formed in an upper portion of the n-type drift region 520 (or in a current spreading layer, if provided). The JFET regions 522 are defined in the upper portion of the drift region 520 between adjacent p-wells 530. The p-wells 530 can include a main well 532 and side wells 534 located on either side of the main well 532. The main well 532 and the side wells 534 can be doped identically or can be doped differently. A channel region 536 for the unit cell 500 is within the side p-wells 534. The channel region 536 electrically connects the n-type source region 540 (discussed below) to the JFET region 522 when a sufficient bias voltage is applied to the gate electrode 572.

[0103] The p-wells 530 are formed via ion implantation. As is known to those skilled in the art, ions such as n-type or p-type dopants can be implanted into a semiconductor layer or region by ionizing a desired ion species and accelerating the ions as an ion beam toward a surface of a semiconductor layer in an ion implantation target chamber at a predetermined kinetic energy. Based on the predetermined kinetic energy, the desired ion species can penetrate into the semiconductor layer. The ions will be implanted into the semiconductor layer at different depths, such that the predetermined kinetic energy will provide an implant "profile" having a varying ion concentration that varies with depth. The dopants can include, for example, Al + or N + ions, although any appropriate dopant ions can be used. In some embodiments, the implantation can be performed at different temperatures, such as, for example, a temperature of 75 °C or higher.

[0104] Figure 6C is a graph showing an example doping profile of the side well 534. As shown in Figure 6C the surface of the side well 534 is doped to a concentration of approximately 1 x 1019 17 / cm 3 , and the doping concentration generally increases with depth. In the example embodiment shown in Figure 6C , the doping concentration reaches a peak of approximately 5 x 1019 18 / cm 3 at a depth of approximately 1 micron below the surface of the p-well 530. The doping concentration sharply decreases at depths below approximately 1 micron, and is below the background n-type doping concentration level of the upper portion of the drift region 520 at a depth of approximately 1.4 microns.

[0105] Figure 6CThe doping profile shown can be achieved by using ion implantation with higher energies. For example, in the example embodiment, ion implantation can be performed at implantation energies from 500 keV to 2 MeV. These higher implantation energies can be used to dope the lower portion of the side well 534 more heavily than the upper portion of the side well 534, achieving an implantation depth of 1.0 micrometer or more, such that the depth of the side p-well 534 can be between 0.8 and 2.0 micrometers in the example embodiment, between 1.0 and 1.7 micrometers in other example embodiments, and between 1.1 and 1.5 micrometers in yet other example embodiments. In some embodiments, the peak doping concentration of the side well 534 can be 8 x 10⁻⁶. 17 Up to 1x10 19 Dopant / cm 3 Between, and in other example embodiments can be 1x10 18 Up to 8x10 18 Dopant / cm 3 In some embodiments, the peak doping concentration may occur at a depth between 0.7 and 1.5 micrometers below the top surface of the semiconductor layer structure 550, and in other embodiments it may occur at a depth between 0.8 and 1.2 micrometers.

[0106] It should be recognized that a multi-step ion implantation process can be used to form the p-well 530. For example, in a first ion implantation step, a relatively low dose of aluminum ions can be implanted at a relatively low implantation energy level. In a second ion implantation step, a moderate dose of aluminum ions can be implanted at a moderate implantation energy level. In a third ion implantation step, a high dose of aluminum ions can be implanted at a high implantation energy level. In some embodiments, the high dose of aluminum ions can be at least one order of magnitude larger than the low dose of aluminum ions, or at least two orders of magnitude larger. In some embodiments, the high dose of aluminum ions can be at least one order of magnitude larger than the moderate dose of aluminum ions. In some embodiments, the high dose of aluminum ions can be implanted using an implantation energy at least two or at least three times that used for implanting the moderate dose of aluminum ions. In some embodiments, the high dose of aluminum ions can be implanted using an implantation energy at least four, at least five, at least six, at least seven, or at least eight times that used for implanting the low dose of aluminum ions. Ions other than aluminum can also be used.

[0107] As in Figure 6BAs is best observed, the higher doping concentration in the bottom portion of the side well 534 causes the side p-well 534 to extend laterally. Therefore, the upper portion of the JFET region 522 defined between the p-wells 530 is at least partially wider than the lower portion of the JFET region 522. In this document, the upper portion of the JFET region 522 refers to the upper half of the JFET region 522, while the lower portion of the JFET region 522 refers to the lower half of the JFET region 522. For example, as... Figure 6B As shown, the upper portion of the JFET region 522 has a first maximum width W1. Although the width of the upper portion of the JFET region 522 is... Figure 6B The width is represented as constant, but in actual devices, it typically varies, and the width W1 is the maximum width of the upper portion of the JFET region 522. The lower portion of the JFET region 522 has a variable width, and the minimum width W2 of the lower portion of the JFET region 522 is less than the maximum width W1 of the upper portion of the JFET region 522. In some embodiments, the maximum width W1 of the upper portion of the JFET region 522 can be between 0.8 and 3.0 micrometers. In other embodiments, the maximum width W1 of the upper portion of the JFET region 522 can be between 1.0 and 2.0 micrometers. In still other embodiments, the maximum width W1 of the upper portion of the JFET region 522 can be between 1.0 and 1.5 micrometers. In some embodiments, the minimum width W2 of the lower portion of the JFET region 522 can be between 0.4 and 1.5 micrometers. In other embodiments, the minimum width W2 of the lower portion of the JFET region 522 can be between 0.5 and 1.0 micrometers or between 0.5 and 0.75 micrometers. In some embodiments, the width W2 can be between 30% and 80% of the width W1. In other embodiments, the width W2 can be between 40% and 60% of the width W1. In some embodiments, the minimum width of the lower half of the JFET region 522 can be between 35% and 90% of the average width of the upper half of the JFET region 522, or between 45% and 65% of the average width of the upper half of the JFET region 522.

[0108] As discussed above, the narrowing region in the lower portion of the JFET region 522 can increase the specific on-resistance of the device including unit cell 500. To offset the increase in on-resistance, a deeper JFET region 522 is provided within the device, wherein the JFET region 522 can be at least as deep as the side p-well 534. Additionally or alternatively, the doping concentration of the JFET region 522 can be increased to a higher level than usual. A deeper, more heavily doped JFET region 522 can also reduce the value of the specific on-resistance at high temperatures, which helps to reduce the rate of increase in the internal temperature of the device under short-circuit conditions (i.e., the device has a smaller temperature coefficient). This can also improve the short-circuit capability of the device. In some embodiments, the deeper, more heavily doped JFET region 522 can be formed by ion implantation. Figure 6B The illustration shows an embodiment in which the depth of the JFET region 522 is approximately the same as the depth of the p-well 530. Figure 6E A modified version 500' of unit cell 500 is shown, which includes a JFET region 522' having a depth approximately 20% deeper than the p-well 530. Figure 6E An embodiment can be formed by forming the JFET region 522 by ion implantation before forming the p-well 530 by ion implantation.

[0109] Figure 6D This is a graph showing an example doped profile of region 522 in the JFET. (Example) Figure 6D As shown, the additional n-type dopant (e.g., nitrogen ions) is approximately 6 x 10⁻⁶. 16 / cm 3 The concentration was injected into the JFET region 522. Figure 6D In the example, a total of six ion implantation steps are performed to dope the JFET region 522, each step with a different implantation energy, which results in Figure 6D The six peaks shown. Injected nitrogen ions tend to deflect less within the semiconductor lattice than aluminum ions, therefore in… Figure 6D In the example embodiment, more implantation steps are used to obtain a fairly constant doping profile throughout the JFET region 522. In this example, the background n-type doping concentration in the drift region 520 is approximately 2 x 10⁻⁶. 16 / cm 3 This results in the JFET region 522 having a doping concentration 2-3 times higher than the background doping concentration. The doping concentration drops sharply below a depth of approximately 1.25 micrometers and falls below the background n-type doping concentration level at a depth of approximately 1.35 micrometers. This can be compared to... Figure 6C and 6DAs can be seen, the depth of the JFET region 522 is approximately equal to the depth of the side p-well 534. The depth of a region formed by ion implantation, such as the p-well 530 (or portions thereof) or the JFET region 522, refers to the depth below the surface of the region (or another reference surface) at which the doping concentration falls to a level equal to the background doping concentration. The background doping concentration can be of the same conductivity type or a different conductivity type.

[0110] In some embodiments, the depth of the JFET region 522 can be between 0.8 and 1.5 times the depth of the side p-well 534. In some embodiments, the depth of the JFET region 522 can be between 1.0 and 1.4 times the depth of the side p-well 534. In still other embodiments, the depth of the JFET region 522 can be between 1.0 and 1.2 times the depth of the side p-well 534. In some embodiments, the depth of the JFET region 522 can be between 0.8 and 2.0 microns. In other embodiments, the depth of the JFET region 522 can be between 1.0 and 1.7 microns.

[0111] The width of the lower portion of the JFET region can be less than the depth of the JFET region 522. In example embodiments, the width of the lower portion of the JFET region 522 can be less than 40% of the depth of the JFET region 522, less than 50% of the depth of the JFET region 522, less than 60% of the depth of the JFET region 522, less than 70% of the depth of the JFET region 522, or less than 80% of the depth of the JFET region 522. The width of the upper portion of the JFET region 522 can be greater than or less than the depth of the JFET region 522. In example embodiments, the width of the upper portion of the JFET region 522 can be between 70% and 130% of the depth of the JFET region 522, between 80% and 120% of the depth of the JFET region 522, or between 90% and 110% of the depth of the JFET region 522.

[0112] The main well 532 and the side well 534 can be formed in the same process and can have the same p-type doping concentration that varies with depth. However, it should be appreciated that in other embodiments, the main well 532 and the side well 534 can be formed to have different doping profiles. For example, an additional shallow ion implantation can be performed to increase the p-type dopant concentration in the upper portion of the main well 532 to between 5xlO 18 / cm 3 and 5xlO 19 / cm 3 .

[0113] After the p-well 530 is formed, a heavily doped (n +The n-type silicon carbide source region 540 can be formed by ion implantation. The substrate 510, the drift region 520 (including the JFET region 522 and any current diffusion layer), the p-well 530 and the source region 540 together constitute the semiconductor layer structure 550.

[0114] The ion implantation steps for forming the p-well 530, JFET region 522, and source region 540 can be performed in any suitable order. For example, ion implantation into the JFET region 522 can occur before or after the formation of the p-well 530. Typically, the p-well 530 is heavily doped (n... + The n-type silicon carbide source region is formed before 540, but this is not necessary.

[0115] After forming the n-type source region 540, a gate insulating layer 570 can be formed on the upper surface of the semiconductor layer structure 550. The gate insulating layer 570 can be formed directly on the semiconductor layer structure 550 without an intermediate n-type epitaxial layer. The gate insulating layer 570 may include, for example, a silicon oxide layer, but other insulating materials can be used. A gate electrode 572 is formed on the gate insulating layer 570. The gate electrode 572 may include, for example, a conductive gate finger used as the gate electrode for a plurality of unit cell transistors 500.

[0116] Source contact 580 may be formed on heavily doped n-type source region 540 and well region 530. Although not shown for simplicity of drawing, source contact 580 may be part of a continuous source pattern 432 extending across the upper surface of the silicon carbide semiconductor layer structure of MOSFET 410 (see [reference]). Figure 5A The source contact 580 may include, for example, a metal (such as nickel, titanium, tungsten, and / or aluminum), and / or an alloy and / or thin-layer stack of these and / or similar materials. The drain contact 590 may be formed on the lower surface of the substrate 510. The drain contact 590 may include, for example, a material similar to that of the source contact, as this forms an ohmic contact to the silicon carbide substrate.

[0117] At least a portion of the lower portion of the deep, highly doped p-well 530 and JFET region 522 can provide enhanced shielding compared to conventional devices. This enhanced shielding can reduce the electric field values in the JFET region 522 and gate insulating layer 570 during on-state operation. Since one known failure mechanism for power MOSFETs and other gate-controlled switching devices is breakdown of the gate insulating layer 570 due to prolonged exposure to high electric fields, the improved shielding increases the lifetime of the device according to embodiments of the present application, thereby increasing the reliability of the device. In addition, the enhanced shielding helps to shield the gate electrode 572 from the drain contact 590, resulting in a lower intrinsic gate-drain capacitance level for the device, which can improve the high frequency switching performance of the device including the unit cell 500.

[0118] The reduced width of the lower portion of the JFET region 522 increases the size of the depletion region when the device is operated under short circuit conditions, which improves the pinch-off effect, thereby reducing the level of the saturated drain current. Thus, the short circuit capability of the device can be improved compared to conventional devices. The increased depth and doping concentration of the JFET region 522 can help to offset any increase in the specific on-resistance of the device that can occur as a result of providing a deeper, more highly doped side p-well 534. The deeper, more highly doped JFET region 522 can also reduce the value of the specific on-resistance at high temperatures, which helps to reduce the rate of internal temperature increase of the device under short circuit conditions (i.e., the device has a smaller temperature coefficient). This can further improve the short circuit capability of the device.

[0119] While the unit cell transistor 500 is an n-type device in which the source contact 580 is located on its upper surface and the drain contact 590 is located on its bottom surface, it should be recognized that in a p-type device, these locations are reversed. Thus, in portions of the following description (including the claims), the source and drain contacts can be referred to collectively as "source / drain contacts," which term generally refers to either the source contact or the drain contact.

[0120] In the above example unit cell 500, the doping concentration of the JFET region 522 can exceed the doping concentration of the silicon carbide drift region 520. The minimum width Wl of the upper portion of the JFET region 522 can be greater than the minimum width W2 of the lower portion of the JFET region 522. The depth of the first side well 534 can be at least 1.0 microns and the depth of the JFET region 522 can equal or exceed the depth of the first side well 534 (e.g., the depth of the JFET region 522 can be between 1.0 and 1.2 times the depth of the first side well 534). For example, the depth of the first side well 534 can be between 1 and 1.5 microns and the depth of the JFET region 522 can be between 1 and 1.7 microns and can equal or exceed the depth of the first side well 534. In some embodiments, the minimum width Wl of the upper portion of the JFET region 522 can be at least 50% greater than the minimum width W2 of the lower portion of the JFET region 522.

[0121] The peak doping concentration of the first side well 534 can exceed 5 x 1019 17 / cm 3 and can occur at a depth between 0.8 and 1.2 microns below the upper surface of the semiconductor layer structure 550. Additionally, the upper 0.2 microns of the first side well 534 can have a peak doping concentration that is at least an order of magnitude less than the peak doping concentration of the first side well 534. The peak doping concentration of the first side well 534 can occur at a first depth from the upper surface of the semiconductor layer structure 550 and at the first depth the doping concentration of the JFET region 522 can be at least an order of magnitude less than the peak doping concentration of the first side well 534.

[0122] Figure 7 is a circuit diagram illustrating a MOSFET under short circuit conditions. As shown in Figure 7 , a power MOSFET can have its source terminal coupled to ground and a high direct current (DC) voltage (V DC ) applied to the drain terminal. As an example, the value of V DC may be 800 volts or some other higher value. If under these conditions, a voltage V g exceeding the threshold voltage for the device is applied to the gate electrode, the device begins to conduct and the drain current rapidly increases due to the large voltage difference between the source and drain terminals. As described above, the power dissipation within the device structure increases with the increase in drain current, rapidly heating the device and typically leading to a permanent device failure if the short circuit conditions are not quickly corrected.

[0123] Figure 8is a plot illustrating simulated drain current and lattice temperature as a function of time for a conventional MOSFET (curves 600 and 602) and a MOSFET according to an embodiment of the application (curves 610 and 612). As shown by curve 600, the drain current in the conventional device rises rapidly to approximately 1050 amperes, and then falls as the pinch-off effect due to depletion in the JFET region causes the drain current to saturate. As shown by curve 602, the temperature within the conventional MOSFET increases to almost 2000 K within 3 x 10 -6 seconds of the short condition occurring. In contrast, as shown by curve 610, the drain current in the MOSFET according to an embodiment of the application rises to only approximately 675 amperes, and then falls as the drain current saturates, and the temperature within the device (curve 612) increases to only approximately 1500 K within 3 x 10 -6 seconds of the short condition occurring. This indicates that the semiconductor device according to an embodiment of the application can exhibit improved short circuit capability.

[0124] Figures 9A-9F is a schematic cross-sectional view illustrating a method of fabricating a power MOSFET according to an embodiment of the application. As shown in Figure 9A , a lightly doped n-type (n - ) silicon carbide drift region 520 can be formed on a substrate 510. The substrate 510 can be a silicon carbide semiconductor substrate 510, such as a single crystal 4H silicon carbide semiconductor substrate heavily doped with n-type impurities. The n-type silicon carbide drift region 520 can be formed by epitaxial growth and can have a doping concentration of, for example, 1 x 10 14 to 5 x 10 16 dopants / cm 3 . An upper portion (e.g., top 2-3 microns) of the n-type silicon carbide drift region 520 can be more heavily doped than the rest of the drift region 520 to form a current spreading layer in the upper portion of the drift region 520.

[0125] As shown in Figure 9B , a p-well 530 is formed in the upper portion of the n-type drift region 520 by ion implantation. A mask 521 (e.g., thick oxide layer) is formed on the upper surface of the drift region 520. P-type dopants are then implanted by ion implantation using the mask 521 as an ion implantation mask. A multi-step implant can be used to achieve the desired doping profile. For example, a low energy implant (e.g., 1 x 10 12 at 50 keV) at a low dose can be used to form an upper portion of the p-well 530, and then a medium energy implant (e.g., 2 x 10 12This is used to form the middle portion (in the depth direction) of the p-well 530. High-dose, high-energy injection (e.g., 1x10 at 500 keV) can be used. 14 This forms the lower portion of the p-well 530. For example... Figure 9B As shown, due to scattering effects, the p-well 530 will extend laterally beyond the opening formed in the mask 521. The lower portion of the p-well 530, which is more heavily doped, can extend laterally further than the middle and upper regions of the p-well 530, which are less heavily doped. Although not shown in the figure, mask 521 can be removed and replaced with a second mask having a narrower opening, and additional high-dose low-energy implantation (e.g., 1x10 at 50 keV) can be used. 14 This significantly increases the doping concentration of the upper portion of the main p-well 532 without affecting the doping concentration of the side p-well 534.

[0126] like Figure 9C As shown, one or more ion implantation masks used to form p-well 530 are removed and replaced with mask 523, which exposes the portion of drift region 520 between p-wells 530. Then, n-type dopant is implanted into this region using mask 523 as an ion implantation mask. Again, a multi-step ion implantation process (e.g., 3-10 steps) can be used. The ion implantation steps can use different but relatively similar doses of implantation energy to provide implantation that increases the concentration of n-type dopant in the portion of drift region 520 between p-wells 530 to form JFET region 522. As mentioned above, the depth of JFET region 522 can be equal to or greater than the depth of p-well 530.

[0127] like Figure 9D As shown, the ion implantation mask used to form the JFET region 522 is removed and replaced with mask 541, which exposes selected portions of the main p-well 532. Then, n-type dopant is implanted into these regions using mask 541 as an ion implantation mask. Finally, as... Figure 9E and 9F As shown, a gate insulating layer 570, a gate electrode 572, and source and drain contacts 580 and 590 can be formed to complete the device.

[0128] While the above discussion focuses on n-channel MOSFETs, it should be recognized that, according to other embodiments of the invention, the polarity of each semiconductor layer in each device can be reversed to provide a corresponding p-channel MOSFET. Similarly, although the embodiments of the invention discussed above are MOSFETs, it should be recognized that the techniques disclosed herein can also be used to form insulated-gate bipolar junction transistors (IGBTs) including MOSFETs according to embodiments of the invention, or other gate-controlled power semiconductor devices.

[0129] While in the above embodiments, the JFET region 522 is formed via ion implantation, it should be recognized that in other embodiments, the JFET region 522 can be formed by a more highly doped upper portion of the drift region 520, which can eliminate the need for an additional ion implantation step. However, if the more highly doped JFET region 522 is formed during growth of the drift region 520, care can be needed to ensure that the high electric field at the edge termination of the device does not degrade the blocking characteristics of the device.

[0130] In this document, embodiments of the application are described in relation to cross-sectional views showing one or two unit cells of a power switching device. It will be recognized that practical implementations will typically include a larger number of unit cells. However, it will also be recognized that the application is not limited to such devices, and that the appended claims also cover MOSFETs and other power switching devices including, for example, a single unit cell. Also, while the present disclosure focuses on silicon carbide devices, it will be recognized that embodiments of the application can also be applicable to devices formed using other wide bandgap semiconductors such as, for example, gallium nitride, zinc selenide, or any other II-VI or III-V wide bandgap compound semiconductor.

[0131] The application has been described above with reference to drawings, in which embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments were provided so that this disclosure is thorough and complete, and fully conveys the scope of the application to those skilled in the art. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, connected or coupled to, the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Like reference numerals refer to like elements throughout.

[0132] It will be understood that, although the terms first and second are used herein to describe various regions, layers and / or elements, these regions, layers and / or elements should not be limited by these terms. These terms are only used to distinguish one region, layer or element from another region, layer or element. Thus, a first region, layer or element discussed below could be termed a second region, layer or element and, similarly, a second region, layer or element could be termed a first region, layer or element without departing from the scope of the application.

[0133] Relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on the "upper" sides of the other elements. The exemplary term "lower" can therefore encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary terms "below" or "beneath" can, therefore, encompass both an orientation of "below" and "above," depending on the particular orientation of the figure.

[0134] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, elements and / or components, but do not preclude the presence or addition of one or more other features, elements, components and / or groups thereof.

[0135] Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of specific embodiments of the present application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present application.

[0136] It will be appreciated that embodiments disclosed herein can be combined. Thus, features depicted and / or described in relation to a first embodiment can equally be included in a second embodiment, and vice versa.

[0137] While the above-mentioned embodiments have been described with reference to particular drawings, it will be understood that some embodiments of the application can include additional and / or intervening layers, structures or elements, and / or particular layers, structures or elements can be deleted. Although several exemplary embodiments of the application have been described, it will be appreciated that those skilled in the art upon considering this drawing and description will readily ascertain many modifications, both to the number of steps described and to the order of steps. Accordingly, all such modifications are intended to be included within the scope of the application as defined in the following claims. Hence, it is to be understood that the foregoing is a description of only some embodiments of the application and is not to be construed as limiting the application, and that modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the application. The application is defined by the following claims, including equivalents of the claims.

Claims

1. A power semiconductor device, comprising: Semiconductor layer structure, including: The silicon carbide drift region has a first type of conductivity. The first well is located in the upper part of the silicon carbide drift region and is doped with a dopant having a second conductivity type different from the first conductivity type. The second well is located in the upper part of the silicon carbide drift region, the second well is spaced apart from the first well, and is doped with a dopant having a second conductivity type; The doping concentration of the first conductivity type dopant in the JFET region exceeds the doping concentration of the first conductivity type dopant in the silicon carbide drift region. The JFET region is at least partially located between the first and second wells and has a JFET depth defined from the upper surface of the semiconductor layer structure; and The maximum width of the upper half of the JFET region is at least 30% larger than the minimum width of the lower half of the JFET region, and The minimum width of the lower half of the JFET region is less than 50% of the JFET depth.

2. The power semiconductor device of claim 1, wherein the first well includes a first main well and a first side well located between the first main well and the JFET region, the first side well including a first channel region. The second well includes a second main well and a second side well located between the second main well and the JFET region. The second side well includes a second channel region.

3. The power semiconductor device of claim 2, wherein the depth of the first side well from the upper surface of the semiconductor layer structure is at least 1.0 micrometers and the JFET depth is between 1.0 and 1.7 micrometers.

4. The power semiconductor device of claim 3, further comprising: The first source / drain contact is on the lower surface of the silicon carbide drift region; A source / drain region having a first conductivity type is located in the upper portion of the first main well and extends to the upper surface of the first well; The second source / drain contact is on the upper surface of the source / drain region; Gate insulating layer, on the JFET region and on the first well; as well as The gate electrode is located on the gate insulating layer.

5. The power semiconductor device according to any one of claims 2-4, wherein the JFET depth is equal to or greater than the depth of the first side well from the upper surface of the semiconductor layer structure.

6. The power semiconductor device according to any one of claims 2-4, wherein the peak doping concentration of the first sidewell exceeds 5 x 10⁻⁶. 17 / cm 3 It appears at a depth between 0.8 and 1.2 micrometers below the upper surface of the semiconductor layer structure.

7. The power semiconductor device according to any one of claims 2-4, wherein the depth of the first side well from the upper surface of the semiconductor layer structure is less than 1.6 micrometers.

8. The power semiconductor device according to any one of claims 2-4, wherein the JFET depth is between 1.0 and 1.2 times the depth of the first side well from the upper surface of the semiconductor layer structure.

9. The power semiconductor device according to any one of claims 2-4, wherein the peak doping concentration of the upper 0.2 micrometer of the first sidewell is at least one order of magnitude smaller than the peak doping concentration of the first sidewell.

10. The power semiconductor device according to any one of claims 1-4, wherein the maximum width of the upper half of the JFET region is at least 50% greater than the minimum width of the lower half of the JFET region.

11. The power semiconductor device of claim 2, wherein the peak doping concentration of the first sidewell occurs at a first depth from the upper surface of the semiconductor layer structure, and wherein the doping concentration of the JFET region at the first depth from the upper surface of the semiconductor layer structure is at least one order of magnitude lower than the peak doping concentration of the first sidewell.

12. The power semiconductor device according to any one of claims 2-4, wherein the depth of the first side well is between 1.0 and 1.5 micrometers from the upper surface of the semiconductor layer structure, the depth of the JFET is between 1.0 and 1.7 micrometers, and the depth of the JFET is at least as deep as the depth of the first side well.

13. The power semiconductor device according to any one of claims 2-4, wherein the distance between the first side well and the second side well is less than 1.5 micrometers.

14. The power semiconductor device of any one of claims 1-4, wherein the JFET region includes an implantation region implanted with a dopant having a first conductivity type.

15. The power semiconductor device according to any one of claims 1-4, wherein the maximum width of the upper half of the JFET region is between 40% and 80% greater than the minimum width of the lower half of the JFET region.

16. The power semiconductor device according to any one of claims 1-4, wherein the JFET region extends below the first well.

17. The power semiconductor device of claim 1, wherein the maximum distance between the first well and the second well in the upper half of the JFET region is greater than the minimum distance between the first well and the second well in the lower half of the JFET region.

18. The power semiconductor device of claim 2, wherein the depth of the first sidewell is between 1.0 and 1.7 micrometers, and the peak doping concentration of the first sidewell is 8 × 10⁻⁶. 17 / cm 3 With 1×10 19 / cm 3 It appears between 0.7 micrometers and 1.5 micrometers in depth.

19. A power semiconductor device, comprising: Semiconductor layer structure, including: The silicon carbide drift region has a first type of conductivity. A first well is located in the upper portion of the silicon carbide drift region. The first well is doped with a dopant having a second conductivity type different from the first conductivity type. The first well includes a first channel region. A second well, located in the upper portion of the silicon carbide drift region, is spaced apart from the first well to define a JFET region of the silicon carbide drift region. The second well is doped with a dopant having a second conductivity type and includes a second channel region. First source / drain contact on the lower surface of the silicon carbide drift region; The second source / drain contacts are located on the upper surface of the silicon carbide drift region, opposite the lower surface of the silicon carbide drift region. The maximum distance between the first and second wells in the upper half of the JFET region is greater than the minimum distance between the first and second wells in the lower half of the JFET region. The doping concentration of the JFET region exceeds the doping concentration of the silicon carbide drift region, and the depth of the first well from the upper surface of the semiconductor layer structure is at least 1.0 micrometers, and the peak doping concentration of the first well exceeds the doping concentration of the first well at a depth of 0.2 micrometers from the upper surface of the semiconductor layer structure by at least one order of magnitude.

20. The power semiconductor device of claim 19, wherein the depth of the JFET region from the upper surface of the semiconductor layer structure exceeds the depth of the first well from the upper surface of the semiconductor layer structure.

21. The power semiconductor device of claim 19, wherein the peak doping concentration of the first well exceeds 5 x 10⁻⁶. 17 / cm 3 It appears at a depth between 0.8 and 1.2 micrometers below the upper surface of the semiconductor layer structure.

22. The power semiconductor device of claim 19, wherein the depth of the first well from the upper surface of the semiconductor layer structure is between 1.0 and 1.6 micrometers.

23. The power semiconductor device of claim 19, wherein the depth of the JFET region from the upper surface of the semiconductor layer structure is less than 1.2 times the depth of the first well from the upper surface of the semiconductor layer structure.

24. The power semiconductor device according to any one of claims 19-21, wherein the maximum width of the upper half of the JFET region is at least 50% greater than the minimum width of the lower half of the JFET region.

25. The power semiconductor device of any one of claims 19-21, wherein the peak doping concentration of the first well occurs at a first depth from the upper surface of the semiconductor layer structure, and wherein the doping concentration of the JFET region at the first depth from the upper surface of the semiconductor layer structure is at least one order of magnitude lower than the peak doping concentration of the first well.

26. The power semiconductor device of claim 19, wherein the maximum width of the upper half of the JFET region is between 40% and 80% greater than the minimum width of the lower half of the JFET region.

27. The power semiconductor device according to any one of claims 19-21, wherein the JFET region extends below the first well.

28. A power semiconductor device, comprising: Semiconductor layer structure, including: The silicon carbide drift region has a first type of conductivity. A first well is located in the upper portion of the silicon carbide drift region. The first well is doped with a dopant having a second conductivity type different from the first conductivity type. The first well includes a first channel region. A second well, located in the upper portion of the silicon carbide drift region, is spaced apart from the first well. The second well is doped with a dopant having a second conductivity type and includes a second channel region. The JFET region, located between the first and second wells in the silicon carbide drift region, has a doping concentration exceeding that of the silicon carbide drift region. The peak doping concentration of the first well occurs at a first depth from the upper surface of the semiconductor layer structure, and the doping concentration of the JFET region at the first depth is at least an order of magnitude lower than the peak doping concentration of the first well. The maximum width of the upper half of the JFET region is at least 30% larger than the minimum width of the lower half of the JFET region. The minimum width of the lower half of the JFET region is between 0.5 and 1.0 micrometers, and the depth of the JFET region is between 1.0 and 1.7 micrometers from the upper surface of the semiconductor layer structure.

29. The power semiconductor device of claim 28, wherein the peak doping concentration of the first well exceeds 5 x 10⁻⁶. 17 / cm 3 It appears at a depth between 0.7 and 1.2 micrometers below the upper surface of the semiconductor layer structure.

30. The power semiconductor device according to any one of claims 28-29, wherein the depth of the JFET region from the upper surface of the semiconductor layer structure is less than 1.2 times the depth of the first well from the upper surface of the semiconductor layer structure.

31. The power semiconductor device according to any one of claims 28-29, wherein the peak doping concentration of the upper 0.2 micrometer of the first well is at least one order of magnitude smaller than the peak doping concentration of the first well.

32. The power semiconductor device according to any one of claims 28-29, wherein the maximum width of the upper half of the JFET region is at least 50% greater than the minimum width of the lower half of the JFET region.

33. The power semiconductor device of any one of claims 28-29, wherein the JFET region includes an implantation region implanted with a dopant of a first conductivity type.

34. The power semiconductor device of claim 28, wherein the JFET region extends below the first well.

35. The power semiconductor device of claim 28, wherein the depth of the JFET region from the upper surface of the semiconductor layer structure exceeds the depth of the first well from the upper surface of the semiconductor layer structure.

36. The power semiconductor device of claim 28, wherein the maximum distance between the first well and the second well in the upper half of the JFET region is greater than the minimum distance between the first well and the second well in the lower half of the JFET region.

37. A method of forming a power semiconductor device, the method comprising: Provides a silicon carbide drift region having a first conductivity type; A second conductivity type dopant is implanted into the upper portion of the silicon carbide drift region to form a first well and a second well; as well as A first conductivity type dopant is implanted into the upper portion of a silicon carbide drift region between a first well and a second well via ion implantation to form a JFET region between the first well and the second well, wherein the silicon carbide drift region and the first and second wells are parts of a semiconductor layer structure. The maximum width of the upper half of the JFET region is at least 30% larger than the minimum width of the lower half of the JFET region, and The minimum width of the lower half of the JFET region is less than 50% of the JFET depth.

38. The method of claim 37, wherein the first well includes a first main well and a first side well located between the first main well and the JFET region, the first side well including a first channel region, and the second well includes a second main well and a second side well located between the second main well and the JFET region, the second side well including a second channel region, and wherein the first side well is at a depth of at least 1.0 micrometer from the upper surface of the semiconductor layer structure.

39. The method of claim 38, further comprising: A first source / drain contact is formed on the lower surface of the silicon carbide drift region; A source / drain region having a first conductivity type is formed in the upper portion of the first main well; A second source / drain contact is formed on the upper surface of the source / drain region; A gate insulating layer is formed on the JFET region and on the first well; as well as A gate electrode is formed on the gate insulating layer.

40. The method of claim 39, wherein the depth of the JFET region from the upper surface of the semiconductor layer structure is equal to or greater than the depth of the first side well from the upper surface of the semiconductor layer structure.

41. The method of any one of claims 38-40, wherein the peak doping concentration of the first sidewell exceeds 5 x 10⁻⁶. 17 / cm 3 It appears at a depth between 0.8 and 1.2 micrometers below the upper surface of the semiconductor layer structure.

42. The method of claim 41, wherein the depth of the JFET region from the upper surface of the semiconductor layer structure is between 1.0 and 1.2 times the depth of the first side well from the upper surface of the semiconductor layer structure.

43. The method of any one of claims 38-40, wherein the peak doping concentration of the upper 0.2 micrometer of the first sidewell is at least one order of magnitude smaller than the peak doping concentration of the first sidewell.

44. The method of any one of claims 37-40, wherein the JFET region is formed prior to the formation of the first well and the second well.

45. The method of any one of claims 37-40, wherein the JFET region extends below the first and second wells.

46. ​​A power semiconductor device, comprising: Semiconductor layer structure, including: The silicon carbide drift region has a first type of conductivity. The first well is located in the upper part of the silicon carbide drift region. The first well is doped with a dopant having a second conductivity type different from the first conductivity type. The first well includes a first side well region. The second well is located in the upper part of the silicon carbide drift region. The second well is spaced apart from the first well. The second well is doped with a dopant having a second conductivity type. The second well includes a second side well region. In the JFET region, in the silicon carbide drift region between the first well and the second well, the doping concentration of the dopant of the JFET region having a first conductivity type exceeds the doping concentration of the silicon carbide drift region; The peak doping concentration of the first sidewell region appears at a first depth from the upper surface of the semiconductor layer structure, and the doping concentration of the JFET region at the first depth is at least one order of magnitude lower than the peak doping concentration of the first sidewell region. The depth of the first side well is between 1.0 and 1.7 micrometers, and the peak doping concentration of the first side well is 8 × 10⁻⁶. 17 / cm 3 and 1×10 19 / cm 3 It appears between 0.7 micrometers and 1.5 micrometers in depth.

47. A power semiconductor device, comprising: Semiconductor layer structure, including: The silicon carbide drift region has a first type of conductivity. A first well, located in the upper portion of a silicon carbide drift region, is doped with a dopant having a second conductivity type different from a first conductivity type, and the first well includes a first sidewell region; and The second well, located in the upper portion of the silicon carbide drift region, is spaced apart from the first well to define the JFET region of the silicon carbide drift region. The JFET region lies between the first well and the second well. The second well is doped with a dopant having the second conductivity type. The maximum distance between the first well and the second well in the upper half of the JFET region is greater than the minimum distance between the first well and the second well in the lower half of the JFET region. The depth of the first side well is between 1.0 and 1.7 micrometers, and the peak doping concentration of the first side well is 8 × 10⁻⁶. 17 / cm 3 With 1×10 19 / cm 3 It appears between 0.7 micrometers and 1.5 micrometers in depth.

48. The power semiconductor device of claim 47, wherein the maximum width of the upper half of the JFET region is at least 30% greater than the minimum width of the lower half of the JFET region, the minimum width of the lower half of the JFET region is between 0.5 and 1.0 micrometers, and the depth of the JFET region is between 1.0 and 1.7 micrometers from the upper surface of the semiconductor layer structure.

49. The power semiconductor device of claim 47, wherein the peak doping concentration of the first well exceeds the doping concentration of the first well at a depth of 0.2 micrometers from the upper surface of the semiconductor layer structure by at least one order of magnitude.

50. The power semiconductor device of claim 49, wherein the first well includes a first channel region and the second well includes a second channel region, the semiconductor layer structure further comprising: First source / drain contact on the lower surface of the silicon carbide drift region; as well as The second source / drain contacts are located on the upper surface of the silicon carbide drift region, opposite the lower surface of the silicon carbide drift region.

Images