Silicon carbide semiconductor device and power conversion device

Abstract

The silicon carbide semiconductor device of the present invention comprises a dummy sensing region (103) formed between an active region (101) and an active sensing region (102), and has a drift layer of a first conductivity type. In the active region (101), an SBD built-in MOSFET including a first well region (30) of a second conductivity type connected to a source electrode is formed. In the active sensing region (102), an SBD built-in MOSFET including a second well region (31) of a second conductivity type connected to a sensing pad (83) is formed. In the dummy sensing region (103), a third well region (32) of a second conductivity type which is not ohmically connected to either the source electrode (81) or the sensing pad (83) is formed on the upper layer of the n-type drift layer (20). The gate electrodes (60) of the SBD built-in MOSFET in the active region (101) and the SBD built-in MOSFET in the active sensing region (102) are connected to the gate pad (82).

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device and a power conversion device composed of silicon carbide. Background Art

[0002] Regarding pn diodes made of silicon carbide (SiC), it is known that when a forward current, i.e., a bipolar current, continues to flow, stacking defects occur in the crystal and the forward voltage shifts. This is known to be a reliability problem. It is believed that the reason is that due to the recombination energy when the minority carriers injected through the pn diode recombine with the majority carriers, stacking defects as surface defects expand starting from the basal plane dislocations existing in the silicon carbide substrate. This stacking defect hinders the flow of current, so due to the expansion of the stacking defect, the current decreases and the forward voltage increases, causing the reliability of the semiconductor device to decrease.

[0003] Such an increase in forward voltage also occurs in vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) using silicon carbide. Vertical MOSFETs have parasitic pn diodes (body diodes) between the source and drain. When a forward current flows through the body diode, the reliability of the vertical MOSFET is reduced in the same way as the pn diode. When the body diode of SiC-MOSFET is used as a return diode of the MOSFET, the MOSFET characteristics may be reduced.

[0004] As a method for solving the reliability problem caused by the forward current flowing into the parasitic pn diode as described above, there is a known method of using a Schottky barrier diode (SBD) which is a unipolar diode as a return diode in a semiconductor device which is a unipolar transistor such as a MOSFET, and a current sensing function is built into the MOSFET having the SBD built in (for example, Patent Document 1).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. WO2014 / 162969 p19-p21 Summary of the invention

[0008] In a semiconductor device having a current sensing function, the current sensing pad has to have a certain area in order to be connected to the outside. However, when the entire lower portion of the current sensing pad is made into an active current sensing region through which the sensing current flows, the ineffective sensing current increases and the loss increases. Therefore, a dummy sensing region is sometimes provided under the current sensing pad independently of the active current sensing region.

[0009] As described in Patent Document 1, if the p-type well region of the dummy sensing region of the MOSFET with built-in SBD is connected to the current sensing pad, a large backflow current flows through the ammeter connected to the sensing pad during the backflow action, and a small current flows through the ammeter during the sensing action. In order to detect the sensing current with high accuracy, it is desirable to reduce the current capacity of the ammeter, but when considering that a large backflow current from the dummy sensing region flows through the ammeter, in order to prevent the damage of the ammeter, it is necessary to increase the current capacity of the ammeter, and it is difficult to simultaneously ensure the high accuracy of the sensing current and the backflow current resistance. In addition, although it is also considered to prevent a large current from flowing through the ammeter during the backflow action by connecting a well region of the conductivity type opposite to the conductivity type of the drift layer of the dummy sensing region of the MOSFET with built-in SBD to the source pad through which the main current flows, in order to achieve this while maintaining the area of ​​the sensing pad as it is, it is necessary to increase the current sensing region to make the active area of ​​the MOSFET narrower. Furthermore, when the well region of the dummy sensing region is connected to the source pad, a forward current flows through a pn diode formed between the p-type well region of the dummy sensing region and the n-type drift layer during a reflow operation, which may cause current degradation.

[0010] The silicon carbide semiconductor device and the power conversion device involved in the present disclosure have a dummy sensing area formed between an active area and an active sensing area, and are equipped with: a semiconductor substrate of silicon carbide of the first conductivity type; a drift layer of the first conductivity type formed on the semiconductor substrate; a first well region of the second conductivity type, a plurality of which are arranged in the drift layer of the active area; a plurality of first separation regions of the first conductivity type, formed adjacent to each of the first well regions; a first ohmic electrode, arranged on the first well region; a source region of the first conductivity type, formed on the surface of the first well region; a source electrode, arranged in contact with the first separation region, Schottky-connected to the first separation region and electrically connected to the first ohmic electrode; a second well region of the second conductivity type, arranged on the surface of the drift layer of the active sensing area away from the first well region; a plurality of third separation regions of the first conductivity type , formed adjacent to each of the second well regions; a second ohmic electrode, arranged on the second well region; a sensing pad, arranged in contact with the third separation region, Schottky-connected to the third separation region and electrically connected to the second ohmic electrode, formed in the active sensing region and the dummy sensing region; a sensing source region of the first conductive type, formed in the surface portion of the second well region; a gate insulating film, formed in contact with the first well region and the second well region; a gate electrode, formed opposite to the first well region and the second well region via the gate insulating film; a gate pad, electrically connected to the gate electrode; and a third well region of the second conductive type, formed in the surface layer of the drift layer in the dummy sensing region between the first well region and the second well region, away from the first well region and the second well region, and not ohmically connected to any of the source electrode and the sensing pad.

[0011] According to the silicon carbide semiconductor device involved in the present disclosure, it is possible to provide a silicon carbide semiconductor device and a power conversion device that can connect an ammeter capable of measuring a minute current to a sense pad and measure a sense current with high accuracy while preventing the silicon carbide semiconductor device from being degraded due to power-on. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a top view of the silicon carbide semiconductor device according to the first embodiment of the present invention.

[0013] Figure 2 It is a plan view of a portion of the silicon carbide semiconductor device according to the first embodiment of the present invention.

[0014] Figure 3 This is a cross-sectional view of a portion of the silicon carbide semiconductor device according to the first embodiment of the present invention.

[0015] Figure 4This is a circuit diagram showing the structure of a silicon carbide semiconductor device and its periphery according to the first embodiment of the present invention.

[0016] Figure 5 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the first embodiment of the present invention.

[0017] Figure 6 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the first embodiment of the present invention.

[0018] Figure 7 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the first embodiment of the present invention.

[0019] Figure 8 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to a second embodiment of the present invention.

[0020] Fig. 9 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the second embodiment of the present invention.

[0021] Fig.10 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the second embodiment of the present invention.

[0022] Fig.11 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to a second embodiment of the present invention.

[0023] Fig.12 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to a second embodiment of the present invention.

[0024] Fig.13 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to a third embodiment of the present invention.

[0025] Fig.14 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the third embodiment of the present invention.

[0026] Fig.15 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the third embodiment of the present invention.

[0027] Fig.16 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the third embodiment of the present invention.

[0028] Fig.17 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the third embodiment of the present invention.

[0029] Fig.18 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the third embodiment of the present invention.

[0030] Fig.19 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the third embodiment of the present invention.

[0031] Fig. 20 This is a cross-sectional view of a portion of a silicon carbide semiconductor device according to another aspect of the third embodiment of the present invention.

[0032] Fig.21 This is a schematic diagram showing the configuration of a power conversion device according to Embodiment 4 of the present invention.

[0033] (Explanation of symbols)

[0034] 10: semiconductor substrate; 20: drift layer; 21: first departure region; 22: second departure region; 23: third departure region; 24: fourth departure region; fifth departure region; 30: well region; 31: sensing well region; 32: dummy sensing well region; 35: well contact region; 36: sensing contact region; 40: source region; 41: sensing source region; 42: low resistance layer; 50: gate insulating film; 51: field insulating film; 55: interlayer insulating film; 60: gate electrode; 70: ohmic electrode; 71: sensing ohmic electrode; 72: dummy sensing ohmic electrode : a first electrode; 81: a source electrode; 82: a gate pad; 83: a sensing pad; 84: a drain electrode; 90: a first contact hole; 91: a second contact hole; 92: a third contact hole; 94: a first groove; 95: a second groove; 96: a third groove; 97: a fourth groove; 98: a fifth groove; 99: a sixth groove; 101: an active region; 102: an active sensing region; 103: a dummy sensing region; 150: a power supply; 200; a power conversion device; 201: a main conversion circuit; 202: a drive circuit; 203: a control circuit; 300: a load. DETAILED DESCRIPTION

[0035] Hereinafter, the implementation mode will be described with reference to the accompanying drawings. In addition, the accompanying drawings are schematically shown, and the relationship between the sizes and positions of the images shown in different drawings is not necessarily correctly recorded, but can be appropriately changed. In addition, in the following description, the same components are illustrated with the same symbols, and their names and functions are also the same. Therefore, their detailed description is sometimes omitted. Furthermore, in the present disclosure, the longitudinal direction refers to the normal direction of the semiconductor substrate of the silicon carbide semiconductor device, and the lateral direction refers to the surface direction of the semiconductor substrate. In addition, the surface side refers to the side of the semiconductor substrate where the drift layer is formed, and the back side refers to the opposite side.

[0036] Implementation method 1.

[0037] First, the structure of the silicon carbide semiconductor device according to the first embodiment of the present disclosure will be described. In the present disclosure, the first conductivity type is set to be the n-type and the second conductivity type is set to be the p-type.

[0038] Figure 1 This is a schematic diagram showing a silicon carbide MOSFET (SiC-MOSFET) chip as a silicon carbide semiconductor device according to Embodiment 1, as viewed from the top surface. Figure 1 In the chip, there are provided: a source electrode 81 (source pad) through which a main current flows, which is provided on substantially the entire surface of the chip, a gate pad 82 formed to be insulated from the source electrode 81, and a sense pad 83 formed to be similarly insulated from the source electrode 81. The lower portion of the source electrode 81 substantially corresponds to the active region 101, and a MOSFET with a built-in SBD is arranged in the active region 101.

[0039] Figure 2 Yes Figure 1 FIG. 8 is an enlarged top view of the vicinity of the sensing pad 83. An active region 101 of a MOSFET with a built-in SBD is formed below the source electrode 81 around the sensing pad 83, and an active sensing region 102 of a MOSFET with a built-in SBD is formed in a portion of the lower portion of the sensing pad 83. A dummy sensing region 103 is formed in the lower portion of the sensing pad 83 where the active sensing region 102 is not formed.

[0040] Figure 3 is and from Figure 2 The cross-sectional view of the active region 101 is a region corresponding to the region where the dummy sensing region 103 is sandwiched between the active sensing region 102 .

[0041] exist Figure 3 In the embodiment, a drift layer 20 composed of n-type silicon carbide is formed by epitaxial growth on the first main surface, i.e., the surface, of a semiconductor substrate 10 composed of n-type and low-resistance silicon carbide having a polytype of 4H. The first main surface of the semiconductor substrate 10 has a plane orientation of (0001) and is inclined 4° relative to the c-axis.

[0042] A region composed of p-type silicon carbide is formed in the surface portion of the drift layer 20 , a plurality of well regions 30 are formed in the active region 101 , a plurality of sense well regions 31 are formed in the active sense region 102 , and a dummy sense well region 32 is formed in the dummy sense region 103 .

[0043] In the active region 101, an n-type first separation region 21 as a part of the drift layer 20 is formed in the central part of each of the plurality of well regions 30 in a plan view, and a p-type well contact region 35 with a high impurity concentration and an n-type source region 40 with a higher n-type impurity concentration than the drift layer 20 are formed from the first separation region 21 inside the well region 30 toward the outside. At least a part of the first separation region 21 is adjacent to the well region 30. The well region 30 is the first well region.

[0044] An n-type second separation region (JFET region) 22 is formed as a part of the drift layer 20 between the well regions 30 of the active region 101. On the second separation region 22, a low-resistance polysilicon gate electrode 60 is formed via a gate insulating film 50 of silicon oxide.

[0045] An ohmic electrode 70 is formed on the source region 40 and the well contact region 35, and a source electrode 81 is formed on the ohmic electrode 70 and the first separation region 21. The first separation region 21 and the source electrode 81 form a Schottky junction, and the source region 40 and the source electrode 81, and the well contact region 35 and the source electrode 81 are ohmically connected, respectively. The ohmic electrode 70 is a first ohmic electrode.

[0046] In addition, in the active sensing region 102, an n-type third separation region 23 as a part of the drift layer 20 is formed in the central portion of each of the plurality of sensing well regions 31, and a sensing contact region 36 of p-type with a high impurity concentration and an n-type sensing source region 41 having an n-type impurity concentration higher than that of the drift layer 20 are formed from the third separation region 23 inside the sensing well region 31 toward the outside. At least a portion of the third separation region 23 is adjacent to the sensing well region 31. The sensing well region 31 is a second well region.

[0047] An n-type fourth separation region (JFET region) 24 is formed as a part of the drift layer 20 between the sense well regions 31 of the active sense region 102. On the fourth separation region 24, a low-resistance polysilicon gate electrode 60 is formed via a silicon oxide gate insulating film 50.

[0048] A sensing ohmic electrode 71 is formed on the sensing source region 41 and the sensing contact region 36, and a sensing pad 83 is formed on the sensing ohmic electrode 71 and the third separation region 23. The third separation region 23 and the sensing pad 83 form a Schottky junction, and the sensing source region 41 and the sensing pad 83, and the sensing contact region 36 and the sensing pad 83 are ohmically connected, respectively. The sensing ohmic electrode 71 is a second ohmic electrode.

[0049] In the active sensing region 102 , a unit cell MOSFET having the same size and the same structure as those in the active region 101 is formed.

[0050] In the dummy sensing region 103 , a dummy sensing well region 32 is formed so as not to be ohmically connected to any of the source electrode 81 and the sensing pad 83 .

[0051] A gate insulating film 50 and a field insulating film 51 made of silicon oxide having a greater film thickness than the gate insulating film 50 are formed on the upper portion of the dummy sense well region 32. Figure 3 In the cross-sectional view of , a sensing pad 83 is formed on the dummy sensing well region 32 , but the dummy sensing well region 32 and the sensing pad 83 are Schottky-connected rather than ohmically connected.

[0052] Here, an n-type fifth separation region 25 is formed between the well region 30 and the dummy sense well region 32, which is a part of the drift layer 20. An n-type fifth separation region 25 is also formed between the sense well region 31 and the dummy sense well region 32, which is a part of the drift layer 20. The dummy sense well region 32 is a third well region.

[0053] Furthermore, an interlayer insulating film 55 made of silicon oxide is formed on the gate insulating film 50 , the gate electrode 60 , or the field insulating film 51 from the active region 101 to the dummy sensing region 103 and the active sensing region 102 .

[0054] Although not shown, the gate electrode 60 of the active region 101 and the gate electrode 60 of the active sensing region are connected to each other through a gate contact hole (not shown) provided in the interlayer insulating film 55. Figure 1 Gate pad 82 is shown electrically connected.

[0055] exist Figure 3 In the cross-sectional view of FIG. 1 , in the active region 101, the source electrode 81 contacts the ohmic electrode 70 and the first separation region 21 via the first contact hole 90. In the active sensing region 102, the sensing pad 83 contacts the sensing ohmic electrode 71 and the third separation region 23 via the second contact hole 91. In the dummy sensing region 103, the sensing pad 83 contacts the dummy sensing well region 32 via the third contact hole 92.

[0056] In addition, the source electrode 81 , the sense pad 83 , and the gate pad 82 are formed of the same electrode material such as Al.

[0057] Furthermore, a drain electrode 84 is formed on the back surface side of the semiconductor substrate 10 .

[0058] Next, a method for manufacturing the SiC-MOSFET with built-in SBD as the silicon carbide semiconductor device according to the present embodiment will be described.

[0059] First, a 1×10 14 Above and 1×10 17 cm -3 At an impurity concentration of 100 μm or less, the drift layer 20 made of n-type silicon carbide with a thickness of 5 μm or more and 100 μm or less is epitaxially grown.

[0060] Next, an implantation mask is formed in a predetermined region on the surface of the drift layer 20 by means of a photoresist or the like, and ion implantation of Al (aluminum) as a p-type impurity is performed. At this time, the depth of the Al ion implantation is set to a depth not exceeding 0.5 μm and not exceeding 3 μm of the thickness of the drift layer 20. In addition, the impurity concentration of the Al ion implantation is 1×10 17 cm -3 Above and 1×10 19 cm -3 The range below is higher than the impurity concentration of the drift layer 20. After that, the implantation mask is removed. The region into which Al ions are implanted in this step becomes the well region 30, the sense well region 31, and the dummy sense well region 32.

[0061] Likewise, by ion implanting Al into a predetermined region at a higher impurity concentration than the impurity concentration of the well region 30 , the well contact region 35 and the sense contact region 36 are formed.

[0062] Next, an implantation mask is formed by a photoresist or the like so as to open predetermined locations inside the well region 30 and the sensing well region 31, and ion implantation of N (nitrogen) as an n-type impurity is performed. The ion implantation depth of N is shallower than the thickness of the well region 30. In addition, the impurity concentration of the ion implanted N is 1×10 18 cm -3 Above and 1×10 21 cm -3 The following range exceeds the p-type impurity concentration of the well region 30. The region exhibiting n-type in the region into which N is implanted in this step becomes the source region 40 and the sense source region 41.

[0063] Next, annealing is performed in a heat treatment apparatus in an inert gas atmosphere such as argon (Ar) gas at a temperature of 1300 to 1900° C. for 30 seconds to 1 hour. This annealing electrically activates the ion-implanted N and Al.

[0064] Next, a field insulating film 51 made of silicon oxide having a film thickness of 0.5 μm or more and 2 μm or less is formed on the semiconductor layer in regions other than regions substantially corresponding to the regions where the well regions 30 and the sense well regions 31 are formed, using a CVD method, a photolithography technique, or the like. The field insulating film 51 is also formed on the dummy sense well region 32.

[0065] Next, the silicon carbide surface not covered by the field insulating film 51 is thermally oxidized to form a silicon oxide film of a desired thickness as the gate insulating film 50. Next, a polycrystalline silicon film having conductivity is formed on the gate insulating film 50 and the field insulating film 51 by a reduced pressure CVD method, and is patterned to form a gate electrode 60. Next, an interlayer insulating film 55 made of silicon oxide is formed by a reduced pressure CVD method. Next, a first contact hole 90 is formed that penetrates the interlayer insulating film 55 and the gate insulating film 50 and reaches the well contact region 35 and the source region 40 in the active region 101, a third contact hole 92 that reaches the dummy sensing well region 32 in the dummy sensing region 103, and a second contact hole 91 that reaches the sensing contact region 36 and the sensing source region 41 of the active sensing region 102.

[0066] Next, after a metal film mainly composed of Ni is formed by sputtering or the like, a heat treatment is performed at a temperature of 600° C. to 1000° C. to react the metal film mainly composed of Ni with the silicon carbide layer in the first contact hole 90 and the second contact hole 91, thereby forming silicide between the silicon carbide layer and the metal film. Next, the remaining metal film other than the silicide formed by the reaction is removed by wet etching. Thus, the ohmic electrode 70 and the sensing ohmic electrode 71 are formed.

[0067] Next, a metal film mainly composed of Ni is formed on the back surface (second main surface) of the semiconductor substrate 10 and heat-treated to form a back ohmic electrode (not shown) on the back side of the semiconductor substrate 10 .

[0068] Next, by patterning using a photoresist or the like, the interlayer insulating film 55 is removed at a location that becomes a gate contact hole (not shown) on the gate electrode 60 in a region where the gate pad 82 is to be formed or in the vicinity thereof.

[0069] Next, a metal film that is Schottky-connected to the drift layer 20 is deposited by sputtering or the like, and a source electrode 81 is formed on the first separation region 21 in the first contact hole 90 and the ohmic electrode 70 and on the interlayer insulating film 55 by patterning using a photoresist or the like. The source electrode 81 does not need to be composed of a single metal, and may be an example of a laminated film of Al and Ti or the like in which two or more metals are laminated. In addition, electrodes of different materials may be applied only to the portions that are Schottky-connected to n-type regions such as the first separation region 21 and the third separation region 23. Simultaneously with the formation of the source electrode 81, a gate pad 82 electrically separated from the source electrode 81 is formed on the gate electrode 60 in the gate contact hole, and a sense pad 83 electrically separated from the source electrode 81 is formed on the third separation region 23 in the second contact hole 91 and the sense ohmic electrode 71.

[0070] Furthermore, if a drain electrode 84 is formed as a metal film on the surface of a back ohmic electrode (not shown) formed on the back side of the substrate, Figures 1 to 3 The silicon carbide semiconductor device of the present embodiment shown is completed.

[0071] Next, a case where the silicon carbide semiconductor device according to the present embodiment of the present disclosure mainly performs a reflow operation will be described.

[0072] A circuit diagram illustrating the silicon carbide semiconductor device of the present disclosure. Figure 4 This is a circuit diagram of the structure of the silicon carbide semiconductor device and its periphery disclosed in the present invention. Here, in the active region 101, a MOSFET having a source electrode 81, a drain electrode 84, and a gate pad 82 is configured, and in the active sensing region 102, a sensing MOSFET having a sensing pad 83, a drain electrode 84, and a gate pad 82 is configured. The sensing pad 83 is connected to an external ammeter. By changing the voltage of the gate pad 82, the MOSFET is turned on / off. The diode connected in anti-parallel to the MOSFET is a structure that combines the body diode of the MOSFET and the built-in SBD.

[0073] In the return current operation, the drain voltage (the voltage of the drain electrode 84) becomes lower than the source voltage (the voltage of the source electrode 81), and a voltage of several V is generated between the source and the drain. In the active region 101, an SBD is formed between the first separation region 21 and the source electrode 81, which is turned on at a voltage lower than that of the body diode composed of the well region 30 and the drift layer 20. Therefore, in principle, the return current flows through the SBD, and the return current does not flow through the well region 30.

[0074] In the active sensing region 102, the sensing source voltage (the voltage of the sensing pad 83) also becomes a value closer to the source voltage than the drain voltage, so in the active sensing region 102, as in the active region 101, an SBD is formed between the third separation region 23 and the sensing pad 83. In principle, a return current flows through the SBD, and no return current flows through the sensing well region 31 during the return action.

[0075] In the dummy sensing region 103, no SBD is formed in this structure, but the dummy sensing well region 32 is not ohmically connected to the source electrode 81 but is Schottky-connected to the sensing pad 83, so that during the reflow operation, no current flows from the source electrode 81 or the sensing pad 83 to the drain electrode 84 via the dummy sensing well region 32. That is, forward current is suppressed from flowing in the pn junction between the dummy sensing well region 32 and the drift layer 20.

[0076] Thus, in the silicon carbide semiconductor device of the present embodiment, in the SBD built-in MOSFET with current sensing function, the lower part of the sensing pad for current sensing is not entirely made into an active sensing area, thereby preventing the increase of invalid current caused by the sensing current, and further, by connecting the dummy sensing well area in the dummy sensing area between the active area and the sensing area to neither the source potential nor the sensing source potential, it is possible to suppress the forward current flowing through the pn diode during the reflux action and causing the power-on degradation.

[0077] Therefore, according to the silicon carbide semiconductor device of this embodiment, the ineffective current caused by the sense current is not increased, and the power-on degradation can be suppressed. In addition, since a dummy sensing area is provided, the sense current can be measured with a small-capacity ammeter with high accuracy without making the sense current an ammeter with a large capacity, and in this sense, the reliability of the element can also be improved.

[0078] In the SiC-MOSFET as the silicon carbide semiconductor device of the present embodiment, as in Figure 3 As shown in the cross-sectional view thereof, a gate electrode 60 is formed on the gate insulating film 50 and the field insulating film 51 on the dummy sensing well region 32 , but the structure on the dummy sensing well region 32 may be other structures.

[0079] Figure 5 FIG. 1 is a cross-sectional view of another embodiment of the silicon carbide semiconductor device of the present embodiment. Figure 5 In the embodiment, the gate insulating film 50 is formed on the dummy sensing well region 32, and the gate electrode 60 is not formed on the dummy sensing well region 32. With this structure, the potential of the dummy sensing well region 32 can be suppressed from changing due to the potential of the gate electrode 60 changing by on / off, and in this respect, the reliability can be further improved.

[0080] Figure 6 is a cross-sectional view of another embodiment of the silicon carbide semiconductor device of the present embodiment. Figure 5 In addition to the structure, an n-type low resistance layer 42 made of silicon carbide is formed on the upper layer of the dummy sensing well region 32. Here, a dummy sensing ohmic electrode 72 is formed on the dummy sensing well region 32, and the low resistance layer 42 and the sensing pad 83 are ohmically connected through the third contact hole 92. The impurity concentration of the n-type low resistance layer 42 is the same as that of the source region 40, 1×10 18 Above and 1×10 21 cm -3 The following range is sufficient.

[0081] Here, the sense pad 83 is ohmically connected to the n-type low resistance layer 42, and is not ohmically connected to the p-type dummy sense well region 32. In addition, the low resistance layer 42 can reduce the voltage generated in the dummy sense well region 32 during the switching operation.

[0082] Alternatively, the dummy sensing well region 32 may be completely covered with an insulating film. Figure 7 FIG. 1 is a cross-sectional view of another embodiment of the silicon carbide semiconductor device of the present embodiment. Figure 7 In the embodiment, the upper portion of the dummy sense well region 32 is covered with the gate insulating film 50 or the field insulating film 51, and the dummy sense well region 32 is not connected to the source electrode 80 and the sense pad 83. Therefore, with this structure, it is possible to provide a silicon carbide semiconductor device that can prevent the silicon carbide semiconductor device from being degraded by power-on while connecting an ammeter capable of measuring a minute current to the sense source electrode to measure the sense current with high accuracy.

[0083] Implementation method 2.

[0084] The SiC-MOSFET as the silicon carbide semiconductor device of this embodiment is different from the SiC-MOSFET of Embodiment 1 in that a gate / sense source capacitance is formed in the dummy sense well region 32. Other points are the same as those of Embodiment 1, and thus detailed description is omitted.

[0085] Figure 8 : is a cross-sectional view of a SiC-MOSFET of a silicon carbide semiconductor device according to the present embodiment. Figure 8 In the embodiment, a gate insulating film 50 is formed on the dummy sensing well region 32, and a gate electrode 60 is formed on the gate insulating film 50. The dummy sensing well region 32 is Schottky-connected to the sensing pad 83 at a certain position in the depth direction of the paper (not shown). The gate electrode 60 may be formed on the entire region of the dummy sensing well region 32 except for the Schottky connection position, or may be formed on the gate insulating film 50. Fig. 9As shown in the cross-sectional view thereof, it is formed on a portion of the dummy sensing well region 32 .

[0086] According to the SiC-MOSFET of the silicon carbide semiconductor device of the present embodiment, a capacitance can be added between the gate pad 82 and the sense pad 83 , so that the electrostatic tolerance can be increased and the reliability of the element can be improved.

[0087] In addition, the SiC-MOSFET of the silicon carbide semiconductor device of the present embodiment can also be Fig.10 As shown in the cross-sectional schematic diagram, a low-resistance n-type low-resistance layer 42 is formed on the upper portion of the dummy sensing well region 32. By configuring the low-resistance layer 42 to face the gate electrode 60 with the gate insulating film 50 sandwiched therebetween, the gate / sensing source capacitance can be further increased, and the capacitance variation caused by the gate voltage can be further reduced.

[0088] Furthermore, it is also possible to Fig.11 As shown in the cross-sectional view thereof, a SBD is formed in the dummy sensing well region 32. Fig.11 In the embodiment, the sixth separation region 26, which is a part of the drift layer 20 formed inside the dummy sense well region 32 in a plan view, is Schottky-connected to the sense pad 83 in the third contact hole 92. By forming the SBD in the dummy sense well region 32, the dummy sense region 103 can be further reduced from being degraded due to power-on.

[0089] In addition, you can also Fig.12 As shown in the cross-sectional view, the n-type low resistance layer 42 formed on the upper layer of the dummy sensing well region 32 and the sensing pad 83 in the third contact hole 92 are ohmically connected, and the low resistance layer 42 and the gate electrode 60 are opposed to each other via the gate insulating film 50. With this structure, the gate / sensing source capacitance can be increased as it is, and the occurrence of power-on degradation can be prevented.

[0090] Implementation method 3.

[0091] The SiC-MOSFET as the silicon carbide semiconductor device of this embodiment is different from Embodiments 1 and 2 in that the MOSFETs in the active region 101 and the active sensing region 102 are trench-type. Other aspects are the same as Embodiments 1 and 2, and thus detailed descriptions are omitted.

[0092] Fig.13 : is a cross-sectional view of a SiC-MOSFET of a silicon carbide semiconductor device according to the present embodiment. Fig.13In the active region 101, a first trench 94 is formed which penetrates the p-type well region 30 formed on the surface of the n-type drift layer 20 and the n-type source region 40 and reaches the drift layer 20, and a gate electrode 60 is formed in the first trench 94 via a gate insulating film 50. A well contact region 35 is formed in a part of the well region 30, and a source electrode 81 is formed on the well contact region 35 and on the ohmic electrode 70 on the source region 40. A trench MOSFET is formed by these.

[0093] The n-type first separation region 21 between the well regions 30 is a part of the drift layer 20 , and is Schottky-connected to the source electrode 81 formed thereon to form a SBD.

[0094] In the active sensing region 102, a second trench 95 is formed that penetrates the p-type sensing well region 31 formed on the surface of the n-type drift layer 20 and the n-type sensing source region 41 and reaches the drift layer 20, and a gate electrode 60 is formed in the second trench 95 via a gate insulating film 50. An interlayer insulating film 55 is formed on the gate electrode 60. A sensing contact region 36 is formed on a portion of the sensing well region 31, and a sensing pad 83 is formed on the sensing contact region 36 and on the sensing ohmic electrode 71 on the sensing source region 41. A trench MOSFET is formed by these. The n-type third separation region 23 between the sensing well regions 31 and the sensing well regions 31 is a portion of the drift layer 20, and is Schottky-connected to the sensing pad 83 formed thereon to form an SBD.

[0095] In the dummy sensing region 103 between the active region 101 and the active sensing region 102 , a p-type dummy sensing well region 32 is formed on the surface of the drift layer 20 , similarly to Embodiment 1. An interlayer insulating film 55 is formed on the dummy sensing well region 32 to cover the entire dummy sensing well region 32 .

[0096] The method for manufacturing the SiC-MOSFET as the silicon carbide semiconductor device of the present embodiment is the same as the method for manufacturing the SiC-MOSFET as the silicon carbide semiconductor device of the first embodiment except that the trench MOSFET is manufactured by a general manufacturing method, so a detailed description is omitted. The first trench 94 of the active region 101 and the second trench 95 of the active sensing region 102 may also be formed at the same time.

[0097] In the SiC-MOSFET as the silicon carbide semiconductor device of the present embodiment, the ineffective current due to the sense current does not increase, and the conduction degradation can be suppressed.

[0098] In addition, the dummy sensing well region 32 of the SiC-MOSFET as the silicon carbide semiconductor device of the present embodiment may be formed, for example, Fig.14 As shown in the cross-sectional view, a gate electrode 60 is provided via a gate insulating film. A low-resistance n-type low-resistance layer 42 is formed on the upper layer of the dummy sensing well region 32. The low-resistance layer 42 and the sensing pad 83 in the third contact hole 92 are ohmically connected via the dummy sensing ohmic electrode 72. The low-resistance layer 42 and the gate electrode 60 are opposed to each other via the gate insulating film 50. The dummy sensing well region 32 is not ohmically connected to the sensing pad 83 as in the first embodiment. By adopting Fig.14 The structure can increase the gate / sensing source capacitance and further improve the reliability of the element. Fig.15 As shown in the cross-sectional view, the dummy sensing well region 32 is divided, a gate insulating film 50 and a gate electrode 60 are provided on each dummy sensing well region 32, and an n-type seventh separation region 27 and a sensing pad 83 are provided between the dummy sensing well regions 32. Here, a unit structure in which the repetition period of the active region 101 and the repetition period of the dummy sensing region 103 are the same can also be provided.

[0099] Here, the dummy sense well region 32 is also not ohmically connected to any of the source electrode 81 and the sense pad 83 .

[0100] Alternatively, the Schottky diode may be provided in a trench provided independently of the trench of the trench MOS. Fig.16 1 is a cross-sectional view of another embodiment of a SiC-MOSFET as a silicon carbide semiconductor device according to the present embodiment. Fig.16 In the SiC-MOSFET having the structure, a trench for MOSFET and a trench for Schottky diode are formed in the active region 101 and the active sensing region 102, respectively. The trench for Schottky diode in the active region 101 is the third trench 96, and the trench for Schottky diode in the active sensing region 102 is the fourth trench 97.

[0101] In the active region 101, a gate trench (first trench) 94 for forming a MOSFET is formed so as to penetrate the well region 30 and the source region 40 and reach the drift layer 20, and a gate electrode 60 is formed in the gate trench (first trench) 94 via a gate insulating film 50. A Schottky trench (third trench) 96 for forming a Schottky diode is formed in the drift layer 20.

[0102] In the active sensing region 102, a gate trench (second trench) 95 for forming a MOSFET is formed so as to penetrate the sensing well region 31 and the sensing source region 41 and reach the drift layer 20, and a gate electrode 60 is formed in the gate trench (second trench) 95 via a gate insulating film 50. A Schottky trench (fourth trench) 97 for forming a Schottky diode is formed in the drift layer 20.

[0103] In the dummy sensing region 103, the dummy sensing well region 32 is formed in the upper layer of the drift layer 20, and the entire upper region thereof may be covered with the interlayer insulating film 55, or only a part thereof may be covered with the interlayer insulating film 55. When the dummy sensing well region 32 is in contact with the source electrode 81 or the sensing pad 83, a Schottky junction is formed with them. The dummy sensing well region 32 is not ohmically connected to any of the source electrode 81 and the sensing pad 83, so that during the reflow operation, no current flows from the source electrode 81 or the sensing pad 83 to the drain electrode 84 via the dummy sensing well region 32. That is, the forward current is suppressed from flowing in the pn junction between the dummy sensing well region 32 and the drift layer 20.

[0104] Here, in the dummy sensing area 103, it is also possible to Fig.17 As shown in the cross-sectional view thereof, a gate electrode 60 is provided on the dummy sensing well region 32 via a gate insulating film 50. A low-resistance and n-type low-resistance layer 42 is formed on the upper layer of the dummy sensing well region 32, the low-resistance layer 42 and the sensing pad 83 in the third contact hole 92 are ohmically connected, and the low-resistance layer 42 and the gate electrode 60 are opposed via the gate insulating film 50. In addition, the dummy sensing well region 32 is not ohmically connected to the sensing pad 83 as in the first embodiment. Thus, the gate / sensing source capacitance can be increased, so the electrostatic tolerance can be increased, and the reliability of the element can be improved.

[0105] Furthermore, a trench-type Schottky trench (fifth trench) 98 may be provided in the dummy sensing region 103 . Fig.18 is a cross-sectional view of a silicon carbide semiconductor device according to this embodiment. Fig.18 In the embodiment, dummy sensing well regions 32 are formed at intervals in the dummy sensing region 103, and Schottky trenches (fifth trenches) 98 are formed between the dummy sensing well regions 32. A sensing pad 83 is formed in the Schottky trenches (fifth trenches) 98, and the sensing pad 83 is Schottky-connected to the drift layer 20. Fig.18 With the structure, a large-area Schottky diode can be formed in the dummy sensing well region 32 , and the dummy sensing region 103 can be further reduced in terms of electrical degradation.

[0106] in addition, Fig.19 is a cross-sectional view of a silicon carbide semiconductor device according to another embodiment of the present embodiment. Fig.19In the embodiment, a groove (sixth groove) 99 which does not penetrate the dummy sensing well region 32 is formed in the dummy sensing well region 32, and a gate electrode 60 is formed in the groove via a gate insulating film 50. An n-type low-resistance layer 42 is formed in the upper layer of the dummy sensing well region 32 and at the bottom of the groove (sixth groove) 99, and is opposed to the gate electrode 60 via a gate insulating film 50. When the depth of the sixth groove 99 is designed to be the same as that of the first to fourth grooves, the dummy sensing well region 32 must be formed deeper than the other well regions, which can be formed by high-energy ion implantation before forming the sixth groove 99, or by ion implantation with an additional inclination on the groove surface after forming the sixth groove 99. The low-resistance layer 42 can be formed to the same depth as the dummy sensing well region 32, or can be formed to the same depth at the same time as other source regions 40.

[0107] according to Fig.19 The silicon carbide semiconductor device having the structure can further increase the gate / sense source capacitance added to the gate electrode 60, so that the electrostatic tolerance can be increased and the reliability of the element can be further improved.

[0108] Fig. 20 FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device of another structure according to the present embodiment. Fig. 20 In the silicon carbide semiconductor device having the structure of Fig.19 In the silicon carbide semiconductor device having such a structure, the gate / sense source capacitance added to the gate electrode 60 can be further increased, so that the electrostatic tolerance can be increased and the reliability of the device can be further improved.

[0109] In the first to third embodiments, the examples in which the dummy sense well region 32 is mainly Schottky-connected or pn-jointed to the sense pad 83 are described, but the dummy sense well region 32 may be Schottky-connected or pn-jointed to the source electrode 81 .

[0110] In the first to third embodiments, the impurity concentration between the active region 101 and the dummy sensing region 103 and between the active sensing region 102 and the dummy sensing region 103 is the same as that of the drift layer 20, but the n-type impurity concentration in these regions may be higher than that in the drift layer 20. In addition, the source electrode 81 or the sensing pad 83 may be formed on the upper part of the drift layer 20 between the active region 101 and the dummy sensing region 103 and between the active sensing region 102 and the dummy sensing region 103, so that the drift layer 20 and the source electrode 81 or the sensing pad 83 are Schottky-connected. Furthermore, for example, Fig.12As shown, the upper portion of the drift layer 20 between the active region 101 and the dummy sensing region 103 and between the active sensing region 102 and the dummy sensing region 103 is covered with an insulating film such as a field insulating film 51 having a greater film thickness than the gate insulating film 50 .

[0111] In addition, in embodiments 1 to 3, aluminum (Al) is used as a p-type impurity, but the p-type impurity may also be boron (B) or gallium (Ga). The n-type impurity may also be phosphorus (P) instead of nitrogen (N). In the MOSFET described in embodiments 1 to 4, the gate insulating film does not necessarily need to be an oxide film such as SiO2, but may also be an insulating film other than an oxide film or a combination of an insulating film other than an oxide film and an oxide film. In addition, an example in which silicon oxide formed by thermally oxidizing silicon carbide is used as the gate insulating film 50 is mainly shown, but it may also be a silicon oxide deposited film using a CVD method. In addition, in the above embodiments, specific examples are used to illustrate the crystal structure, the plane orientation of the main surface, the tilt angle, and various injection conditions, but the scope of application is not limited to these numerical ranges. Furthermore, in the above embodiments, a silicon carbide semiconductor device of a so-called vertical MOSFET is described, but it can also be applied to a MOSFET having a super junction structure.

[0112] Implementation method 4.

[0113] This embodiment is an example in which the silicon carbide semiconductor device according to the above-mentioned Embodiments 1 to 3 is applied to a power conversion device. The present disclosure is not limited to a specific power conversion device, but the following describes a case in which the present disclosure is applied to a three-phase inverter as Embodiment 4.

[0114] Fig.21 A block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

[0115] Fig.21 The power conversion system shown is composed of a power supply 150, a power conversion device 200, and a load 300. The power supply 150 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various examples, for example, it can be composed of a DC system, a solar cell, a storage battery, or a rectifier circuit connected to an AC system, and an AC / DC converter. In addition, the power supply 150 can also be composed of a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0116] The power conversion device 200 is a three-phase inverter connected between the power source 150 and the load 300, converts the DC power supplied from the power source 150 into AC power, and supplies the AC power to the load 300. Fig.18As shown, the power conversion device 200 includes: a main conversion circuit 201, which converts DC power into AC power and outputs it; a drive circuit 202, which outputs a drive signal for driving each switching element of the main conversion circuit 201; and a control circuit 203, which outputs a control signal of the control drive circuit 202 to the drive circuit 202.

[0117] The drive circuit 202 controls each normally-off switching element to be turned off by making the voltage of the gate electrode and the voltage of the source electrode the same potential.

[0118] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Load 300 is not limited to a specific use, and is a motor mounted on various electrical devices, such as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0119] The power conversion device 200 is described in detail below. The main conversion circuit 201 includes a switching element and a return diode (not shown), and converts the DC power supplied from the power supply 150 into AC power by switching the switching element, and supplies it to the load 300. There are various examples of the specific circuit structure of the main conversion circuit 201, but the main conversion circuit 201 of this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 return diodes connected in anti-parallel with each switching element. In each switching element of the main conversion circuit 201, the silicon carbide semiconductor device involved in any of the above-mentioned embodiments 1 to 6 is applied. With respect to the 6 switching elements, upper and lower branches are formed for every 2 switching elements connected in series, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. In addition, the output terminal of each upper and lower branch, that is, the three output terminals of the main conversion circuit 201, is connected to the load 300.

[0120] The drive circuit 202 generates a drive signal for driving the switch element of the main conversion circuit 201, and supplies it to the control electrode of the switch element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, the drive signal for turning on the switch element and the drive signal for turning off the switch element are output to the control electrode of each switch element. When the switch element is maintained in the on state, the drive signal is a voltage signal (on signal) above the threshold voltage of the switch element, and when the switch element is maintained in the off state, the drive signal is a voltage signal (off signal) below the threshold voltage of the switch element.

[0121] The control circuit 203 controls the switch elements of the main conversion circuit 201 in such a manner that the desired power is supplied to the load 300. Specifically, the time (on-time) when each switch element of the main conversion circuit 201 should be in the on state is calculated according to the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switch element according to the voltage to be output. In addition, a control instruction (control signal) is output to the drive circuit 202 in such a manner that an on signal is output to the switch element that should be in the on state and an off signal is output to the switch element that should be in the off state at each time point. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switch element in accordance with the control signal.

[0122] In the power conversion device according to this embodiment, the silicon carbide semiconductor devices according to Embodiments 1 to 3 are applied as switching elements of the main conversion circuit 201 , so that a power conversion device with low loss and improved reliability of high-speed switching can be realized.

[0123] In this embodiment, an example of applying the present disclosure to a 2-level three-phase inverter is described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but a 3-level or multi-level power conversion device can also be used. When power is supplied to a single-phase load, the present disclosure can also be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0124] In addition, the application of the power conversion device disclosed in the present invention is not limited to the case where the above-mentioned load is an electric motor. For example, it can be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

Claims

1. A silicon carbide semiconductor device, characterized in that: The silicon carbide semiconductor device has a dummy sensing region formed between the active region and the active sensing region. The silicon carbide semiconductor device comprises: a semiconductor substrate of silicon carbide of a first conductivity type; A drift layer of the first conductivity type is formed on the semiconductor substrate; A first well region of the second conductivity type is provided in plurality in the drift layer of the active region; A plurality of first conductive type first separation regions are formed adjacent to the first well regions; a first ohmic electrode, disposed on the first well region; A source region of the first conductivity type is formed in a surface portion of the first well region; A source electrode is disposed in contact with the first separation region, is Schottky-connected to the first separation region, and is electrically connected to the first ohmic electrode; a second well region of a second conductivity type, disposed at a surface layer of the drift layer in the active sensing region away from the first well region; A plurality of third separation regions of the first conductivity type are formed adjacent to each of the second well regions; a second ohmic electrode, disposed on the second well region; A sensing pad is disposed in contact with the third separation region, is Schottky-connected to the third separation region and is electrically connected to the second ohmic electrode, and is formed in the active sensing region and the dummy sensing region; A sensing source region of the first conductivity type is formed on a surface portion of the second well region; a gate insulating film formed in contact with the first well region and the second well region; a gate electrode formed to face the first well region and the second well region via the gate insulating film; A gate pad electrically connected to the gate electrode; as well as A third well region of the second conductivity type is formed in a surface layer of the drift layer in a dummy sensing region between the first well region and the second well region away from the first well region and is not ohmically connected to any of the source electrode and the sensing pad.

2. The silicon carbide semiconductor device according to claim 1, wherein: The third well region is Schottky-connected to the sensing pad.

3. The silicon carbide semiconductor device according to claim 1, wherein: A low-resistance layer of the first conductivity type is provided in an upper layer portion of the third well region, and the low-resistance layer is ohmically connected to the sensing pad.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that: In a plan view, a fourth separation region of the first conductivity type is provided in the third well region, and the fourth separation region and the sensing pad are Schottky-connected.

5. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that: The silicon carbide semiconductor device includes the gate insulating film in contact with the third well region, and the silicon carbide semiconductor device comprises the gate electrode in contact with the gate insulating film in contact with the third well region.

6. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that: In the active region, the gate insulating film is formed in contact with the first trench penetrating the source region and the first well region, and in the active sensing region, the gate insulating film is formed in contact with the second trench penetrating the sensing source region and the second well region.

7. The silicon carbide semiconductor device according to claim 6, wherein: In the active region, the source electrode formed in the third groove independently of the first groove is Schottky-connected to the first separation region, and in the active sensing region, the sensing pad formed in the fourth groove independently of the second groove is Schottky-connected to the third separation region.

8. The silicon carbide semiconductor device according to any one of claims 1 to 3, characterized in that: The dummy sensing region has a unit structure having the same repetition period as that of the active region.

9. The silicon carbide semiconductor device according to claim 8, wherein: A fifth trench is provided in the dummy sensing region, and the sensing pad formed in the fifth trench is Schottky-connected to the drift layer.

10. The silicon carbide semiconductor device according to claim 8, wherein: The dummy sensing region includes a sixth trench, and the gate electrode is formed in the sixth trench via the gate insulating film.

11. The silicon carbide semiconductor device according to claim 10, wherein: The sixth trench is not in contact with the drift layer.

12. A power conversion device comprising: A main conversion circuit, comprising the silicon carbide semiconductor device according to any one of claims 1 to 11, the main conversion circuit converting input power and outputting the power; a drive circuit that performs a cutoff operation by making the voltage of the gate electrode of the silicon carbide semiconductor device equal to the voltage of the source electrode, and outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device; as well as The control circuit outputs a control signal for controlling the drive circuit to the drive circuit.

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