Optical semiconductor device

Abstract

The optical semiconductor device comprises: a submount substrate (7) having a GND pattern (13), a capacitor mounting pattern (14) and a signal line (11) on the surface, and a GND pattern (19) on the back; an optical modulator (1) bonded to the surface of the GND pattern (13); a matching capacitor (4) having a back surface bonded to the surface of the capacitor mounting pattern (14), and the surface of the matching capacitor (4) being connected to the surface electrode of the optical modulator (1) via a lead (2a); a matching resistor (3) connecting the capacitor mounting pattern (14) and the GND pattern (13); and a protective resistor (6) connecting the signal line (11) connected to the surface electrode of the optical modulator (1) via a lead (2b) and the GND pattern (19) via the submount substrate (7) in the thickness direction of the board, thereby miniaturizing the submount substrate.

Description

Technical Field

[0001] The present application relates to an optical semiconductor device. Background Art

[0002] Conventional optical semiconductor devices have adopted a structure in which a capacitor is inserted between a light emitting element and ground (GND) to reduce power consumption. In this case, a protective resistor is connected in parallel with the capacitor to prevent charge from being accumulated (see, for example, Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2012-88348 (Paragraphs 0010, Figure 1 )

[0004] However, in order to adopt this structure, an area for providing a protection resistor on the sub-mount substrate is required, and therefore there is a problem that it is difficult to achieve miniaturization of the sub-mount substrate while ensuring an area for providing the protection resistor. Summary of the invention

[0005] The present application discloses an optical semiconductor device that solves the above-mentioned problems and has an object to provide a sub-mount substrate that is provided with a protective resistor and is also miniaturized.

[0006] The optical semiconductor device disclosed in the present application is characterized in that it comprises: a substrate having a first GND pattern, a first conductive pattern and a second conductive pattern on the surface, and a second GND pattern on the back surface; a light-emitting element bonded to the surface of the above-mentioned first GND pattern; a capacitor having a back surface bonded to the surface of the above-mentioned second conductive pattern, and a surface connected to the surface electrode of the above-mentioned light-emitting element via a first lead; a first resistor connecting the above-mentioned second conductive pattern and the above-mentioned first GND pattern; and a second resistor connecting the above-mentioned first conductive pattern and the above-mentioned second GND pattern connected to the surface electrode of the above-mentioned light-emitting element via the second lead in the direction of the plate thickness via the above-mentioned substrate.

[0007] According to the present application, it is possible to provide a protective resistor while miniaturizing the sub-mount substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is an equivalent circuit diagram showing the electrical structure of the optical semiconductor device according to the first embodiment.

[0009] Figure 2 (a) and (b) are a plan view and a cross-sectional view showing the structure of the optical semiconductor device according to the first embodiment.

[0010] Figure 3 (a) and (b) are an equivalent circuit diagram and a plan view showing other structures of the optical semiconductor device according to the first embodiment.

[0011] Figure 4 (a) and (b) are plan views showing other structures of the optical semiconductor device according to the first embodiment.

[0012] Figure 5 This is a graph showing the relationship between attenuation and frequency.

[0013] Figure 6 This is a graph showing the relationship between attenuation and resistance value.

[0014] Figure 7 This is a graph showing the relationship between attenuation and frequency.

[0015] Figure 8 It is a plan view showing another structure of the optical semiconductor device according to the first embodiment.

[0016] Fig. 9 It is a plan view showing another structure of the optical semiconductor device according to the first embodiment.

[0017] Fig.10 (a) and (b) are a plan view and a cross-sectional view showing the structure of the optical semiconductor device according to the second embodiment.

[0018] Fig.11 This is a graph showing the relationship between attenuation and frequency.

[0019] Fig.12 (a) and (b) are a plan view and a side view showing the structure of the optical semiconductor device according to the third embodiment. DETAILED DESCRIPTION

[0020] Implementation Method 1

[0021] As optical semiconductor devices have multiple wavelengths, there are increasing cases where one optical semiconductor device is equipped with a plurality of light emitting elements 1. In the first embodiment, an example is shown in which two light emitting elements 1 are mounted on one optical semiconductor device.

[0022] Figure 1 1 is an equivalent circuit diagram showing the electrical structure of the optical semiconductor device 101 according to the first embodiment of the present application. Figure 1As shown, the optical semiconductor device 101 is a TOSA (Transmitter Optical Sub-Assembly), which has a light-emitting element 1, a matching resistor 3 as a first resistor, a capacitor 4, and a protection resistor 6 as a second resistor. The anode of the light-emitting element 1 is connected to the drive circuit 5, and the cathode is connected to GND. The matching resistor 3 and the capacitor 4, and the protection resistor 6 are connected in parallel with the light-emitting element 1. The light-emitting element 1 is, for example, an EML-LD (Electro-absorption Modulator Laser Diode). The light-emitting element 1 emits light according to a high-frequency modulated electrical signal supplied from the drive circuit 5. In addition, the matching resistor 3 and the capacitor 4 may also be configured from the drive circuit 5 side.

[0023] Figure 2 (a) and Figure 2 (b) is a diagram showing the structure of the optical semiconductor device 101 according to the first embodiment of the present application. Figure 2 (a) is a top view, Figure 2 (b) is Figure 2 (a) is a cross-sectional view taken along the AA line. Figure 2 (a) and Figure 2 As shown in (b), the optical semiconductor device 101 is provided with a sub-mount substrate 7 on a carrier substrate 8. The carrier substrate 8 is made of CuW, for example, and the sub-mount substrate 7 is made of AlN, for example. Conductive patterns 21 and 22 are provided on both sides of the carrier substrate 8. A second GND pattern 19 is provided on the back side of the sub-mount substrate 7. The conductive pattern 21 of the carrier substrate 8 and the second GND pattern 19 of the sub-mount substrate 7 are joined by solder or the like. A first conductive pattern 11 and a first GND pattern 13 separated from each other are provided on the surface of the sub-mount substrate 7. Among them, gold plating is applied to the surfaces of the first conductive pattern 11 and the first GND pattern 13. In addition, in the present embodiment 1, a light receiving element is not mounted, but a light receiving element may also be mounted.

[0024] The light emitting element 1 is bonded to a back electrode (not shown) of the light emitting element 1 by solder or the like on a first GND pattern 13 formed on the surface of the sub-mount substrate 7. The surface electrode (not shown) of the light emitting element 1 is connected to a surface electrode (not shown) of the capacitor 4 and the first conductive pattern 11 via a lead 2a as a first lead and a lead 2b as a second lead, respectively.

[0025] The capacitor 4 is joined to a back electrode (not shown) of the capacitor 4 by solder or the like on a second conductive pattern 14 formed on the surface of the sub-mount substrate 7. The surface electrode (not shown) of the capacitor 4 is connected to a surface electrode (not shown) of the light emitting element 1 via a lead 2a. The second conductive pattern 14 for mounting the capacitor 4 is connected to the first GND pattern 13 via a matching resistor 3, the capacitor 4 is connected in parallel to the light emitting element 1, and the capacitor 4 is connected in series to the matching resistor 3.

[0026] The matching resistor 3 connects the second conductive pattern 14 on which the capacitor 4 is mounted to the first GND pattern 13 joined to the light emitting element 1, and is connected in parallel with the light emitting element 1. The resistance value of the matching resistor 3 is set to 50Ω in order to achieve impedance matching, but it can be changed from 50Ω in order to fine-tune the characteristics.

[0027] The optical semiconductor device 101 according to the first embodiment of the present application is characterized in that the protective resistor 6 is composed of a second resistor 16a in which a resistor body is filled in a hole. Figure 2 (a) and Figure 2 As shown in (b), the second resistor 16a is formed, for example, by filling a hole provided in the sub-mount substrate 7 with a resistor paste. The second resistor 16a filled with a resistor body penetrates the sub-mount substrate 7 and connects the connection end 11a connected to the surface electrode (not shown) of the light-emitting element 1 via the lead 2b, which is close to the side of the sub-mount substrate 7 and connected to the outside, and the second GND pattern 19 formed on the back of the sub-mount substrate 7, and is connected in parallel with the light-emitting element 1, the matching resistor 3, and the capacitor 4. As a result, the charge is not charged to the surface electrode of the capacitor 4, and can escape to the second GND pattern 19 on the back of the sub-mount substrate 7 through the second resistor 16a filled with a resistor body.

[0028] The first conductive pattern 11 is connected to the modulation electric signal wiring 12a through the lead 17. The first GND pattern 13 is connected to the GND wiring 12b through the lead 18. In addition, the GND wiring 12b is provided on both sides of the modulation electric signal wiring 12a, and the first GND pattern 13 is provided on both sides of the first conductive pattern 11, respectively constituting a coplanar waveguide. The modulation electric signal wiring 12a and the first conductive pattern 11 transmit the modulated electric signal from the driving circuit 5. In addition, the leads 2a, 2b, 17, and 18 are, for example, gold leads, but may also be strip-shaped gold wires or the like.

[0029] In addition, in the present embodiment 1, a case where two light emitting elements are mounted is shown, but the present invention is not limited to this. The number of light emitting elements 1 may be one or three or more. Figure 3 (a) and Figure 3 (b) shows an example of an optical semiconductor device 101 in which one light emitting element is mounted. Figure 3 (a) is the equivalent circuit diagram, Figure 3 (b) is a top view.

[0030] In the first embodiment, the second resistor 16a is provided at the external connection end 11a of the first conductive pattern 11, but the present invention is not limited thereto. Figure 4 As shown in (a), a second resistor 16b may be provided at the connection end 11b connected to the light emitting element 1. Figure 4 As shown in (b), the second resistor 16c may be provided at the connection portion 11c between the connection end 11b connected to the light emitting element 1 and the external connection end 11a of the first conductive pattern 11. In particular, the connection ends 11a and 11b at both ends of the first conductive pattern 11 are enlarged in pattern area to form a capacitance component in order to offset the inductance component of the lead wire. Therefore, the second resistors 16a and 16b can be easily connected to the first conductive pattern 11, so there is also an effect of improving productivity.

[0031] In the first embodiment, the second resistor 16a is used as the protection resistor 6. Figure 5 The simulation results showing the relationship between the attenuation of the signal and the frequency when the resistance value of the resistor filled in the second resistor 16a is changed are shown. In the simulation, the resistance value of the matching resistor 3 is set to 50Ω and the capacitance of the capacitor 4 is set to 10nF. The horizontal axis represents the frequency of the signal input to the optical semiconductor device 101. The vertical axis represents the amount of attenuation when the optical semiconductor device 101 transmits the signal. Line I, line II, line III and line IV respectively represent the results when the resistance value of the second resistor 16a is 2.1kΩ, 1.1kΩ, 0.3kΩ, and 0.1kΩ. For example, if the value of the vertical axis is -3dB, the strength of the signal becomes half. The attenuation at 0GHz varies according to the resistance value, and the smaller the resistance value, the greater the variation.

[0032] Figure 6 The simulation result shows the relationship between the attenuation of the signal at 0 GHz and the resistance value when the resistance value of the resistor filled in the second resistor 16a is changed. The horizontal axis shows the resistance value of the resistor filled in the second resistor 16a. The vertical axis shows the attenuation amount when the optical semiconductor device 101 transmits the signal at 0 GHz. There is a tendency that the smaller the resistance value, the greater the attenuation. Therefore, in order to obtain the desired characteristics, the resistance value is preferably 0.3 kΩ or more.

[0033] Figure 7The simulation results show the relationship between the attenuation amount of the signal and the frequency in each case of the second resistor 16a (resistance value 0.1 kΩ) provided at the external connection end 11a of the first conductive pattern 11, the second resistor 16b (resistance value 0.1 kΩ) provided at the connection end 11b connected to the light emitting element 1, and the second resistor 16c (resistance value 0.1 kΩ) provided at the connection portion 11c of the connection end 11b connected to the light emitting element 1 and the external connection end 11a of the first conductive pattern 11. In the simulation, the resistance value of the matching resistor 3 is set to 50Ω, and the capacitance of the capacitor 4 is set to 10nF. The horizontal axis represents the frequency of the signal input to the optical semiconductor device 101. The vertical axis represents the amount of attenuation when the optical semiconductor device 101 transmits the signal. Line V, line VI, and line VII represent the results in the cases of the second resistor 16a, the second resistor 16b, and the second resistor 16c, respectively. According to Figure 7 , it was confirmed that the second resistor 16a and the second resistor 16b provided at the end of the first conductive pattern 11 have the same characteristics, but the second resistor 16c provided at the center of the first conductive pattern 11 has a large attenuation in the high frequency band above 20GHz, and the high frequency performance is high when provided at the end of the first conductive pattern 11. When it is configured near the center, since there is only an area of ​​the line width of the first conductive pattern 11, if the position of the second resistor 16c is offset, it will contact the adjacent first GND pattern 13 and become a poor characteristic. Therefore, the second resistor 16c requires high manufacturing accuracy.

[0034] Furthermore, the capacitor 4 does not need to be disposed on the sub-mount substrate 7 , and may be disposed on the carrier substrate 8 . Figure 8 The capacitor 4 is shown in a form provided on a carrier substrate 8 . Figure 8 The carrier substrate 8 shown is, for example, AlN. A conductive pattern 21 and a second conductive pattern 14 are provided on the carrier substrate 8. The back electrode (not shown) of the capacitor 4 is joined to the second conductive pattern 14 by solder or the like. Here, since the back electrode of the capacitor 4 needs to be separated from the GND pattern, the conductive pattern 21 and the second conductive pattern 14 also need to be separated. The surface electrode (not shown) of the capacitor 4 and the upper surface electrode of the light-emitting element 1 are connected by a lead 2a. A conductive pattern 28 is provided on the sub-mounting substrate 7. The conductive pattern 28 is connected to the second conductive pattern 14 by a lead 27. By setting this structure, the sub-mounting substrate 7 can be further miniaturized.

[0035] in addition, Fig. 9 Another embodiment in which the capacitor 4 is provided on the carrier substrate 8 is shown. Fig. 9The carrier substrate 8 shown is, for example, CuW. The back electrode of the capacitor 4 is joined to the conductive pattern 21 by solder or the like. A conductive pattern 29, a conductive pattern 31, and a matching resistor 3 are provided on the sub-mount substrate 7, and the matching resistor 3 is connected between the conductive pattern 29 and the conductive pattern 31. The surface electrode (not shown) of the light emitting element 1 is connected to the conductive pattern 29 by a lead 2a. The conductive pattern 31 is connected to the surface electrode (not shown) of the capacitor 4 by a lead 30. By setting this structure, it is possible to further miniaturize the sub-mount substrate 7.

[0036] As described above, the optical semiconductor device 101 involved in the present embodiment 1 comprises: a sub-mounting substrate 7, on the surface of which a first GND pattern 13, a first conductive pattern 11 and a second conductive pattern 14 are provided, and on the back side a second GND pattern 19 is provided; a light-emitting element 1, which is bonded to the surface of the first GND pattern 13; a capacitor 4, on the back side of which a surface of the second conductive pattern 14 is bonded, and the surface is connected to the surface electrode of the light-emitting element 1 via a lead 2a; a matching resistor 3, which connects the second conductive pattern 14 and the first GND pattern 13; and a protection resistor 6, which passes through the sub-mounting substrate 7 and connects the first conductive pattern 11, which is connected to the surface electrode of the light-emitting element 1 via a lead 2b, and the second GND pattern 19. Since the protection resistor 6 (second resistor 16a) is formed by the resistor body filled in the hole provided in the sub-mounting substrate 7, the sub-mounting substrate can be miniaturized while providing the protection resistor.

[0037] Implementation Method 2

[0038] In the first embodiment, the protection resistor 6 is formed of a resistor element filled in the hole. However, in the second embodiment, a case where the protection resistor 6 is formed of a resistor paste applied to the side wall of the hole will be described.

[0039] Fig.10 (a) and Fig.10 (b) is a diagram showing the structure of an optical semiconductor device 102 according to Embodiment 2 of the present application. Fig.10 (a) is a top view, Fig.10 (b) is Fig.10 (a) is a cross-sectional view taken along the AA line.

[0040] The optical semiconductor device 102 according to the second embodiment of the present application is characterized in that the protective resistor 6 is composed of a second resistor 26a formed of a resistor paste applied to the side wall of a hole provided in the sub-mount substrate 7. Fig.10 (a) and Fig.10As shown in (b), in the optical semiconductor device 102, the second resistor 26a penetrates the sub-mount substrate 7 to connect the connection end 11a of the first conductive pattern 11 connected to the surface electrode (not shown) of the light emitting element 1 via the lead 2b, which is close to the side of the sub-mount substrate 7 and connected to the outside, and the second GND pattern 19 formed on the back of the sub-mount substrate 7. The other structures of the optical semiconductor device 102 involved in the second embodiment are the same as those of the optical semiconductor device 101 in the first embodiment, and the same reference numerals are given to the corresponding parts, and their descriptions are omitted.

[0041] In the second embodiment, the second resistor 26a is used as the protection resistor 6. Fig.11 The simulation results showing the relationship between the attenuation of the signal and the frequency when the resistance value of the resistor paste applied to the second resistor 26a is 0.1kΩ are shown. In the simulation, the resistance value of the matching resistor 3 is set to 50Ω, and the capacitance of the capacitor 4 is set to 10nF. The horizontal axis represents the frequency of the signal input to the optical semiconductor device 102. The vertical axis represents the amount of attenuation when the optical semiconductor device 102 transmits the signal. Line VIII is the result in the case of the second resistor 26a of this embodiment 2, and line IX represents the result in the case of the second resistor 16a (resistance value 0.1kΩ) of embodiment 1 as a comparison. As shown in FIG. Fig.11 As shown, the second resistor 26a of the second embodiment has an inductance component in addition to the effect of the second resistor 16a of the first embodiment, and thus generates peaking, thereby having an effect of improving characteristics in the frequency band of 5 GHz to 25 GHz.

[0042] In addition, in the second embodiment, although the second resistor 26a is provided at the external connection end 11a of the first conductive pattern 11, it is not limited to this. It is also possible to use a second resistor 26b provided at the connection end 11b connected to the light emitting element 1. In addition, it is also possible to use a second resistor 26c provided at the connection portion 11c between the connection end 11b connected to the light emitting element 1 and the external connection end 11a of the first conductive pattern 11. In particular, the connection ends 11a and 11b at both ends of the first conductive pattern 11 expand the pattern area to form a capacitance component in order to offset the inductance component of the lead. Therefore, it is possible to easily connect the second resistor to the first conductive pattern 11, so there is also an effect of improving productivity.

[0043] As described above, the optical semiconductor device 102 involved in the present embodiment 2 comprises: a sub-mounting substrate 7, on the surface of which a first GND pattern 13, a first conductive pattern 11 and a second conductive pattern 14 are provided, and on the back side a second GND pattern 19 is provided; a light-emitting element 1, which is bonded to the surface of the first GND pattern 13; a capacitor 4, on the back side of which a surface of the second conductive pattern 14 is bonded, and the surface is connected to the surface electrode of the light-emitting element 1 via a lead 2a; a matching resistor 3, which connects the second conductive pattern 14 and the first GND pattern 13; and a protective resistor 6, which passes through the sub-mounting substrate 7 and connects the first conductive pattern 11, which is connected to the surface electrode of the light-emitting element 1 via a lead 2b, and the second GND pattern 19. Since the protective resistor 6 (second resistor 26a) is formed by a resistor paste applied to the side wall of a hole provided in the sub-mounting substrate 7, the sub-mounting substrate can be miniaturized while providing the protective resistor.

[0044] Implementation 3

[0045] In the first and second embodiments, the protection resistor 6 is formed to penetrate the sub-mount substrate 7 , but in the third embodiment, a case where the protection resistor 6 is formed along the side surface of the sub-mount substrate 7 will be described.

[0046] Fig.12 (a) and Fig.12 (b) is a diagram showing the structure of an optical semiconductor device 103 according to Embodiment 3 of the present application. Fig.12 (a) is a top view, Fig.12 (b) is Fig.12 (a) is a side view from the direction BB.

[0047] The optical semiconductor device 103 according to the third embodiment of the present application is characterized in that the protective resistor 6 is composed of a second resistor 36 formed of a metallized layer provided on the side surface of the sub-mount substrate 7. Fig.12 (a) and Fig.12 As shown in (b), in the optical semiconductor device 103, the second resistor 36 connects the connection end 11a for external connection on the side of the sub-mounting substrate 7 of the first conductive pattern 11 connected to the surface electrode (not shown) of the light-emitting element 1 via the lead 2b along the side of the sub-mounting substrate 7, and the second GND pattern 19 formed on the back side of the sub-mounting substrate 7. The other structures of the optical semiconductor device 103 involved in the third embodiment are the same as those of the optical semiconductor device 101 in the first embodiment, and the same reference numerals are given to corresponding parts, and their descriptions are omitted.

[0048] As described above, according to the optical semiconductor device 103 involved in the third embodiment, there are: a submount substrate 7, on which the first GND pattern 13, the first conductive pattern 11 and the second conductive pattern 14 are provided on the surface, and the second GND pattern 19 is provided on the back surface; a light emitting element 1 is bonded to the surface of the first GND pattern 13; a capacitor 4, on which the back surface is bonded to the surface of the second conductive pattern 14, and the surface is connected to the surface electrode of the light emitting element 1 via the lead 2a; a matching resistor 3, which connects the second conductive pattern 14 and the first GND pattern 13; and a protection resistor 6, which connects the first conductive pattern 11 and the second GND pattern 19 connected to the surface electrode of the light emitting element 1 via the lead 2b along the side surface of the submount substrate 7. Since the protection resistor 6 (second resistor 36) is formed by the metallization layer provided on the side surface of the submount substrate 7, the submount substrate can be miniaturized while providing the protection resistor. In addition, by providing the second resistor 36 on the side surface, the metallization pattern on the first conductive pattern 11 is not uneven, and the productivity during the lead connection can be improved.

[0049] This application describes various illustrative embodiments and examples, but the various features, methods and functions described in one or more embodiments are not limited to the application of a specific embodiment, and can be applied to the embodiments alone or in various combinations. Therefore, countless unillustrated variations can be imagined within the technical scope disclosed in the specification of this application. For example, it includes the case where at least one constituent element is deformed, added or omitted, and the case where at least one constituent element is extracted and combined with constituent elements of other embodiments.

[0050] Description of Reference Numerals

[0051] 1…light-emitting element; 2a, 2b…leads; 3…matching resistor; 4…capacitor; 6…protective resistor; 7…secondary mounting substrate; 11…first conductive pattern; 13…first GND pattern; 14…second conductive pattern; 16a, 16b, 16c…second resistor; 19…second GND pattern; 26a, 26b, 26c…second resistor; 36…second resistor; 101, 102, 103…optical semiconductor device.

Claims

1. An optical semiconductor device, characterized in that: have: A substrate having a first GND pattern, a first conductive pattern and a second conductive pattern on a surface thereof and a second GND pattern on a back surface thereof; A light emitting element, bonded to a surface of the first GND pattern; A capacitor, the back surface of which is bonded to the surface of the second conductive pattern, and the surface of which is connected to the surface electrode of the light-emitting element via a first lead; a first resistor, connecting the second conductive pattern and the first GND pattern; as well as The second resistor connects the second GND pattern and the first conductive pattern connected to the surface electrode of the light emitting element via the second lead through the substrate in the thickness direction of the substrate.

2. The optical semiconductor device according to claim 1, wherein The second resistor is connected through the substrate.

3. The optical semiconductor device according to claim 2, wherein: The second resistor is formed of a resistor element filled in a hole provided in the substrate.

4. The optical semiconductor device according to claim 2, wherein The second resistor is formed of a resistor body coated on a side wall of a hole provided in the substrate.

5. The optical semiconductor device according to claim 3 or 4, characterized in that The second resistor is connected to an end portion of the first conductive pattern for connection to the outside.

6. The optical semiconductor device according to claim 3 or 4, characterized in that The second resistor is connected to the connection end portion of the first conductive pattern connected to the surface electrode of the light emitting element.

7. The optical semiconductor device according to claim 3 or 4, characterized in that: The second resistor is connected to a connection portion between an end portion of the first conductive pattern connected to the outside and an end portion of the first conductive pattern connected to a surface electrode of the light emitting element.

8. The optical semiconductor device according to claim 1, wherein The second resistor is connected along a side surface of the substrate.

9. The optical semiconductor device according to claim 8, wherein The second resistor is formed by a metallization layer disposed on a side surface of the substrate.

10. The optical semiconductor device according to any one of claims 1 to 4, 8 and 9, characterized in that The resistance value of the second resistor is greater than or equal to 0.3 kΩ.

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