Mirror chamfering method of wafer, wafer manufacturing method and wafer

Abstract

A method for mirror chamfering a wafer is provided that can suppress the sharp corners at the boundary between the main surface and the chamfered surface of the wafer. The present invention is a method for mirror chamfering a wafer (W) by mirror-polishing the chamfered surface of the wafer (W) using a polishing pad (4, 6), characterized in that the angle (α1, α2) formed by the main surface of the polishing pad (4, 6) and the main surface of the wafer (W) is set to be less than a target value of the chamfering angle during chamfering.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 201980026464.0, application date September 12, 2019, and invention name “Mirror chamfering method of chip, manufacturing method of chip and chip”. Technical Field

[0002] The present invention relates to a mirror chamfering method for a wafer, a wafer manufacturing method and the wafer. Background Art

[0003] Semiconductor devices are manufactured by chamfering, polishing, etching, double-side grinding, mirror chamfering, and finish grinding wafers cut from single crystal ingots, and then forming electrical circuits on the main surfaces of the wafers in a device process. "Chamfering" refers to the process of creating a chamfered surface on the periphery of the wafer using a chamfering grindstone, etc., while "mirror chamfering" refers to the process of polishing the chamfered surface to a mirror finish using a polishing pad.

[0004] Patent Document 1 provides mirror chamfering of a chamfered wafer using the following method. Specifically, the chamfered surface of the wafer, which has been chamfered so that the angle between the main surface of the wafer and the chamfered surface is approximately 22°, is pressed against a polishing pad to provide mirror chamfering such that the angle between the main surface of the polishing pad and the main surface of the wafer is approximately 45°.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 11-188590.

[0006] However, wafers mirror-chamfered using the method of Patent Document 1 have been found to have the potential for dust generation due to contact between the wafer chuck and the grooves within the wafer container during the final wafer cleaning process and beyond. Furthermore, careful observation of the mirror-chamfered wafer surface revealed sharp corners at the boundary between the main surface and the chamfered surface, potentially contributing to dust generation. Summary of the Invention

[0007] In view of the above problems, the present invention aims to provide a method for mirror chamfering a wafer that can suppress the sharp corners at the boundary between the main surface and the chamfered surface of the wafer. Furthermore, the present invention aims to provide a method for manufacturing a wafer that can suppress the sharp corners at the boundary between the main surface and the chamfered surface of the wafer. Furthermore, the present invention aims to provide a wafer that can suppress the sharp corners at the boundary between the main surface and the chamfered surface of the wafer.

[0008] The gist of the present invention for solving the above-mentioned problems is as follows.

[0009] (1) A method for mirror chamfering a wafer by mirror-polishing the chamfered surface of the wafer with the aid of a polishing pad, characterized in that an angle α formed by a main surface of the polishing pad and a main surface of the wafer is set to be less than a target value of an angle θ formed by the main surface of the wafer and the chamfered surface during chamfering of the wafer.

[0010] (2) In the wafer mirror chamfering method described in (1) above, the target value of the angle θ is set to 22° or more and 26° or less.

[0011] (3) In the wafer mirror chamfering method described in (2) above, the angle α is set to be greater than or equal to 20°.

[0012] (4) In the mirror chamfering method of a chip described in any one of (1) to (3) above, a mirror chamfering device for a chip is used, and the mirror chamfering device for the chip comprises a table and a polishing pad mounting fixture, the table adsorbs and holds the chip and is rotatable, the polishing pad mounting fixture has the polishing pad attached to an inclined surface inclined relative to the main surface of the chip, and is swung along the inclined surface, so that the angle formed by the inclined surface of the polishing pad mounting fixture and the main surface of the chip is consistent with the angle α, and the polishing pad mounting fixture is swung along the inclined surface while the polishing pad is always in contact with the chamfered surface of the chip rotated by the table.

[0013] (5) In the mirror chamfering method of a chip described in any one of (1) to (3) above, a mirror chamfering device for a chip is used, and the mirror chamfering device for the chip comprises a table and a polishing pad mounting fixture, the table being capable of adsorbing and holding the chip, the polishing pad mounting fixture having the polishing pad attached to an inclined surface inclined relative to the main surface of the chip, and being capable of swinging along the inclined surface so that the angle formed by the inclined surface of the polishing pad mounting fixture and the main surface of the chip is consistent with the angle α, and the polishing pad mounting fixture is swung along the inclined surface and moved circumferentially along the chip while the polishing pad is always in contact with the chamfered surface of the chip held on the table.

[0014] (6) In the mirror chamfering method of a wafer described in (4) or (5), the diameter of the stage is reduced from a surface adsorbed on one side of the wafer to a surface opposite to the surface.

[0015] (7) In the mirror chamfering method of a wafer described in (6) above, the angle formed by the side surface of the stage and the surface of the stage adsorbed to the wafer is 20° or less.

[0016] (8) A method for manufacturing a wafer, comprising mirror-chamfering the wafer using the method for mirror-chamfering a wafer according to any one of (1) to (7).

[0017] (9) A wafer characterized in that the angularity of the boundary between the front surface and the chamfer and / or the angularity of the boundary between the back surface and the chamfer is 180 μm or more.

[0018] (10) In the wafer described in (9) above, the angularity of the boundary between the front surface and the chamfer and / or the angularity of the boundary between the back surface and the chamfer is 200 μm or more.

[0019] (11) In the wafer described in (9) or (10) above, ESFQRmax is 45 nm or less.

[0020] Effects of the Invention

[0021] According to the present invention, a wafer can be obtained in which sharp corners at the boundary between the main surface and the chamfered surface of the wafer are suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic cross-sectional view showing the shape of the peripheral edge portion of a wafer that can be used in the wafer mirror chamfering method according to one embodiment of the present invention.

[0023] Figure 2A 1 is a schematic diagram of a wafer mirror chamfering apparatus 100 that can be used in a wafer mirror chamfering method according to an embodiment of the present invention.

[0024] Figure 2B yes Figure 2A An enlarged view of part I of FIG.

[0025] Figure 3A This is a diagram explaining a method for quantifying sharp angles.

[0026] Figure 3B This is a diagram explaining a method for quantifying sharp angles.

[0027] Figure 4 This is a graph showing the relationship between the angle α1 formed between the main surface of the polishing pad and the main surface of the front side of the wafer, and the angularity of the boundary between the front side and the chamfer in each of the inventive examples and comparative examples.

[0028] Figure 5 This is a graph showing the relationship between the angle α1 formed between the main surface of the polishing pad and the main surface of the front side of the wafer and ESFQRmax in each of the inventive examples and comparative examples.

[0029] Figure 6 This is a graph illustrating the relationship between the angularity and ESFQRmax. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0031] First, a wafer that can be used for the mirror chamfering method of the wafer of this embodiment will be described. Figure 1 The peripheral portion of the chip has an end face E perpendicular to the main face M1 on the front side and the main face M2 on the back side of the chip, an upper chamfered face C1 connecting the main face M1 on the front side of the chip and the end face E, and a lower chamfered face C2 connecting the main face M2 on the back side of the chip and the end face E. Figure 1 A wafer having the shape shown can be obtained by, for example, chamfering a wafer cut from a single crystal ingot and then performing double-side polishing.

[0032] Figure 1 In the figure, θ1 is the angle formed by the main surface M1 on the front side of the wafer and the upper chamfered surface C1 (hereinafter referred to as the "upper chamfer angle"). θ2 is the angle formed by the main surface M2 on the back side of the wafer and the lower chamfered surface C2 (hereinafter referred to as the "lower chamfer angle"). That is, in this specification, the angle on the front side of the angle θ formed by the main surface and the chamfered surface of the wafer is defined as θ1, and the angle on the back side is defined as θ2. In the chamfering of the wafer, the target values ​​of θ1 and θ2 can be set to be greater than 22° and less than 26°. The target value is determined by the groove shape of the chamfering foil or the like used in the chamfering. However, due to the wear of the groove of the fixture, the grinding allowance in double-sided grinding, etc., there is a possibility that θ1 and θ2 of the wafer used for mirror chamfering may deviate from the target value by ±1°. In addition, if the target values ​​of θ1 and θ2 are larger than 26°, the chamfer angle of the wafer before mirror chamfering becomes larger, so the effect of suppressing the edge angle becomes smaller. The target values ​​of θ1 and θ2 are more preferably set to 22° or more and 23° or less, and further preferably set to 22°.

[0033] t is the thickness of the peripheral portion of the chip, which can be set to 760μm~790μm. A1 is the upper chamfer width, A2 is the lower chamfer width, and A1 and A2 can both be set to 200μm~450μm. B1 is the upper chamfer thickness, B2 is the lower chamfer thickness, and B1 and B2 can both be set to 80μm~240μm. R1 is the curvature radius of the upper chamfer, R2 is the curvature radius of the lower chamfer, and R1 and R2 can both be set to 200~250μm. BC is the length of the end face in the chip thickness direction, which can be set to 300μm~600μm. In addition, Figure 1 In the description, a wafer with BC-≠0 is used. However, a wafer that can be used for the mirror chamfering method of the wafer in this embodiment may also be a so-called arc-shaped wafer with BC=0.

[0034] Next, a description will be given of a wafer mirror chamfering apparatus 100 that can be used in the wafer mirror chamfering method according to the present embodiment.

[0035] Reference Figure 2AThe mirror chamfering device 100 includes a table 2 that absorbs and holds the chip W and is capable of rotating, a first polishing pad 4 that is arranged at a position capable of contacting the upper chamfered surface C1 of the chip W, a second polishing pad 6 that is arranged at a position capable of contacting the lower chamfered surface C2 of the chip W, and a slurry supply mechanism 8 that supplies slurry to the peripheral portion of the chip W.

[0036] The first polishing pad 4 is adhered to the inclined surface 10A of the first polishing pad mounting fixture 10. The first polishing pad mounting fixture 10 can swing along the inclined surface 10A, and accordingly, the first polishing pad 4 can also swing along the inclined surface 10A. In addition, the second polishing pad 6 is adhered to the inclined surface 12A of the second polishing pad mounting fixture 12. The second polishing pad mounting fixture 12 can swing along the inclined surface 12A, and accordingly, the second polishing pad 6 can also swing along the inclined surface 12A. Here, the first and second polishing pad mounting fixtures 10 and 12 are arranged at positions facing each other across the wafer W when looking down at the mirror chamfering device 100. In addition, the mechanism for causing the first and second polishing pad mounting fixtures 10 and 12 to swing is not particularly limited, and for example, a sliding mechanism driven by an air pressure cylinder or a servo motor can be used.

[0037] The first and second polishing pads 4 and 6 preferably use polishing pads with a compression rate of 1.5% to 7.5%, and more preferably use polishing pads with a compression rate of 3.5% to 7.5%. Polishing pads with these compression rates are harder than polishing pads used in general mirror chamfering (compression rate: 9% or more), which can suppress over-polishing and prevent the portions of the upper and lower chamfered surfaces C1 and C2 close to the end surface E from remaining unpolished. The material of such a polishing pad can be a general material, for example, a polyurethane non-woven fabric can be used. In addition, the thickness of the first and second polishing pads 4 and 5 can be 1.0 to 2.0 mm.

[0038] The table 2 preferably has a diameter that decreases from the surface adsorbed to the wafer W toward the surface opposite to the surface adsorbed to the wafer W, so that the first and second polishing pad mounting jigs 10 and 12 do not contact the first and second polishing pad mounting jigs 10 and 12 and the first and second polishing pads 4 and 6 during swinging. Specifically, the angle β formed between the side surface of the table 2 and the surface adsorbed to the wafer W is preferably 20° or less. Furthermore, the diameter of the surface adsorbed to the wafer W is preferably 4 to 10 mm smaller than the diameter of the wafer W. This prevents interference between the table 2 and the first and second polishing pads 4 and 6 without reducing the adsorption force to the wafer W.

[0039] Next, an example of a method for mirror chamfering a wafer according to the present embodiment that can be performed using the mirror chamfering apparatus 100 will be described.

[0040] Reference Figure 2ABy rotating the table 2 to rotate the wafer W, the first polishing pad 4 is constantly in contact with the upper chamfered surface C1 of the wafer W, and the second polishing pad 6 is constantly in contact with the lower chamfered surface C2 of the wafer W. The first polishing pad mounting jig 10 is then swung along the inclined surface 10A, and the second polishing pad mounting jig 12 is then swung along the inclined surface 12A. Furthermore, a load is applied to the first and second polishing pad mounting jigs 10 and 12 in a direction from the periphery toward the center of the wafer W, and the slurry supplied from the slurry supply mechanism 8 is supplied toward the periphery of the wafer W. Thus, the first polishing pad 4 is also swung along the inclined surface 10A, and the second polishing pad 6 is also swung along the inclined surface 12A. As a result, the upper chamfered surface C1 is mirror-polished by the first polishing pad 4, and the lower chamfered surface C2 is mirror-polished by the second polishing pad 6. The rotation speed of the wafer W can be 300 to 1500 rpm, the load applied to the first and second polishing pad mounting jigs can be 30 to 60 N, and the swing speed can be 1 to 8 mm / sec.

[0041] Also refer to Figure 1 In this embodiment, it is important that, at the mirror chamfering, the angle α1 formed between the main surface of the first polishing pad 4 and the main surface M1 on the front side of the wafer W is set to be less than the target value of the upper chamfer angle θ1 when the wafer W is chamfered, and / or the angle α2 formed between the main surface of the second polishing pad 6 and the main surface M2 on the back side of the wafer W is set to be less than the target value of the lower chamfer angle θ2 when the wafer W is chamfered. The significance of this technology is described below. In addition, Figure 2B , which shows an example of the magnitude relationship between θ1 and α1, where α1 is smaller than θ1.

[0042] In conventional mirror chamfering, the angle α formed between the main surface of the polishing pad and the main surface of the wafer is set to be much larger than the target value for chamfering angle θ. This is because it is believed that if the angle α formed between the main surface of the polishing pad and the main surface of the wafer is too small, the area at the center of the wafer, which is more than several hundred μm away from the boundary between the main surface of the wafer and the chamfered surface, will be over-polished. Indeed, conventional methods can suppress over-polishing. However, the inventors of the present invention have discovered that, according to conventional methods, the amount of polishing at the boundary between the main surface of the wafer and the chamfered surface is insufficient, resulting in sharp corners at this boundary, and thus a new technical problem such as the possibility of dust generation in the process after the final cleaning of the wafer. Furthermore, further research has found that even if the angle α formed between the main surface of the polishing pad and the main surface of the wafer is smaller than conventional, over-polishing is not a problem. Furthermore, it has been found that by setting the angle α formed between the main surface of the polishing pad and the main surface of the wafer to be below the target value for chamfering angle θ, over-polishing can be suppressed to an acceptable level, and sharp corners can also be suppressed. The present embodiment is based on these findings.

[0043] The "edges" in this specification can be quantified by the following method. First, use a known laser microscope to scan the surface shape of the chip in the radial direction. Specifically, the scanning direction is set to the x-axis, and the position 400 to 600 μm from the outer edge of the main surface of the chip to the center side is set as the starting point of the scan (the origin of the x-coordinate), and the position 100 to 300 μm from the outer edge of the chip to the center side is set as the end point of the scan. Thus, we get Figure 3A The profile curve (f(x)) is shown. Next, using a known analytical method, the profile curve (f(x)) is differentiated twice with respect to x, and thus Figure 3A The quadratic differential curve (f)(x) shown in FIG. Next, the peak with the largest depth of the quadratic differential curve (f)(x)) is identified (hereinafter referred to as the "maximum peak"). Then, the depth of the maximum peak is set to d, and the x coordinates of the intersection of y = -d × 60% and y = f)(x) are set to x1 and x2. Then, using a known analytical method, such as Figure 3B As shown in FIG, the contour curve (f(x)) of the region x1≤x≤x2 is fitted with a circle. The radius of the fitted circle is used as an indicator of the angularity. That is, the larger the radius of the fitted circle, the more the angularity of the boundary between the main surface and the chamfered surface of the wafer is suppressed. In addition, when scanning the main surface of the front side of the wafer, the fitted circle is used as an indicator of the angularity of the boundary between the main surface and the chamfered surface of the wafer. Figure 3B The radius of the circle shown (unit: μm) is called the angularity of the front-chamfer boundary. On the other hand, when scanning the main surface of the back side of the wafer, the radius of the circle fitted by the same method as the angularity of the front-chamfer boundary is called the angularity of the back-chamfer boundary. Figure 3A In FIG. 2B , the vibration of f(x) in the region of x ≥ 230 μm is noise that is unrelated to the surface shape of the wafer.

[0044] Reference Figure 1 , in the chamfering of the wafer, the target values ​​of the upper chamfer angle θ1 and the lower chamfer angle θ2 can be set to 22° or more and 26° or less, respectively. θ1 and θ2 are more preferably 22° or more and 23° or less, and further preferably 22°. In this case, also refer to Figure 2ABy making the angle α1 less than 22°, the angularity of the front surface and the chamfered boundary portion can be made greater than 180 μm. In addition, by making the angle α2 less than 22°, the angularity of the back surface and the chamfered boundary portion can be made greater than 180 μm. Furthermore, by making the angle α1 less than 21°, even if the chamfer angle of the wafer used for mirror chamfering is uneven, the angularity can be effectively suppressed. For example, when the chamfer angle is uneven and θ1 = 22° ± 1°, the angularity of the front surface and the chamfered boundary portion can be made greater than 200 μm. In addition, by making the angle α2 less than 21°, even if the chamfer angle of the wafer used for mirror chamfering is uneven and θ2 = 22° ± 1°, the angularity of the back surface and the chamfered boundary portion can be made greater than 200 μm.

[0045] From the perspective of suppressing over-polishing on the front side of the wafer W to an acceptable level, the angle α1 is preferably set to 20° or greater. Furthermore, from the perspective of suppressing over-polishing on the back side of the wafer W to an acceptable level, the angle α2 is preferably set to 20° or greater. Furthermore, "over-polishing to an acceptable level" means that the ESFQRmax is 45 nm or less.

[0046] The "ESFQRmax" in this specification is determined based on the ESFQR (Edge Site Frontleast Quares Range) specified in SEMI standard M67. Specifically, an annular region extending from the outer edge of the wafer in the radial direction of 1 to 30 mm is divided into 72 sectors along the circumference of the wafer. The sum of the absolute values ​​of the maximum displacement on the positive side and the maximum displacement on the negative side from the reference plane, obtained by least squares analysis of the thickness distribution within each sector, is defined as the ESFQR for each sector. The maximum of these ESFQRs is defined as ESFQRmax.

[0047] That is, if α1 is set to 20° or more and 22° or less, ESFQRmax can be 45nm or less and the angularity of the front and chamfered boundary portion can be 180μm or more. If α1 is set to 20° or more and 21° or less, ESFQRmax can be 45nm or less and the angularity of the front and chamfered boundary portion can be 200μm or more. Similarly, if α2 is set to 20° or more and 22° or less, ESFQRmax can be 45nm or less and the angularity of the back and chamfered boundary portion can be 180μm or more. If α2 is set to 20° or more and 21° or less, ESFQRmax can be 45nm or less and the angularity of the back and chamfered boundary portion can be 200μm or more.

[0048] The above description has been made of the mirror chamfering method of a wafer according to the present invention using the present embodiment as an example. However, the present invention is not limited thereto and can be modified appropriately within the scope of the claims.

[0049] For example, the mirror chamfering device described below can be used to mirror chamfer the wafer. That is, a mirror chamfering device for the wafer is used, which includes a table that can hold the wafer by adsorbing it, and a polishing pad mounting fixture that has a polishing pad attached to an inclined surface that is inclined relative to the main surface of the wafer and can swing along the inclined surface. Furthermore, the angle formed by the inclined surface of the polishing pad mounting fixture and the main surface of the wafer and the angle α formed by the main surface of the polishing pad and the main surface of the wafer are made consistent, and the polishing pad mounting fixture is swung along the inclined surface and moved along the circumferential direction of the wafer while the polishing pad is always in contact with the chamfered surface of the wafer held on the table. That is, this mirror chamfering method is similar to the method of moving the polishing pad mounting fixture along the circumferential direction of the wafer while the wafer is fixed without being rotated. Figure 2A The chamfering method shown is different. In addition, in addition to the reference to Figure 2A The content of the description.

[0050] Next, an example of a method for manufacturing a wafer of the present invention that can be performed using the above-mentioned method for mirror chamfering a wafer will be described.

[0051] The manufacturing method of the wafer of the present embodiment includes using the above-mentioned wafer chamfering method to mirror chamfer the wafer. Specifically, first, a wafer is obtained by slicing a single crystal ingot. Then, the wafer is chamfered using a known grindstone for chamfering to obtain a wafer with a chamfered surface. Then, known polishing and etching are performed on the wafer with the chamfered surface. Then, double-sided grinding of the wafer is performed using a known double-sided grinding device. Then, mirror chamfering of the wafer is performed using the above-mentioned mirror chamfering method. Then, finish grinding of the wafer is performed using a known single-sided grinding device. Then, the wafer is cleaned using a known cleaning method. The wafer is manufactured in this way. In addition, the grinding amount in the finish grinding is very small, so the angularity of the front and chamfered boundary, the angularity of the back and chamfered boundary, and the value of ESFQRmax remain unchanged.

[0052] According to this embodiment, a wafer with suppressed sharp corners can be obtained.

[0053] The wafer manufacturing method of the present invention has been described above using the present embodiment as an example. However, the present invention is not limited thereto and can be modified appropriately within the scope of the claims.

[0054] Example

[0055] (Invention Example 1)

[0056] A silicon wafer with a diameter of 300 mm cut from a single crystal silicon ingot was subjected to chamfering, polishing, etching, and double-side grinding in this order to obtain 5 wafers having a diameter of 300 mm. Figure 1 A silicon wafer with the shape shown. The wafer was chamfered using a #2000 resin grindstone, with target values ​​of θ1 and θ2 set to 22°. Furthermore, t = 776 μm, A1 = 240 μm, A2 = 240 μm, B1 = 213 μm, B2 = 213 μm, BC = 350 μm, R1 = 230 μm, and R2 = 230 μm.

[0057] Next, use Figure 2A The mirror chamfering apparatus shown performs mirror chamfering on each silicon wafer under the following conditions.

[0058] α1, α2: 22°

[0059] β: 20°

[0060] Type of 1st and 2nd polishing pads: Polyurethane non-woven fabric

[0061] Compression rate of the first and second polishing pads: 5%

[0062] Thickness of the 1st and 2nd polishing pads: 1.5mm

[0063] Swing speed of the 1st and 2nd polishing pad mounting fixtures: 4mm / sec

[0064] Load: 37~40N

[0065] Chip rotation speed: 1300rpm

[0066] Type of slurry: Colloidal silica

[0067] (Invention Example 2)

[0068] Five silicon wafers for mirror chamfering were obtained by the same method as in Inventive Example 1. The same method as in Inventive Example 1 was used except that the mirror chamfering of each silicon wafer was performed with α1 = α2 = 21°.

[0069] (Invention Example 3)

[0070] Five silicon wafers for mirror chamfering were obtained by the same method as in Inventive Example 1. The same method as in Inventive Example 1 was used except that the mirror chamfering of each silicon wafer was performed with α1 = α2 = 20°.

[0071] (Invention Example 4)

[0072] Five silicon wafers for mirror chamfering were obtained by the same method as in Inventive Example 1. The same method as in Inventive Example 1 was used except that the mirror chamfering of each silicon wafer was performed with α1 = α2 = 19°.

[0073] (Comparative Example 1)

[0074] Five silicon wafers for mirror chamfering were obtained in the same manner as in Invention Example 1. Except that the mirror chamfering of each silicon wafer was performed with α1 = α2 = 30°, it was the same as in Invention Example 1.

[0075] (Comparative Example 2)

[0076] Five silicon wafers for mirror chamfering were obtained in the same manner as in Invention Example 1. Except that the mirror chamfering of each silicon wafer was performed with α1 = α2 = 25°, it was the same as in Invention Example 1.

[0077] (Comparative Example 3)

[0078] Five silicon wafers for mirror chamfering were obtained in the same manner as in Invention Example 1. Except that the mirror chamfering of each silicon wafer was performed with α1 = α2 = 23°, it was the same as in Invention Example 1.

[0079] (Evaluation Method)

[0080] For each silicon wafer obtained in each invention example and comparative example, the chamfer edge, over-polishing, and light point defects (LPD, Light Point Defect) were evaluated by the following evaluation method.

[0081] <Evaluation of Chamfer Edge>

[0082] According to the described method, the chamfer edge amount at the boundary between the front surface and the chamfer (hereinafter simply referred to as "chamfer edge amount") was calculated to evaluate the chamfer edge. Figure 4 The evaluation results are shown. In addition, for the laser microscope, Keyence Corporation's VK-X200 was used. The position 400 μm from the outer peripheral end of the front surface of the wafer toward the center side was set as the starting point of scanning, and the position 100 μm from the outer peripheral end of the wafer toward the center side was set as the end point of scanning. In addition, the least squares method was used for fitting.

[0083] <Evaluation of Over-Polishing>

[0084] The ESFQR of each silicon wafer was measured using a flatness measurement device (KLA-Tencor Corporation: Wafersight 2), and ESFQRmax was calculated according to the above method. Figure 5 The measurement results are shown.

[0085] <Evaluation of LPD>

[0086] After each silicon wafer obtained in each invention example and comparative example was clamped 1000 times (emphasis on evaluation) with the wafer chuck of the wafer transfer robot arm, it was measured in DCO mode using a laser particle counter (KLA-Tencor Corporation, SP-3), and the number of LPDs with a size of 35 nm or more was obtained.

[0087] (Explanation of evaluation results)

[0088] Reference Figure 4 、 5 In comparative examples 1 to 3, the angle α1 is set larger than the target value of the angle θ1, so the ESFQRmax is reduced to less than 45nm, which can suppress over-polishing. However, the angularity is less than 180μm, and the angularity cannot be suppressed. On the other hand, in inventive examples 1 to 3, regardless of whether the angle α1 is set below the target value of the angle θ1, the ESFQRmax can be reduced to less than 45nm, and over-polishing can be suppressed to an allowable level. Furthermore, in inventive example 1, the angularity is greater than 180μm, which can suppress the angularity. In inventive examples 2 and 3, the angularity is greater than 200μm, which can further suppress the angularity. In addition, in inventive example 4, the angularity is good, but the angle α1 is too small, so the ESFQRmax exceeds 45nm, and over-polishing cannot be suppressed to an allowable level. In addition, the angularity can also be suppressed on the back side. Reference Figure 6 If the angularity is greater than 230 μm, ESFQRmax will be greater than 45 nm, which is not preferable. Therefore, the angularity is preferably 230 μm or less.

[0089] Regarding LPD, in Comparative Examples 1-3, the sharpness was less than 180 μm, resulting in 2 to 10 LPDs per wafer. This was due to dust generation during chucking. In contrast, in Inventive Example 1, the sharpness was greater than 180 μm, resulting in 1 LPD per wafer, suppressing dust generation. Furthermore, in Inventive Examples 2-4, the sharpness was greater than 200 μm, resulting in 0.1 to 0.7 LPDs per wafer, further suppressing dust generation.

[0090] Industrial applicability

[0091] According to the present invention, a wafer can be obtained in which sharp corners at the boundary between the main surface and the chamfered surface of the wafer are suppressed.

[0092] Description of Reference Numerals

[0093] M1 Main surface on the front side

[0094] M2 Main surface on the back side

[0095] C1 upper chamfer surface

[0096] C2 lower chamfer surface

[0097] E end face

[0098] θ1 upper chamfer angle

[0099] θ2 lower chamfer angle

[0100] 100 Mirror chamfering device

[0101] 2 units

[0102] 4. 1st polishing pad

[0103] 6. Second polishing pad

[0104] 8 Slurry supply mechanism

[0105] 10 1st polishing pad mounting jig

[0106] 10A Inclined surface

[0107] 12 Second polishing pad mounting jig

[0108] 12A Inclined surface

[0109] α1 Angle between the main surface of the first polishing pad and the main surface of the front side of the wafer

[0110] α2 Angle between the main surface of the second polishing pad and the main surface of the back side of the wafer

[0111] β is the angle between the side of the stage and the side of the stage that is adsorbed to the wafer.

[0112] W chip.

Claims

1. A wafer, characterized in that: The scanning direction is set as the x-axis, and the position 400 to 600 μm from the outer edge of the main surface of the wafer to the center is set as the starting point of the scan, and the position 100 to 300 μm from the outer edge of the wafer to the center is set as the end point of the scan. The surface shape of the wafer is scanned in the radial direction to obtain the profile curve f(x). The profile curve f(x) is differentiated twice with x to obtain a quadratic differential curve f"(x). The peak with the largest depth of the quadratic differential curve f"(x) is determined, and the depth of the largest peak is set to d. The x coordinates of the intersection of y = -d × 60% and y = f"(x) are set to x1 and x2. The contour curve f(x) in the region x1≤x≤x2 is fitted with a circle, and the radius of the fitted circle is used as an indicator of the angularity. When scanning the main surface of the front side of the wafer, the radius of the fitted circle is called the angularity of the boundary between the front side and the chamfer. When scanning the main surface of the back side of the wafer, the radius of the fitted circle is called the angularity of the boundary between the back side and the chamfer. The angularity of the boundary between the front surface and the chamfer and / or the angularity of the boundary between the back surface and the chamfer is 200 μm or more. ESFQRmax is below 45nm, The upper chamfer width A1 and the lower chamfer width A2 of the wafer are both 200 μm to 450 μm.

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