Optical proximity correction method and system, mask, apparatus, and storage medium

Abstract

An optical proximity correction method and system, a mask, a device and a storage medium, the optical proximity correction method comprising: providing an initial layout layer, the initial layout layer comprising a first pattern, the first pattern having a first size along a critical dimension direction; splitting the first pattern into a second pattern along the critical dimension direction, the second pattern constituting a combined pattern identical to the corresponding first pattern, the second pattern having a second size along the critical dimension direction, the second size being less than or equal to a preset size; and splitting the initial layout layer into a plurality of layout layers, the second pattern corresponding to each first pattern being placed in different layout layers respectively. The present application improves the accuracy of the structure corresponding to the first pattern formed on the wafer, and is conducive to improving the accuracy of the pattern conversion of the layout layer corrected by the optical proximity correction method.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and more particularly to an optical proximity correction method and system, a photomask, an apparatus, and a storage medium. Background Technology

[0002] To transfer a pattern from a photomask to the surface of a silicon wafer, the process typically involves an exposure step, a development step following the exposure step, and an etching step following the development step. In the exposure step, light passes through the light-transmitting areas of the photomask and shines onto the silicon wafer coated with photoresist, causing a chemical reaction in the photoresist. In the development step, the different solubility of the developer in the photoresist and the unphotoresisted photoresist creates a photolithographic pattern, transferring the pattern from the photomask to the photoresist. In the etching step, the silicon wafer is etched based on the photolithographic pattern formed by the photoresist layer, further transferring the pattern from the photomask onto the silicon wafer.

[0003] However, as device dimensions shrink, the difference between the pattern on the chip surface and the original photomask pattern increases after photolithography. To avoid inconsistencies between the chip pattern and the mask pattern caused by optical proximity effect, the current solution is usually to perform optical proximity correction (OPC) on the mask pattern, and then perform pattern transfer based on the corrected mask pattern. The OPC correction process typically requires a mask manufacturing rule check to ensure final pattern convergence and mask fabrication accuracy. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide an optical proximity correction method and system, mask, device and storage medium to improve the effect of optical proximity correction.

[0005] To address the aforementioned problems, embodiments of the present invention provide an optical proximity correction method, comprising: providing an initial plate layer, the initial plate layer including a first graphic, the first graphic having a first dimension along a critical dimension direction; splitting the first graphic into second graphics along the critical dimension direction, the combined graphic formed by the second graphics being identical to the corresponding first graphic, the second graphic having a second dimension along the critical dimension direction, the second dimensions being all less than or equal to a preset dimension; splitting the initial plate layer into multiple plate layers, and placing the second graphic corresponding to each first graphic in different plate layers.

[0006] Accordingly, embodiments of the present invention also provide an optical proximity correction system, comprising: a plate layer providing module for providing an initial plate layer, the initial plate layer including a first graphic, the first graphic having a first dimension along a critical dimension direction; a graphic splitting module for splitting the first graphic into second graphics along the critical dimension direction, the combined graphic formed by the second graphics being identical to the corresponding first graphic, the second graphics having a second dimension along the critical dimension direction, the second dimensions being all less than or equal to a preset dimension. The plate layer splitting module is used to split the initial plate layer into multiple plate layers, placing the second graphic corresponding to each first graphic in different plate layers.

[0007] Accordingly, embodiments of the present invention also provide a photomask, including a pattern obtained using the optical proximity correction method provided in embodiments of the present invention.

[0008] Accordingly, embodiments of the present invention also provide an apparatus including at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the optical proximity correction method provided in embodiments of the present invention.

[0009] Accordingly, embodiments of the present invention also provide a storage medium storing one or more computer instructions, which are used to implement the optical proximity correction method provided in embodiments of the present invention.

[0010] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0011] In the optical proximity correction method provided in this embodiment of the invention, the first pattern is split into second patterns along the critical dimension direction. The combination of the second patterns maintains the shape of the first pattern. The second patterns have a second dimension along the critical dimension direction, and the second dimension is less than or equal to a preset dimension. The first pattern is first split into multiple second patterns, such that the second dimension of the second pattern along the critical dimension direction is less than or equal to the preset dimension. Then, the multiple second patterns corresponding to each first pattern are placed in different plate layers, thereby converting the optical proximity correction processing of the first pattern into the optical proximity correction processing of multiple second patterns. This helps to reduce the correction error caused by the excessive size of the first pattern along the critical dimension direction. Moreover, when etching the structure corresponding to the first pattern on the wafer, the structure corresponding to multiple second patterns can be formed by etching, thereby forming the structure corresponding to the first pattern. The critical dimension of the structure corresponding to the second pattern is smaller, which helps to reduce the situation where the etching error is easily generated due to the excessive size of the first pattern along the critical dimension direction. This helps to improve the accuracy of the structure corresponding to the first pattern formed on the wafer, and further helps to improve the accuracy of pattern conversion using the plate layer corrected by the optical proximity correction method.

[0012] In the optional scheme, the second dimensions of each of the second graphics corresponding to the same graphic to be processed are equal, which helps to reduce the diversity of graphics in the plate layer, makes the shape of the second graphics more uniform, reduces the difficulty of optical proximity correction of the second graphics, and thus helps to improve the effect of optical proximity correction of the second graphics.

[0013] In an optional scheme, if there is an overlap between adjacent second patterns corresponding to the same pattern to be processed, then when the structure corresponding to the pattern to be processed is formed by etching multiple structures corresponding to the second patterns on the wafer, it is beneficial to avoid the situation where the structures corresponding to adjacent second patterns are separated due to etching errors in the critical dimension direction, thereby helping to ensure the integrity of the structure corresponding to the pattern to be processed formed on the wafer. Attached Figure Description

[0014] Figure 1 This is a flowchart of an optical proximity correction method;

[0015] Figures 2 to 3 This is a schematic diagram of the steps in an optical proximity correction method.

[0016] Figure 4 This is a flowchart of an embodiment of the optical proximity correction method of the present invention;

[0017] Figures 5 to 9 This is a schematic diagram of each step in one embodiment of the optical proximity correction method of the present invention;

[0018] Figure 10 This is a functional block diagram of an embodiment of the optical proximity correction system of the present invention;

[0019] Figure 11 This is a hardware structure diagram of an embodiment of the device provided by the present invention. Detailed Implementation

[0020] The effectiveness of optical proximity correction needs improvement. This paper analyzes the reasons why the effectiveness of optical proximity correction needs improvement by combining an optical proximity correction method.

[0021] Figure 1 This is a flowchart of an optical proximity correction method. (Refer to reference.) Figures 2 to 3 The diagram illustrates the steps in the optical proximity correction method, which includes:

[0022] refer to Figure 2 , Figure 2 This is a schematic diagram corresponding to step s1. Step s1: Provide an initial version layer 10, which includes the target graphic 11.

[0023] refer to Figure 3 , Figure 3 This is a schematic diagram corresponding to step s2. Step s2: Perform plate layer splitting process, split the initial plate layer 10 into multiple plate layers (not shown), and place each target graphic 10 on one of the plate layers respectively.

[0024] For example, such as Figure 3 As shown, taking the initial version layer 10 as an example of splitting it into four version layers, the initial version layer 10 is split into a first version layer, a second version layer, a third version layer, and a fourth version layer.

[0025] In the semiconductor field, the dimensions of a pattern along the critical dimension direction have a significant impact on the pattern. During optical proximity correction processing, when the target pattern 11 is along the critical dimension direction (e.g., ...), the dimensions of the pattern along the critical dimension direction have a significant impact on the pattern. Figure 2 When the size w1 (as shown in the Y direction) is too large, it is easy to cause a large correction error. When etching the structure corresponding to the target pattern 11 on the wafer, it is also easy to cause a large etching error due to the large size w1 of the target pattern 11, thus affecting the accuracy of forming the structure corresponding to the target pattern 11 on the wafer.

[0026] To address the technical problem, embodiments of the present invention provide an optical proximity correction method. (Reference) Figure 4 The flowchart of an embodiment of the optical proximity correction method of the present invention is shown.

[0027] In this embodiment, the optical proximity correction method includes the following basic steps:

[0028] Step S1: Provide an initial layer, which includes a first graphic having a first dimension along the critical dimension direction;

[0029] Step S2: Along the critical dimension direction, split the first graphic into the second graphic. The combined graphic formed by the second graphic is the same as the corresponding first graphic. The second graphic has a second dimension along the critical dimension direction. The second dimension is less than or equal to the preset dimension.

[0030] Step S3: Split the initial plate layer into multiple plate layers, and place the multiple second graphics corresponding to each first graphic into different plate layers.

[0031] The first pattern is first split into multiple second patterns, ensuring that the second dimension of each second pattern along the critical dimension direction is less than or equal to a preset dimension. Then, the multiple second patterns corresponding to each first pattern are placed in different lithography layers. This transforms the optical proximity correction process for the first pattern into an optical proximity correction process for multiple second patterns. This helps reduce correction errors caused by excessive size of the first pattern along the critical dimension direction. Furthermore, when etching the structure corresponding to the first pattern on the wafer, the structure corresponding to the first pattern can be formed by etching the structures corresponding to multiple second patterns. This helps reduce the large etching errors caused by excessive size of the first pattern along the critical dimension direction, thereby improving the accuracy of the structure corresponding to the first pattern formed on the wafer. This, in turn, helps improve the accuracy of pattern conversion using lithography layers corrected by the optical proximity correction method.

[0032] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Figures 5 to 9 This is a schematic diagram of each step in one embodiment of the optical proximity correction method of the present invention.

[0034] refer to Figure 5 Step S1: Provide an initial version layer 100, which includes a first graphic 110. The first graphic 110 has a key dimension direction (e.g., ...). Figure 5 The first dimension L1 (shown in the Y direction).

[0035] The first graphic 110 in the initial layer 100 is the target graphic to be transferred onto the wafer. After optical proximity correction is performed on the first graphic 110, the resulting graphic is used to create a photomask, which is then used for photolithography to form a corresponding mask pattern on the wafer.

[0036] The first dimension L1 of the first pattern 110 along the critical dimension direction is the critical dimension (CD) of the first pattern 110. Therefore, the accuracy of the first dimension L1 has a significant impact on the structure corresponding to the first pattern 110 subsequently formed on the wafer.

[0037] As an example, in this embodiment, the initial layout layer 100 is a layout layer for forming an SRAM device, the first pattern 110 is a metal line cut pattern, and the key dimension direction is the extension direction of the metal line.

[0038] The metal wire cutting pattern is used to form a partition structure on the wafer, thereby cutting the metal wire. The size of the partition structure along the extension direction of the metal wire determines the size of each metal wire formed after the metal wire is cut. Therefore, in this embodiment, the critical dimension direction is the extension direction of the metal wire.

[0039] Furthermore, when the spacing between the metal wires that need to be broken is large along the direction of the metal wire extension, the size of the partition structure along the direction of the metal wire extension is large, and the first dimension L1 of the first pattern 110 used to form the partition structure is large. Therefore, in this embodiment, the method of splitting the first pattern 110 into multiple second patterns is adopted, and the structures corresponding to the multiple second patterns are formed by etching, thereby forming the partition structure corresponding to the first pattern 110 with a larger first dimension L1. This is beneficial to forming a partition structure with higher accuracy along the direction of the metal wire extension.

[0040] Continue to refer to Figure 5 In the step of providing the initial version layer 100, the first graphic 110 with a first size L1 greater than the preset size is selected as the graphic to be processed 120.

[0041] The dimensions along the critical dimension direction have a significant impact on the pattern, thus the first dimension L1 has a significant impact on the first pattern 110. When the first dimension L1 is too large, it can easily cause a large correction error. When etching the structure corresponding to the first pattern 110 on the wafer, the large first dimension L1 can also easily cause a large etching error, thereby affecting the accuracy of forming the structure corresponding to the first pattern 110 on the wafer.

[0042] In this embodiment, a first graphic 110 with a first size L1 greater than a preset size is selected as the graphic to be processed 120. This is to avoid large correction errors and large etching errors caused by the first size L1 being too large after the graphic to be processed 120 is processed.

[0043] It should be noted that the preset size should not be too large or too small. If the preset size is too large, it is easy for the first pattern 110 to be not selected as the pattern to be processed 120 when the first size L1 is less than or equal to the preset size but is still large. As a result, the first pattern 110 that needs to be processed may be missed when selecting patterns, which will lead to a large correction error in the optical proximity correction processing of the first pattern 110. The etching error will also be large when etching the structure corresponding to the first pattern 110 on the wafer. If the preset size is too small, the selection condition of the pattern is too strict, which will lead to the selection of the first pattern 110, which has a small first size L1 and does not need to be processed, as the pattern to be processed 120. This will increase the processing time for subsequent processing and cause unnecessary waste. Moreover, after the first pattern 110 is split into multiple second patterns, the second patterns have a second size along the critical size direction. The second size is less than or equal to the preset size. If the preset size is too small, it is easy to cause the second size to be too small, which will make the exposure of the second pattern difficult. Therefore, in this embodiment, the preset size is 55nm to 65nm.

[0044] Reference Figures 6 to 8 Step S2: Along the critical dimension direction, the first graphic 110 is split into the second graphic 210. The combined graphic formed by the second graphic 210 is the same as the corresponding first graphic 110. The second graphic 210 has a second dimension L2 along the critical dimension direction. The second dimension L2 is less than or equal to the preset dimension.

[0045] For the pattern 120 with a large first size L1, it needs to be split to avoid large correction errors and etching errors caused by an excessively large first size L1. For the first pattern 110 with a small first size L1, it can be left unsplit, thereby saving correction time and improving correction efficiency.

[0046] Therefore, in this embodiment, in the step of splitting the first graphic 110 into the second graphic 210 along the critical dimension direction, the graphic to be processed 120 is split into the second graphic 210, and the combined graphic formed by the second graphic 210 is the same as the corresponding graphic to be processed 120.

[0047] Accordingly, in this embodiment, there are multiple second patterns 210.

[0048] For ease of illustration, Figure 6 and Figure 7 for Figure 8 An enlarged view of the graphic to be processed, 120, within the dashed box.

[0049] The pattern 120 to be processed is first divided into multiple second patterns 210, such that the second dimension L2 of the second pattern 210 along the critical dimension direction is less than or equal to a preset dimension. Then, the multiple second patterns 210 corresponding to each pattern 120 to be processed are placed in different plate layers. This transforms the optical proximity correction processing of the pattern 120 to be processed into optical proximity correction processing of multiple second patterns 210. This helps to reduce the correction error caused by the excessive size of the pattern 120 to be processed along the critical dimension direction. Moreover, when etching the structure corresponding to the pattern 120 to be processed on the wafer, the structure corresponding to the pattern 120 to be processed can be formed by etching the structure corresponding to the multiple second patterns 210. This helps to reduce the large etching error caused by the excessive size of the pattern 120 to be processed along the critical dimension direction. This helps to improve the accuracy of the structure corresponding to the pattern 120 to be processed formed on the wafer, and thus helps to improve the accuracy of pattern conversion using plate layers corrected by the optical proximity correction method.

[0050] Specifically, refer to Figure 6 Along the critical dimension direction, the graphic 120 to be processed is divided multiple times, splitting the graphic 120 into multiple second graphics 210. The division process includes: setting a first dividing line 111 on the graphic 120 (e.g., ...). Figure 6 (as shown by the dashed line) and the second dividing line 112 (as shown by the dashed line) Figure 6 (As shown by the midpoint line), the extension directions of the first dividing line 111 and the second dividing line 112 (as shown by the midpoint line). Figure 6 (As shown in the X direction) are all perpendicular to the critical dimension direction, and the distance L0 between the first dividing line 111 and the second dividing line 112 is less than or equal to the preset dimension.

[0051] The first dividing line 111 and the second dividing line 112 are used to determine the two ends of the second graphic 210 in the key dimension direction, respectively. In each division process, the first dividing line 111 and the second dividing line 112 are used to delineate the area in the graphic 120 to be processed that constitutes the second graphic 210.

[0052] In order to make the combined graphic formed by multiple second graphics 210 identical to the corresponding graphic to be processed 120, the first dividing line 111 of the first dividing process and the second dividing line 112 of the last dividing process should be located at both ends of the graphic to be processed 120. Therefore, the first dividing line 111 of the first dividing process is flush with either end of the graphic to be processed 120 in the critical dimension direction, and the second dividing line 112 of the last dividing process is flush with the other end of the graphic to be processed 120 in the critical dimension direction.

[0053] In this process, the first dividing line 111 of the subsequent division process coincides with or is located between the first dividing line 111 and the second dividing line 112 of the previous division process. The second dividing line 112 of the subsequent division process is located on the same side as the first dividing line 111 and the second dividing line 112 of the previous division process. Thus, the regions divided by the two adjacent division processes are adjacent or have overlapping parts, reducing the probability that the region divided by the subsequent division process falls completely into the region divided by the previous division process. This helps to reduce unnecessary computational waste, thereby enabling a more sufficient and regular division of the graphic 120 to be processed along the key dimension direction, which is beneficial to improving the efficiency and effect of the division process.

[0054] Reference Figure 7 and Figure 8 The portion of the graphic to be processed 120 separated by the first dividing line 111 and the second dividing line 112 is taken as the second graphic 210.

[0055] In this embodiment, the distance L0 between the first dividing line 111 and the second dividing line 112 is less than or equal to a preset size, so that the second size L2 of the second graphic 210 formed by the division process along the key size direction is less than or equal to the preset size.

[0056] In this embodiment, in the step of splitting the graphic to be processed 120 into multiple second graphics 210 along the critical dimension direction, the second dimension L2 of each second graphic 210 corresponding to the same graphic to be processed 120 is equal.

[0057] The second dimension L2 of each second graphic 210 corresponding to the same graphic 120 is equal, which helps to reduce the diversity of graphics in the subsequent plate layer and makes the shape of the second graphic 210 more uniform. This helps to reduce the difficulty of optical proximity correction of the second graphic 210, thereby improving the effect of optical proximity correction of the second graphic 210.

[0058] In this embodiment, in the step of splitting the graphic to be processed 120 into multiple second graphics 210 along the critical dimension direction, among the multiple second graphics 210 corresponding to the same graphic to be processed 120, there is an overlapping portion between adjacent second graphics 210.

[0059] If there is an overlap between adjacent second patterns 210 corresponding to the same pattern to be processed 120, then when the structure corresponding to the pattern to be processed 120 is formed by etching multiple second patterns 210 on the wafer, it is beneficial to avoid the situation where the structure corresponding to the adjacent second patterns 210 is separated due to etching error in the critical dimension direction, thereby helping to ensure the integrity of the structure corresponding to the pattern to be processed 120 formed on the wafer.

[0060] In this embodiment, among the multiple second patterns 210 corresponding to the same pattern to be processed 120, the overlapping portion between adjacent second patterns 210 has a third dimension L3 along the critical dimension direction. The percentage of the third dimension L3 to the first dimension L1 should not be too large. If the percentage of the third dimension L3 to the first dimension L1 is too large, the overlapping portion of adjacent second patterns 210 will be too large. While ensuring that the second dimension L2 of each second pattern 210 is less than or equal to a preset dimension, this increases unnecessary computation time for subsequent optical proximity correction processing of the second patterns 210, resulting in unnecessary waste. Furthermore, when subsequent over-etching forms the structure corresponding to multiple second patterns 210 to form the structure corresponding to the pattern to be processed 120, the excessive overlap of the structures corresponding to adjacent second patterns 210 also causes unnecessary waste. Therefore, in this embodiment, the percentage of the third dimension L3 to the first dimension L1 is less than or equal to 2.5%.

[0061] It should be noted that when forming the structure corresponding to the pattern to be processed 120 by etching multiple second patterns 210 on the wafer to form the structure corresponding to the pattern to be processed, in order to reduce the probability of gaps between adjacent structures corresponding to the second patterns 210 in the critical dimension direction due to etching errors, and to ensure the integrity of the structure corresponding to the pattern to be processed 120 formed on the wafer, the percentage of the third dimension L3 to the first dimension L1 is appropriately increased when there is an overlapping portion between adjacent second patterns 210. In this embodiment, among the multiple second patterns 210 corresponding to the same pattern to be processed 120, the overlapping portion between adjacent second patterns 210 has a third dimension L3 along the critical dimension direction, and the third dimension L3 is 1% to 2.5% of the first dimension L1.

[0062] In this embodiment, among the multiple second graphics 210 corresponding to the same graphic 120 to be processed, the third dimension L3 of the overlapping portion between adjacent second graphics 210 along the key dimension direction is equal.

[0063] If the third dimension L3 of the overlapping portion between adjacent second patterns 210 is equal along the critical dimension direction, then when multiple structures corresponding to the second patterns 210 are etched on the wafer to form the structure corresponding to the pattern to be processed 120, the overlapping portion size of the structures corresponding to the adjacent second patterns 210 is equal. This helps to reduce the diversity of the overlapping portion of the structures corresponding to the adjacent second patterns 210, making the structure corresponding to the pattern to be processed 120 formed by the overlapping portion of the structures corresponding to the adjacent second patterns 210 more uniform, thereby helping to make the structure corresponding to the pattern to be processed 120 itself have better dimensional uniformity.

[0064] In other embodiments, in the step of splitting the graphic to be processed into multiple second graphics along the critical dimension direction, adjacent second graphics may also be adjacent to each other among the multiple second graphics corresponding to the same graphic to be processed.

[0065] refer to Figure 9 Step S3: Split the initial plate layer 100 into multiple plate layers (not shown), and place the second graphic 210 corresponding to each first graphic 110 into different plate layers.

[0066] Accordingly, in this embodiment, in the step of splitting the initial plate layer 100 into multiple plate layers, the second graphic 210 corresponding to each graphic to be processed 120 is placed in a different plate layer.

[0067] As an example, the initial plate layer 100 is split into multiple plate layers, including a first plate layer, a second plate layer, a third plate layer, and a fourth plate layer. The multiple second graphics 210 corresponding to each graphic to be processed 120 are placed in different plate layers, thereby ensuring that there is a large gap between adjacent second graphics 210 in each plate layer. This avoids the multiple second graphics 210 corresponding to the graphic to be processed 120 being too close together, which would affect the optical proximity correction effect. At the same time, it is beneficial to improve the subsequent photolithography quality of each second graphic row 210.

[0068] It should be noted that before splitting the initial plate layer 100 into multiple plate layers, the number of plate layers to be split is calculated based on the graphic arrangement of the initial plate layer 100 before splitting the graphic to be processed 120 into multiple second graphics 210, according to the minimum photolithographic spacing. In the step of splitting the initial plate layer 100 into multiple plate layers, it is only necessary to place the multiple second graphics 210 corresponding to the same graphic to be processed 120 into different plate layers calculated in advance. Thus, in this embodiment, it is not necessary to increase the number of plate layers. While improving the accuracy of graphic conversion using plate layers corrected by the optical proximity correction method, the probability of increasing additional costs is reduced.

[0069] Accordingly, the present invention also provides an optical proximity correction system. Figure 10 This is a functional block diagram of an embodiment of the optical proximity correction system of the present invention.

[0070] In this embodiment, the optical proximity correction system 50 includes: a plate layer providing module 501, used to provide an initial plate layer, the initial plate layer including a first graphic, the first graphic having a first dimension along the critical dimension direction; a graphic splitting module 502, used to split the first graphic into second graphics along the critical dimension direction, the combined graphic formed by the second graphics being the same as the corresponding first graphic, the second graphic having a second dimension along the critical dimension direction, the second dimensions being less than or equal to a preset dimension; and a plate layer splitting module 503, used to split the initial plate layer into multiple plate layers, placing the second graphic corresponding to each first graphic in different plate layers.

[0071] The first graphic in the initial pattern layer provided by the pattern layer providing module 501 is the target graphic to be transferred onto the wafer. After optical proximity correction is performed on the first graphic, the obtained graphic is used to create a photomask, thereby using the photomask to perform photolithography to form the corresponding photomask pattern on the wafer.

[0072] The first dimension L1 along the critical dimension direction of the first pattern is the critical dimension of the first pattern. Therefore, the accuracy of the first dimension L1 has a significant impact on the structure corresponding to the first pattern formed on the wafer.

[0073] As an example, in this embodiment, the initial layout layer is a layout layer used to form an SRAM device, the first pattern is a metal line cut pattern, and the critical dimension direction is the extension direction of the metal line.

[0074] The metal wire cutting pattern is used to form a partition structure on the wafer, thereby cutting the metal wire. The size of the partition structure along the extension direction of the metal wire determines the size of each metal wire formed after the metal wire is cut. Therefore, in this embodiment, the critical dimension direction is the extension direction of the metal wire.

[0075] Furthermore, when the spacing between the metal wires that need to be broken is large along the direction of the metal wire extension, the size of the partition structure along the direction of the metal wire extension is large, and the first dimension L1 of the first pattern used to form the partition structure is large. Therefore, in this embodiment, the method of splitting the first pattern into multiple second patterns is adopted, and the structures corresponding to the multiple second patterns are formed by etching, thereby forming the partition structure corresponding to the first pattern with a larger first dimension L1. This is beneficial to forming a partition structure with higher accuracy along the direction of the metal wire extension.

[0076] The layer module 501 is also used to select a first graphic whose first size L1 is greater than a preset size as the graphic to be processed.

[0077] The dimensions along the critical dimension direction have a significant impact on the pattern, thus the first dimension L1 has a significant impact on the first pattern. When the first dimension L1 is too large, it can easily cause a large correction error. Subsequently, when etching the structure corresponding to the first pattern on the wafer, the excessively large first dimension L1 can also easily cause a large etching error, thereby affecting the accuracy of forming the structure corresponding to the first pattern on the wafer.

[0078] In this embodiment, a first graphic with a first size L1 greater than a preset size is selected as the graphic to be processed. This is to avoid large correction errors and large etching errors caused by the first size L1 being too large after subsequent processing of the graphic.

[0079] It should be noted that the preset size should not be too large or too small. If the preset size is too large, it is easy for the first pattern to be not selected as the pattern to be processed when the first size L1 is less than or equal to the preset size but is still relatively large. This can easily lead to the omission of the first pattern that needs subsequent processing when selecting patterns, resulting in a still large correction error in the optical proximity correction processing of the first pattern. In the subsequent etching process to form the structure corresponding to the first pattern on the wafer, the etching error will also be relatively large. If the preset size is too small, the selection criteria for the pattern will be too stringent, causing the first pattern with a small first size L1 that does not need subsequent processing to be selected as the pattern to be processed, increasing the processing time for subsequent processing and causing unnecessary waste. Moreover, after the first pattern is split into multiple second patterns, the second patterns have a second size along the critical size direction, and the second size is less than or equal to the preset size. If the preset size is too small, it is easy for the second size to be too small in the subsequent formation, which will cause difficulties in the exposure of the second pattern. Therefore, in this embodiment, the preset size is 55nm to 65nm.

[0080] The graphic splitting module 502 is used to split the first graphic into the second graphic along the key dimension direction. The combined graphic formed by the second graphic is the same as the corresponding first graphic. The second graphic has a second dimension L2 along the key dimension direction. The second dimension L2 is less than or equal to a preset dimension.

[0081] For patterns with a large first size L1, in order to avoid large correction errors and etching errors caused by an excessively large first size L1, it is necessary to split them. For patterns with a small first size L1, they can be left unsplit, thereby saving correction time and improving correction efficiency.

[0082] Therefore, in this embodiment, the graphic to be processed is split into a second graphic along the critical dimension direction, and the combined graphic formed by the second graphic is the same as the corresponding graphic to be processed.

[0083] Accordingly, in this embodiment, there are multiple second graphics.

[0084] The pattern to be processed is first split into multiple second patterns, such that the second dimension L2 of the second pattern along the critical dimension direction is less than or equal to a preset dimension. Then, the multiple second patterns corresponding to each pattern to be processed are placed in different plate layers. This transforms the optical proximity correction processing of the pattern to be processed into optical proximity correction processing of multiple second patterns. This helps to reduce the correction error caused by the excessive size of the pattern to be processed along the critical dimension direction. Moreover, when etching the structure corresponding to the pattern to be processed on the wafer, the structure corresponding to the pattern to be processed can be formed by etching the structure corresponding to multiple second patterns. This helps to reduce the large etching error caused by the excessive size of the pattern to be processed along the critical dimension direction. This helps to improve the accuracy of the structure corresponding to the pattern to be processed formed on the wafer, and thus improves the accuracy of pattern conversion using plate layers corrected by the optical proximity correction method.

[0085] Specifically, along the critical dimension direction, the graphic to be processed is divided multiple times to split the graphic into multiple second graphics. The division process includes setting a first dividing line and a second dividing line on the graphic to be processed. The extension directions of the first dividing line and the second dividing line are both perpendicular to the critical dimension direction, and the distance L0 between the first dividing line and the second dividing line is less than or equal to a preset size.

[0086] The first dividing line and the second dividing line are used to determine the two ends of the second graphic in the key dimension direction, respectively. In each division process, the first dividing line and the second dividing line are used to delineate the region that constitutes the second graphic in the graphic to be processed.

[0087] In order to make the combined graphic composed of multiple second graphics identical to the corresponding graphic to be processed, the first dividing line of the first division process and the second dividing line of the last division process should be located at both ends of the graphic to be processed. Therefore, the first dividing line of the first division process is flush with either end of the graphic to be processed in the critical dimension direction, and the second dividing line of the last division process is flush with the other end of the graphic to be processed in the critical dimension direction.

[0088] In this process, the first dividing line of the subsequent division process coincides with or is located between the first and second dividing lines of the previous division process. The second dividing line of the subsequent division process is located on the same side as the first and second dividing lines of the previous division process. Thus, the regions divided by two adjacent division processes are adjacent or have overlapping parts, reducing the probability that the region divided by the subsequent division process falls completely into the region divided by the previous division process. This helps to reduce unnecessary computational waste, thereby enabling a more thorough and regular division of the graphic to be processed along the key dimension direction, which is beneficial to improving the efficiency and effectiveness of the division process.

[0089] The portion of the graphic to be processed separated by the first and second dividing lines is taken as the second graphic.

[0090] In this embodiment, the distance L0 between the first dividing line and the second dividing line is less than or equal to a preset size, so that the second size L2 of the second graphic formed by the division process along the key size direction is less than or equal to the preset size.

[0091] In this embodiment, in the step of splitting the graphic to be processed into multiple second graphics along the critical dimension direction, the second dimension L2 of each second graphic corresponding to the same graphic to be processed is equal.

[0092] The second dimension L2 of each second graphic corresponding to the same graphic to be processed is equal, which helps to reduce the diversity of graphics in the subsequent plate layer and makes the shape of the second graphic more uniform. This helps to reduce the difficulty of optical proximity correction of the second graphic, thereby improving the effect of optical proximity correction of the second graphic.

[0093] In this embodiment, in the step of splitting the graphic to be processed into multiple second graphics along the critical dimension direction, among the multiple second graphics corresponding to the same graphic to be processed, there is an overlapping part between adjacent second graphics.

[0094] If there is an overlap between adjacent second patterns corresponding to the same pattern to be processed, then when the structure corresponding to the pattern to be processed is formed by etching multiple structures corresponding to the second patterns on the wafer, it is beneficial to avoid the situation where the structures corresponding to the adjacent second patterns are separated due to etching errors in the critical dimension direction, thereby helping to ensure the integrity of the structure corresponding to the pattern to be processed formed on the wafer.

[0095] In other embodiments, in the step of splitting the graphic to be processed into multiple second graphics along the critical dimension direction, adjacent second graphics may also be adjacent to each other among the multiple second graphics corresponding to the same graphic to be processed.

[0096] In this embodiment, among multiple second patterns corresponding to the same pattern to be processed, the overlapping portion between adjacent second patterns has a third dimension L3 along the critical dimension direction. The percentage of the third dimension L3 to the first dimension L1 should not be too large. If the percentage of the third dimension L3 to the first dimension L1 is too large, the overlapping portion of adjacent second patterns will be too large. While ensuring that the second dimension L2 of each second pattern is less than or equal to a preset size, this increases unnecessary computation time for subsequent optical proximity correction processing of the second patterns, resulting in unnecessary waste. Furthermore, when subsequent over-etching forms structures corresponding to multiple second patterns to form the structure corresponding to the pattern to be processed, excessive overlap of structures corresponding to adjacent second patterns also causes unnecessary waste. Therefore, in this embodiment, the percentage of the third dimension L3 to the first dimension L1 is less than or equal to 2.5%.

[0097] It should be noted that when forming the structure corresponding to the pattern to be processed by etching multiple structures corresponding to the second patterns on the wafer, in order to reduce the probability of gaps between adjacent structures corresponding to the second patterns in the critical dimension direction due to etching errors, and to ensure the integrity of the structure corresponding to the pattern to be processed formed on the wafer, the percentage of the third dimension L3 to the first dimension L1 is appropriately increased when there is an overlap between adjacent second patterns. In this embodiment, among the multiple second patterns corresponding to the same pattern to be processed, the overlapping portion between adjacent second patterns has a third dimension L3 along the critical dimension direction, and the third dimension L3 is 1% to 2.5% of the first dimension L1.

[0098] In this embodiment, among the multiple second graphics corresponding to the same graphic to be processed, the third dimension L3 of the overlapping part between adjacent second graphics is equal along the key dimension direction.

[0099] If the third dimension L3 of the overlapping portion between adjacent second patterns is equal along the critical dimension direction, then when multiple structures corresponding to the second patterns are etched on the wafer to form the structure corresponding to the pattern to be processed, the overlapping portion of the structures corresponding to the adjacent second patterns is equal in size. This helps to reduce the diversity of the overlapping portion of the structures corresponding to the adjacent second patterns, making the structure corresponding to the pattern to be processed formed by the overlapping portion of the structures corresponding to the adjacent second patterns more uniform, thus helping to make the size uniformity of the structure corresponding to the pattern to be processed better.

[0100] The plate layer splitting module 503 is used to split the initial plate layer into multiple plate layers, and place the second graphic corresponding to each first graphic in different plate layers.

[0101] Accordingly, in this embodiment, the second graphic corresponding to each graphic to be processed is placed in a different plate layer.

[0102] As an example, the initial plate layer is split into multiple plate layers, including a first plate layer, a second plate layer, a third plate layer, and a fourth plate layer. The multiple second graphics corresponding to each graphic to be processed are placed in different plate layers, thereby ensuring that there is a large gap between adjacent second graphics in each plate layer. This avoids the multiple second graphics corresponding to the graphic to be processed being too close together, which would affect the optical proximity correction effect. At the same time, it is beneficial to improve the subsequent photolithography quality of each second graphic row.

[0103] It should be noted that before splitting the initial plate layer into multiple plate layers, the number of plate layers to be split is calculated based on the graphic layout of the initial plate layer before splitting the graphic to be processed into multiple second graphics, according to the minimum photolithographic spacing. In the step of splitting the initial plate layer into multiple plate layers, it is only necessary to place the multiple second graphics corresponding to the same graphic to be processed into different plate layers calculated in advance. Thus, in this embodiment, it is not necessary to increase the number of plate layers. This improves the accuracy of graphic conversion using plate layers corrected by the optical proximity correction method while reducing the probability of increasing additional costs.

[0104] Accordingly, the present invention also provides a photomask, comprising: a pattern obtained using the optical proximity correction method provided in the embodiments of the present invention.

[0105] As can be seen from the foregoing embodiments, the first pattern is first split into second patterns, such that the second dimension of the second pattern along the critical dimension direction is less than or equal to a preset dimension. Then, the second pattern corresponding to each first pattern is placed in different lithography layers. This transforms the optical proximity correction process for the first pattern into an optical proximity correction process for multiple second patterns. This helps to reduce the correction error caused by the excessive size of the first pattern along the critical dimension direction. Moreover, when etching the structure corresponding to the first pattern on the wafer, the structure corresponding to the first pattern can be formed by etching multiple structures corresponding to the second patterns. This helps to reduce the large etching error caused by the excessive size of the first pattern along the critical dimension direction. This helps to improve the accuracy of the structure corresponding to the first pattern formed on the wafer, and further helps to improve the accuracy of pattern conversion using the lithography layer corrected by the optical proximity correction method.

[0106] This invention also provides a device that can implement the optical proximity correction method provided in this invention by loading a program, as described above. An optional hardware structure of the terminal device provided in this invention can be as follows: Figure 11 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.

[0107] In this embodiment, the number of processor 01, communication interface 02, memory 03, and communication bus 04 is at least one, and the processor 01, communication interface 02, and memory 03 communicate with each other through communication bus 04. Communication interface 02 can be an interface of a communication module for network communication, such as the interface of a GSM module. Processor 01 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. Memory 03 may include high-speed RAM and may also include non-volatile memory (NVM), such as at least one disk storage device. Memory 03 stores one or more computer instructions, which are executed by processor 01 to implement the optical proximity correction method provided in this embodiment of the present invention.

[0108] It should be noted that the aforementioned terminal device may also include other devices (not shown) that may not be essential to understanding the content disclosed in the embodiments of the present invention; given that these other devices may not be essential for understanding the content disclosed in the embodiments of the present invention, the embodiments of the present invention will not describe them one by one.

[0109] This invention also provides a storage medium storing one or more computer instructions for implementing the optical proximity correction method provided in this invention.

[0110] In the optical proximity correction method provided in this embodiment of the invention, a first pattern is split into second patterns along the critical dimension direction. The combination of the second patterns maintains the shape of the first pattern. The second patterns have a second dimension along the critical dimension direction, and the second dimension is less than or equal to a preset dimension. The first pattern is first split into multiple second patterns, such that the second dimension of the second pattern along the critical dimension direction is less than or equal to the preset dimension. Then, the multiple second patterns corresponding to each first pattern are placed in different plate layers. This transforms the optical proximity correction processing of the first pattern into optical proximity correction processing of multiple second patterns. This helps to reduce the correction error caused by the excessive size of the first pattern along the critical dimension direction. Moreover, when etching the structure corresponding to the first pattern on the wafer, the structure corresponding to the first pattern can be formed by etching multiple structures corresponding to the second patterns. This helps to reduce the situation where the large etching error is easily generated due to the excessive size of the first pattern along the critical dimension direction. This helps to improve the accuracy of the structure corresponding to the first pattern formed on the wafer, and further helps to improve the accuracy of pattern conversion of the plate layer corrected by the optical proximity correction method.

[0111] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise stated, elements or features may be considered optional. Individual elements or features may be practiced without combination with other elements or features. Furthermore, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some constructions of any embodiment may be included in another embodiment and may be replaced by corresponding constructions of another embodiment. It will be apparent to those skilled in the art that claims in the appended claims that are not expressly referenced in each other may be combined to form embodiments of the present invention, or may be included as new claims in amendments made after the filing of this application.

[0112] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc. In a firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. Software code can be stored in memory units and executed by a processor. The memory units are located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0113] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0114] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An optical proximity correction method, characterized in that, include: An initial version layer is provided, the initial version layer including a first graphic, the first graphic having a first dimension along a key dimension direction; Along the key dimension direction, the first graphic is split into a second graphic, and the combined graphic formed by the second graphic is the same as the corresponding first graphic. The second graphic has a second dimension along the key dimension direction, and the second dimension is less than or equal to a preset dimension. The initial plate layer is split into multiple plate layers, and the second graphic corresponding to each of the first graphics is placed in a different plate layer.

2. The optical proximity correction method as described in claim 1, characterized in that, In the step of providing the initial layer, a first graphic whose first size is larger than the preset size is selected as the graphic to be processed; In the step of splitting the first graphic into the second graphic along the key dimension direction, the graphic to be processed is split into the second graphic, and the combined graphic formed by the second graphic is the same as the corresponding graphic to be processed; In the step of splitting the initial plate layer into multiple plate layers, the second graphic corresponding to each graphic to be processed is placed in a different plate layer.

3. The optical proximity correction method as described in claim 1, characterized in that, In the step of splitting the first graphic into the second graphic, there are multiple second graphics.

4. The optical proximity correction method as described in claim 2, characterized in that, In the step of splitting the graphic to be processed into the second graphic along the key dimension direction, the second dimensions of each of the second graphics corresponding to the same graphic to be processed are equal.

5. The optical proximity correction method as described in claim 2, characterized in that, In the step of splitting the graphic to be processed into the second graphic along the key dimension direction, the second graphics corresponding to the same graphic to be processed have overlapping parts between adjacent second graphics, or the adjacent second graphics are adjacent to each other.

6. The optical proximity correction method as described in claim 5, characterized in that, In the second graphic corresponding to the same graphic to be processed, there is an overlapping portion between adjacent second graphics, and the overlapping portion between adjacent second graphics has a third dimension along the direction of the key dimension, the third dimension being 1% to 2.5% of the first dimension.

7. The optical proximity correction method as described in claim 5, characterized in that, In the second graphic corresponding to the same graphic to be processed, there is an overlapping portion between adjacent second graphics, and the overlapping portion between adjacent second graphics has a third dimension along the direction of the key dimension, and the third dimension is equal.

8. The optical proximity correction method as described in claim 2, characterized in that, Along the key dimension direction, the graphic to be processed is divided multiple times to split the graphic into the second graphic. The division process includes: A first dividing line and a second dividing line are set on the graphic to be processed. The extension directions of the first dividing line and the second dividing line are both perpendicular to the key dimension direction, and the distance between the first dividing line and the second dividing line is less than or equal to the preset dimension. The portion of the graphic to be processed separated by the first dividing line and the second dividing line is used as the second graphic. In the first division process, the first dividing line is flush with either end of the graphic to be processed in the critical dimension direction. In the subsequent division process, the first dividing line coincides with or is located between the first and second dividing lines of the previous division process. The second dividing line of the subsequent division process is located on the same side as the first and second dividing lines of the previous division process. In the last division process, the second dividing line is flush with the other end of the graphic to be processed in the critical dimension direction.

9. The optical proximity correction method as described in claim 2, characterized in that, In the step of selecting a first graphic whose first size is larger than a preset size as the graphic to be processed, the preset size is 55nm to 65nm.

10. The optical proximity correction method as described in claim 1, characterized in that, In the step of providing the initial layout layer, the initial layout layer is a layout layer for forming an SRAM device, the first pattern is a metal line cut pattern, and the critical dimension direction is the extension direction of the metal line.

11. An optical proximity correction system, characterized in that, include: A plate layer providing module is used to provide an initial plate layer, the initial plate layer including a first graphic having a first dimension along a critical dimension direction; The graphic splitting module is used to split the first graphic into second graphics along the key dimension direction. The combined graphic formed by the second graphics is the same as the corresponding first graphic. The second graphic has a second dimension along the key dimension direction, and the second dimension is less than or equal to a preset dimension. The plate layer splitting module is used to split the initial plate layer into multiple plate layers, and place the second graphic corresponding to each first graphic in different plate layers.

12. A photomask, characterized in that, include: The image obtained using the optical proximity correction method as described in any one of claims 1-10.

13. A semiconductor device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the optical proximity correction method as described in any one of claims 1-10.

14. A storage medium, characterized in that, The storage medium stores one or more computer instructions for implementing the optical proximity correction method as described in any one of claims 1-10.

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