Bus system

Abstract

The present invention provides a bus system. The bus system includes a master control element and a plurality of slave elements. Each of the slave elements has a pin. The plurality of pins of the plurality of slave elements are electrically connected together via a control line. A first slave element provides a first clock signal to each second slave element via the control line, so that a second clock signal of each second slave element is synchronized with the first clock signal. After the plurality of second clock signals are synchronized with the first clock signal, each second slave element adjusts the phase of the second clock signal in a clock phase shift phase, so that the second clock signal has a phase difference with the first clock signal. The phase difference between the second clock signal of each second slave element and the first clock signal is different.

Description

Technical Field

[0001] The present invention relates to a bus system, and more particularly to a bus system having a plurality of slave components. Background Art

[0002] In the past, in computer systems, chipsets such as south bridge chips were electrically connected to other circuit modules, such as system-on-a-chip (SoC) with different functions, through low pin count (LPC) interfaces. These external circuit modules connected through the low pin count interface can be assigned different independent addresses, so the south bridge chip can communicate with the external circuit modules in a one-to-many manner. However, in recent years, some newly proposed bus architectures, such as the Enhanced Serial Peripheral Interface (eSPI) bus, only allow the chipset and external circuit modules to communicate in a one-to-one mechanism.

[0003] Therefore, a mechanism is needed to schedule buses of multiple circuit modules. Summary of the invention

[0004] The present invention provides a bus system. The bus system includes a master control element, an enhanced sequence peripheral device interface bus, and a plurality of slave elements electrically connected to the master control element via the enhanced sequence peripheral device interface bus. Each of the slave elements has a pin, and the plurality of pins of the plurality of slave elements are electrically connected together via a control line. A first slave element of the plurality of slave elements provides a first clock signal to each second slave element of the plurality of slave elements via the control line, so that a second clock signal of each second slave element is synchronized with the first clock signal. After the plurality of second clock signals are synchronized with the first clock signal, each second slave element adjusts the phase of the second clock signal in a clock phase shift stage so that the second clock signal has a phase difference with the first clock signal. The phase difference between the second clock signal of each second slave element and the first clock signal is different.

[0005] Furthermore, the present invention provides a bus system. The bus system includes a master control element, an enhanced sequence peripheral device interface bus and a plurality of slave elements. The plurality of slave elements are electrically connected to the master control element via the enhanced sequence peripheral device interface bus. Each of the slave elements has a pin, and the plurality of pins of the plurality of slave elements are electrically connected together via a control line. The plurality of slave elements determine whether to communicate with the master control element via the enhanced sequence peripheral device interface bus by driving the control line. After a first slave element of the plurality of slave elements provides a first clock signal to each second slave element of the plurality of slave elements via the control line, each second slave element controls a second clock signal to have a phase difference with the first clock signal. The phase difference between the second clock signal of each second slave element and the first clock signal is different.

[0006] In an embodiment of the present invention, without adding additional pins, the warning handshake control line can be used to perform clock phase synchronization and clock phase shift operations to schedule the priority of each slave component to use the bus to communicate with the master component. In addition, by adjusting the phase difference of the clock signal of each slave component, the power to drive the warning handshake control line can be given to the slave component with lower priority first. Thus, it can be avoided that the slave component with higher priority always occupies the bus to communicate with the master component. In addition, compared with the traditional bus system that needs to drive the warning handshake control line according to the priority order, in an embodiment of the present invention, the slave component with interruption demand can drive the warning handshake control line in the same cycle of the clock signal after detecting that the warning handshake control line is not driven, thereby improving the efficiency of communicating with the master component. This allows the bus system to have a faster response speed and more flexible response policy for emergencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A bus system according to some embodiments of the present invention is shown.

[0008] Figure 2 Display according to some embodiments of the present invention Figure 1 Connection configuration diagram of the bus system in .

[0009] Figure 3 A flowchart of a clock phase shift scheduling control method of a bus system according to some embodiments of the present invention is shown.

[0010] Figure 4 A sample signal waveform showing the slave device's clock signal and the warning handshake control line is used to illustrate Figure 3 The state in which the clock phase shift operation in the clock phase shift scheduling control method is unsuccessful.

[0011] Figure 5 A sample signal waveform showing the slave device's clock signal and the warning handshake control line is used to illustrate Figure 3 The state of a successful clock phase shift operation in the clock phase shift scheduling control method.

[0012] Figure 6 A sample signal waveform showing the slave device's clock signal and the warning handshake control line is used to illustrate Figure 3 The sequencing operation in the clock phase shift scheduling control method.

[0013] Reference Numbers

[0014] 1: Bus system

[0015] 10: Main control components

[0016] 12: Bus

[0017] 14A-14D: Slave components

[0018] 142A-142D: Clock Phase Adjustment Module

[0019] 145A-145D: Scheduler Controller

[0020] 16A-16D: Address entry selection pin

[0021] 18A-18D: Address segment selection pins

[0022] 20: Processing module

[0023] 22: Memory

[0024] Alert_1-Alert_4: Alert handshake pins

[0025] ALERT_HAND~Alert handshake control line;

[0026] clk1-clk4: clock signal

[0027] eSPI_CS: chip select signal line

[0028] eSPI_CLK: clock signal

[0029] eSPI_IO: input and output signal lines

[0030] eSPI_RST: reset signal line

[0031] GND: Ground terminal

[0032] R: Pull-up resistor

[0033] S302-S338~Steps

[0034] VDD: Power supply DETAILED DESCRIPTION

[0035] In order to make the above and other purposes, features, and advantages of the present invention more clearly understood, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings as follows:

[0036] Figure 1 The bus system 1 according to some embodiments of the present invention is shown. The bus system 1 includes a master component 10, a bus 12, and a plurality of slave components 14A-14D. In some embodiments, the master component 10 is a south bridge chip. In some embodiments, the master component 10 can be electrically connected to a processing module 20 of a computer system (not shown) so as to access data with the slave components 14A-14D via the bus 12 in response to instructions from the processing module 20. In some embodiments, the processing module 20 can be electrically connected to a memory 22 of the computer system so as to access the memory 22 according to the requirements of different application programs. In some embodiments, the bus 12 is an Enhanced Serial Peripheral Interface (eSPI) bus. The master component 10 is electrically connected to the slave components 14A-14D via the bus 12. In addition, the master component 10 communicates with the slave components 14A-14D in a one-to-one mechanism, and the slave components 14A-14D communicate with the master component 10 according to an arbitration mechanism. It should be noted that the number of slave components 14A-14D is only an example and is not intended to limit the present invention.

[0037] Figure 2 Display according to some embodiments of the present invention Figure 1 1 is a connection configuration diagram of the bus system 1. In this embodiment, the bus 12 includes a reset signal line eSPI_RST, a chip select signal line eSPI_CS, a clock signal eSPI_CLK, and an input / output signal line eSPI_IO. The master control element 10 communicates with the slave elements 14A-14D in a one-to-one mechanism via the chip select signal line eSPI_CS. In addition, through the arbitration mechanism, the slave elements 14A-14D can communicate with the master control element 10 (for example, transmit data and instructions) via the input / output signal line eSPI_IO. When the master control element 10 communicates with the slave elements 14A-14D via the bus 12, the clock signal eSPI_CLK can be used as a reference clock.

[0038] Generally speaking, according to the operation mechanism of the chip selection signal line eSPI_CS, the master control component 10 can only select a single component for communication. However, by using the arbitration mechanism, only one of the slave components 14A-14D responds to the master control component 10 at a time in the bus system 1. Therefore, when the master control component 10 still operates in a one-to-one communication mechanism, the bus 12 can correspond to one chip selection signal line eSPI_CS and connect the slave components 14A-14D for communication, thereby improving the expandability of the bus system 1.

[0039] exist Figure 2 , the slave components 14A-14D include address segment selection pins 18A-18D, address entry selection pins 16A-16D, and alert handshake pins Alert_1-Alert_4. The addresses corresponding to the slave components 14A-14D can be configured by a combination of voltage levels received by the address segment selection pins 18A-18D and the address entry selection pins 16A-16D, so that the slave components 14A-14D have different address segments. For example, the address segment selection pins 18A and 18C of the slave components 14A and 14C are coupled to the ground terminal GND to correspond to the first address segment. The address entry selection pins 16A and 16C of the slave components 14A and 14C are respectively coupled to the ground terminal GND and the power supply VDD to respectively correspond to different address entry codes, for example, respectively corresponding to the first address and the second address of the first address segment. In addition, the address segment selection pins 18B and 18D of the slave components 14B and 14D are coupled to the power supply VDD to correspond to the second address segment. The address entry selection pins 16B and 16D of the slave components 14B and 14D are respectively coupled to the ground terminal GND and the power supply VDD to correspond to different address entry codes, such as the first address and the second address of the second address segment.

[0040] The alert handshake pins Alert_1-Alert_4 of the slave components 14A-14D are electrically connected to the alert handshake control line ALERT_HAND. In this embodiment, the alert handshake control line ALERT_HAND is electrically connected to the power supply VDD via a pull-up resistor R, so that the alert handshake control line ALERT_HAND is at a high voltage level (e.g., a high logic signal "H"). In addition, according to the respective clock signals of the slave components 14A-14D, the schedule controllers 145A-145D in the slave components 14A-14D can drive the alert handshake control line ALERT_HAND by controlling the corresponding alert handshake pins Alert_1-Alert_4 to be at a low voltage level (e.g., a low logic signal "L"), so that the alert handshake control line ALERT_HAND is at a low voltage level. Thus, each slave device 14A-14D can obtain the right to actively communicate with the master device 10 by controlling the voltage level of the alert handshake control line ALERT_HAND. The alert handshake pins Alert_1-Alert_4 are bidirectional input / output pins and are open drain in output mode.

[0041] In some embodiments, the alert handshake control line ALERT_HAND is electrically connected to the ground terminal GND via a pull-down resistor (not shown) so that the alert handshake control line ALERT_HAND is at a low voltage level (e.g., a low logic signal "L"). Therefore, according to the respective clock signals of the slave components 14A-14D, the schedule controllers 145A-145D in the slave components 14A-14D can drive the alert handshake control line ALERT_HAND by controlling the corresponding alert handshake pins Alert_1-Alert_4 to be at a high voltage level (e.g., a high logic signal "H"), so that the alert handshake control line ALERT_HAND is at a high voltage level. Therefore, each slave component 14A-14D can obtain the right to actively communicate with the master component 10 by controlling the voltage level of the alert handshake control line ALERT_HAND.

[0042] In the bus system 1, the slave components 14A-14D can respectively have clock signals with the same period (same frequency) and different phases through the clock phase adjustment modules 142A-142D. Therefore, the slave components 14A-14D drive the alert handshake control line ALERT_HAND according to their respective clock signals so as to communicate with the master component 10 via the bus 12. In order to simplify the description, the clock generators in the slave components 14A-14D will be omitted.

[0043] Figure 3A flowchart of a clock phase shift scheduling control method 300 of a bus system 1 according to some embodiments of the present invention is shown. Figure 3 The clock phase shift scheduling control method can be executed by the scheduling controllers 145A-145D and the clock phase adjustment modules 142B-142D of the slave components 14A-14D in the bus system 1.

[0044] First, when the slave component 14A-14D is powered on or reset (step S302), the scheduling controller 145A-145D determines whether the slave component has the highest priority to communicate with the master component 10 (step S304). If the slave component has the highest priority, the slave component will drive the alert handshake control line ALERT_HAND to notify other slave components to enter the phase synchronization requirement phase Phase_Sync (step S306). Then, in the synchronization code phase Sync_Code, the slave component with the highest priority will transmit the phase synchronization code to other slave components through the alert handshake control line ALERT_HAND (step S308). On the contrary, if the slave component does not have the highest priority, the slave component will receive the phase synchronization code from the alert handshake control line ALERT_HAND in the synchronization code phase Sync_Code (step S310). Next, in the clock phase synchronization phase ClockPhase_Sync, the slave component with the highest priority transmits its own clock signal to other slave components through the alert handshake control line ALERT_HAND (step S312). At the same time, according to the clock signal from the alert handshake control line ALERT_HAND, other slave components synchronize their own clock signals with the received clock signal. Next, the slave components 14A-14D enter the clock phase synchronization end phase ClockPhase_SyncEnd (step S314).

[0045] Next, it is determined whether all slave components 14A-14D have completed the operation of clock phase synchronization (step S316). If a slave component has not completed the operation of phase synchronization, the slave component will drive the alert handshake control line ALERT_HAND (step S318) to notify other slave components. Then, the process of the clock phase shift scheduling control method 300 will return to step S304 until all slave components have completed the operation of clock phase synchronization. In some embodiments, if a slave component has not completed the operation of phase synchronization, the process of the clock phase shift scheduling control method 300 will return to step S306, S308 or S312.

[0046] Figure 4The exemplary signal waveform diagrams showing the clock signals clk1 - clk4 of the slave components 14A - 14D and the alert handshake control line ALERT_HAND are used to illustrate Figure 3 In the clock phase shift scheduling control method, the clock phase shift operation is not successful. In addition, Figure 4 The waveforms of the clock signals clk1 - clk4 and the alert handshake control line ALERT_HAND shown are merely examples and are not intended to limit the present invention.

[0047] exist Figure 4 In the example, it is assumed that the slave device 14A has the highest priority to communicate with the master device 10. In some embodiments, for the slave device, the priority of communicating with the master device 10 is set by the address segment selection pins 18A-18D, the address entry selection pins 16A-16D or the register.

[0048] At time point t1, in response to the interrupt request P_REQ, the schedule controller 145A of the slave component 14A drives the alert handshake control line ALERT_HAND (e.g., controls the alert handshake control line ALERT_HAND to change from a high voltage level to a low voltage level) to notify the slave components 14B-14D to enter the phase synchronization requirement phase Phase_Sync (step S306). It should be noted that the number of clock cycles during which the alert handshake control line ALERT_HAND is driven in the phase synchronization requirement phase Phase_Sync is only an example and is not intended to limit the present invention.

[0049] At time point t2, the scheduling controller 145A controls the alert handshake control line ALERT_HAND to transmit the phase synchronization code "01010" to the slave components 14B-14D in the synchronization code stage Sync_Code (step S308). It is worth noting that since the clock signals of the slave components 14A-14D are not synchronized at this time (for example, the phase of the clock signal clk4 of the slave component 14D is the same as the clock signal clk1 of the slave component 14A, and the phases of the clock signals clk2 and clk3 of the slave components 14B and 14C are different from the clock signal clk1 of the slave component 14A), each bit of the phase synchronization code needs to be transmitted and maintained for two clock cycles of the clock signal clk1 to ensure that each slave component can receive the phase synchronization code "01010". It is worth noting that the number of bits and data values ​​of the phase synchronization code "01010" are only examples and are not used to limit the present invention. In some embodiments, the number of bits of the phase synchronization code can be determined by the number of slave components. For example, when the number of slave elements increases, the number of bits of the phase synchronization code also increases.

[0050] At time point t3, the schedule controller 145A transmits the clock signal clk1 to the slave components 14B-14D via the alert handshake control line ALERT_HAND in the clock phase synchronization stage ClockPhase_Sync. Then, the clock phase adjustment modules 142B-142D of the slave components 14B-14D adjust their own clock signals based on the clock signal clk1 so that their own clock signals can be synchronized with the clock signal clk1 on the alert handshake control line ALERT_HAND.

[0051] In some embodiments, the slave components 14A-14D may re-execute synchronization operations according to specific conditions to re-synchronize and phase-shift the clock signals clk1-clk4 to prevent factors such as voltage and temperature from causing clock signal deviations that affect the operation of the bus system 1.

[0052] In some embodiments, the slave components 14A-14D adjust the clock signals clk1-clk4 based on the clock signal eSPI_CLK of the bus 12. For example, after the bus system 1 is powered on, only the slave component 14A with the highest priority can communicate with the master component 10 through the bus 12. At this time, each slave component can use the clock signal eSPI_CLK for synchronization to achieve a continuous synchronization effect, thereby avoiding the clock signal offset caused by factors such as voltage and temperature fluctuations. In this embodiment, the frequency of the clock signal of each slave component is the same as the clock signal eSPI_CLK.

[0053] At time point t4, the slave components 14A-14D enter the clock phase synchronization end stage ClockPhase_SyncEnd. Since the slave component 14B has not yet completed the clock phase synchronization operation, the schedule controller 145B of the slave component 14B drives the alert handshake control line ALERT_HAND (for example, controls the alert handshake control line ALERT_HAND to change from a high voltage level to a low voltage level) to notify the slave components 14A, 14C and 14D that the synchronization operation has not yet been completed. As described previously, since the clock signals of the slave components 14A-14D are still not synchronized at this time, the schedule controller 145B needs to drive the alert handshake control line ALERT_HAND for two clock cycles of the clock signal clk2 to ensure that the slave components 14A, 14C and 14D can know that other slave components have not completed phase synchronization. Then, at time point t5, the clock phase synchronization end phase ClockPhase_SyncEnd will end, and the slave components 14A-14D will re-execute the phase synchronization operation until the clock phase synchronization operation is completed.

[0054] Reference Figure 3In step S316, if the slave components 14A-14D complete the clock phase synchronization operation, then except for the slave component with the highest priority, each slave component will adjust its own clock signal to the corresponding phase according to the preset phase value in the clock phase shift stage ClockPhase_Shift (step S320).

[0055] After the clock phase shift phase ClockPhase_Shift (step S320), all slave components complete the phase synchronization operation and phase shift operation of the clock signal. Therefore, all slave components have clock signals of the same frequency and different phases. Then, these slave components perform a sorting operation S330 according to their respective clock signals to communicate with the master component 10.

[0056] In the standby waiting stage IdleWait (step S332) of the sorting operation S330, the scheduling controller 145A-145D of each slave component 14A-14D controls the corresponding alert handshake pin Alert_1-Alert_4 to the input mode to monitor whether the alert handshake control line ALERT_HAND is driven by any slave component 14A-14D, for example, the alert handshake control line ALERT_HAND changes from a high voltage level to a low voltage level.

[0057] Figure 5 The exemplary signal waveform diagrams showing the clock signals clk1 - clk4 of the slave components 14A - 14D and the alert handshake control line ALERT_HAND are used to illustrate Figure 3 The state of a successful clock phase shift operation in the clock phase shift scheduling control method. Figure 5 The phase synchronization requirement phase Phase_Sync, the synchronization code phase Sync_Code and the clock phase synchronization phase ClockPhase_Sync are the same as Figure 4 .also, Figure 5 The waveforms of the clock signals clk1 - clk4 and the alert handshake control line ALERT_HAND shown are merely examples and are not intended to limit the present invention.

[0058] At time point t6, slave components 14A-14D enter the clock phase synchronization end stage ClockPhase_SyncEnd. Since slave components 14B-14D have completed the clock phase synchronization operation, slave components 14B-14D will not drive the alert handshake control line ALERT_HAND. In addition, in the clock phase synchronization end stage ClockPhase_SyncEnd, the clock signals clk2-clk4 of slave components 14B-14D are synchronized with the clock signal clk1 of slave component 14A. Then, at time point t7, slave components 14A-14D enter the clock phase shift stage ClockPhase_Shift. In the clock phase shift stage ClockPhase_Shift, slave components 14A-14D phase shift the clock signals according to their respective priority orders. In this embodiment, when communicating with the master component 10 (e.g., in the standby waiting stage IdleWait), the slave component 14A has the first priority (i.e., the highest priority), the slave component 14B has the second priority, the slave component 14C has the third priority, and the slave component 14D has the fourth priority (i.e., the lowest priority). In addition, in this embodiment, the slave components from the first priority to the fourth priority are phase-shifted by 0°, 90°, 180°, and 270°, respectively, as shown at time points t7, t8, t9, and t10. Specifically, the phase difference between the clock signal clk1 of the slave component 14A and the clock signal clk2 of the slave component 14B is 90° (i.e., a specific phase difference), the phase difference between the clock signal clk1 of the slave component 14A and the clock signal clk3 of the slave component 14C is 180° (i.e., twice the specific phase difference), and the phase difference between the clock signal clk1 of the slave component 14A and the clock signal clk4 of the slave component 14D is 270° (i.e., three times the specific phase difference). In this embodiment, the specific phase difference is determined by the number of slave components 14A-14D, for example, 360° / 4=90°. In other words, the clock phase adjustment modules 142B-142D of the slave components 14B-14D adjust the phases of their respective clock signals according to the clock signal clk1. In addition, the phase difference between the clock signals clk2-clk4 and the clock signal clk1 is an integer multiple of the specific phase difference. In the slave components 14B-14D, the clock signal clk2 has the smallest phase difference with the clock signal clk1, and the clock signal clk4 has the largest phase difference with the clock signal clk1. In other words, in the slave components 14B-14D, the slave component 14B has the highest priority, and the slave component 14D has the lowest priority. Then, at time point t11, the clock phase shift phase ClockPhase_Shift enters the standby waiting phase IdleWait of the sorting operation S330.

[0059] Reference Figure 3 In the sorting operation S330, after the standby waiting stage IdleWait (step S332), each slave component can decide whether it is necessary to issue an interrupt request REQ to request communication with the master control component 10 through the bus 12 (step S334). If it is not necessary to communicate with the master control component 10, the slave component will return to the standby waiting stage IdleWait. If it is necessary to communicate with the master control component 10 (for example, eSPI communication), the slave component will drive the alert handshake control line ALERT_HAND according to its clock signal to notify other slave components (step S336) until the communication is completed (step S338). In the standby waiting stage IdleWait, the slave component with a higher priority can drive the alert handshake control line ALERT_HAND earlier. Therefore, after the slave component with a lower priority detects that the alert handshake control line ALERT_HAND is driven, it will not control the corresponding alert handshake pin to drive the alert handshake control line ALERT_HAND. Once the communication with the master control element 10 is completed, the slave element with a higher priority will stop driving the alert handshake control line ALERT_HAND. At the same time, if there is an interrupt request REQ from another slave element, the slave element can drive the alert handshake control line ALERT_HAND according to its own clock signal. Then, when it is detected that the alert handshake control line ALERT_HAND is not driven, all slave elements will return to the standby waiting stage IdleWait (step S332).

[0060] Figure 6 The exemplary signal waveform diagrams showing the clock signals clk1 - clk4 of the slave components 14A - 14D and the alert handshake control line ALERT_HAND are used to illustrate Figure 3 In the clock phase shift scheduling control method, the sequencing operation S330 is performed. In addition, Figure 6 The waveforms of the clock signals clk1 - clk4 and the alert handshake control line ALERT_HAND shown are merely examples and are not intended to limit the present invention.

[0061] As described above, at time point t11 ​​, the slave components 14A- 14D enter the idle waiting phase IdleWait.

[0062] In this embodiment, the slave devices 14A-14C need to communicate with the master device 10. Therefore, in response to the interrupt request REQ, the slave devices 14A-14C request to communicate with the master device 10 via the bus 12 according to their respective clock signals clk1-clk3.

[0063] At time point t12, since slave component 14A has the highest priority, slave component 14A drives the alert handshake control line ALERT_HAND in response to interruption request REQ1 so as to communicate with master component 10 through bus 12. Then, slave components 14B and 14C detect that the alert handshake control line ALERT_HAND is driven. Therefore, slave components 14B and 14C do not drive the alert handshake control line ALERT_HAND at time points t13 and t14. After completing the communication with the master component, slave component 14A stops driving the alert handshake control line ALERT_HAND at time point t15.

[0064] After the slave component 14A stops driving the alert handshake control line ALERT_HAND, the slave components 14B-14D detect that the alert handshake control line ALERT_HAND is not driven. Then, at time point t16, the slave component 14B drives the alert handshake control line ALERT_HAND in response to the interruption request REQ2 so as to communicate with the master control component 10 through the bus 12. Since the alert handshake control line ALERT_HAND is driven, the slave component 14C will not drive the alert handshake control line ALERT_HAND at time point t17. In addition, it is worth noting that because the slave component 14A with the highest priority has passed the phase in which the alert handshake control line ALERT_HAND can be driven in the cycle CY1 of the clock signal clk1, only the other slave components 14B-14D with lower priorities can detect that the alert handshake control line ALERT_HAND is not driven. Therefore, the slave components 14B-14D with lower priority can raise the interrupt request REQ. Specifically, when multiple slave components need to communicate with the master component 10 through the bus 12 at the same time, by using clock signals with different phases, it can be avoided that the bus 12 is always used by the slave components with higher priority, thereby affecting the use rights of other slave components with lower priority to communicate with the master component 10. In other words, the slave component 14A will detect that the alert handshake control line ALERT_HAND is driven, so it will not drive the alert handshake control line ALERT_HAND at the time point t18.

[0065] After completing the communication with the master control element 10, the slave element 14B stops driving the alert handshake control line ALERT_HAND at time point t19. After the slave element 14B stops driving the alert handshake control line ALERT_HAND, the slave element 14C drives the alert handshake control line ALERT_HAND at time point t20 in response to the interrupt request REQ3, so as to communicate with the master control element 10 through the bus 12. Similarly, because the slave element 14A with the highest priority has passed the phase in which the alert handshake control line ALERT_HAND can be driven in the cycle CY2 of the clock signal clk1, that is, the slave element 14A detects that the alert handshake control line ALERT_HAND is driven, it will not drive the alert handshake control line ALERT_HAND at time point t21.

[0066] After completing the communication with the master component 10, the slave component 14C stops driving the alert handshake control line ALERT_HAND at time point t22. Since the slave component 14D does not drive the alert handshake control line ALERT_HAND in the cycle CY3 of the clock signal clk1, the slave component 14A can drive the alert handshake control line ALERT_HAND at time point t23 to communicate with the master component 10. Then, after completing the communication with the master component 10, the slave component 14A stops driving the alert handshake control line ALERT_HAND. If no other slave components continue to drive the alert handshake control line ALERT_HAND, the slave components 14A-14D enter the standby waiting stage IdleWait.

[0067] In the embodiment of the present invention, without adding additional pins, the alarm handshake control line ALERT_HAND can be used to perform clock phase synchronization and clock phase shift operations to schedule the priority of each slave component to use the bus 12 to communicate with the master component 10. In addition, by adjusting the phase difference of the clock signal of each slave component, the power to drive the alarm handshake control line ALERT_HAND can be given to the slave component with lower priority first. Therefore, it can be avoided that the slave component with higher priority always occupies the bus 12 to communicate with the master component 10. In addition, compared with the traditional bus system that needs to drive the alarm handshake control line ALERT_HAND according to the priority order, in the embodiment of the present invention, the slave component with interruption demand can drive the alarm handshake control line ALERT_HAND in the same cycle of the clock signal (for example, cycle CY1, CY2 and CY3) after detecting that the alarm handshake control line ALERT_HAND is not driven, so the efficiency of communicating with the master component can be improved. The bus system 1 can have a faster response speed and a more flexible response policy for emergency events.

[0068] Although the present invention has been described above with reference to the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended claims.

Claims

1. A bus system, characterized in that: include: A main control element; - an enhanced serial peripheral interface bus; as well as A plurality of slave components are electrically connected to the master component via the ESPI bus; Each of the slave components has a pin, and the pins of the slave components are electrically connected together via a control line; wherein a first slave element of the plurality of slave elements provides a first clock signal to each second slave element of the plurality of slave elements via the control line, so that a second clock signal of each second slave element is synchronized with the first clock signal; wherein after a plurality of second clock signals are synchronized with the first clock signal, each of the second slave components adjusts the phase of the second clock signal in a clock phase shift phase so that the second clock signal has a phase difference with the first clock signal; The phase difference between the second clock signal and the first clock signal of each of the second slave components is different.

2. The bus system according to claim 1, characterized in that The phase difference between the second clock signal of each of the second slave elements and the first clock signal is an integer multiple of a specific phase difference.

3. The bus system according to claim 2, characterized in that The specific phase difference is determined by the number of the plurality of slave elements.

4. The bus system according to claim 1, characterized in that The plurality of slave components determine whether to communicate with the master component via the ESPI bus by driving the control line.

5. The bus system according to claim 4, characterized in that In a standby waiting stage, the first slave component has the highest priority in communicating with the master component among the plurality of slave components.

6. The bus system according to claim 5, characterized in that In the standby waiting stage, the priority of the second slave components to communicate with the master component is determined by the phase differences between the second clock signals and the first clock signal.

7. The bus system according to claim 6, characterized in that In the standby waiting stage, among the plurality of second slave elements, the phase difference between the second clock signal of the second slave element having the highest priority for communicating with the master element and the first clock signal is the smallest.

8. The bus system according to claim 6, characterized in that The phase difference between the second clock signal of the second slave element having the lowest priority for communicating with the master element and the first clock signal among the plurality of second slave elements is the largest.

9. The bus system according to claim 1, characterized in that: Before the first slave component provides the first clock signal to the second slave components via the control line, the first slave component further provides a phase synchronization code to the second slave components via the control line, wherein the phase synchronization code has a plurality of bits.

10. A bus system, characterized in that: include: A main control element; - an enhanced serial peripheral interface bus; as well as A plurality of slave components are electrically connected to the master component via the ESPI bus; Each of the slave components has a pin, and the pins of the slave components are electrically connected together via a control line; wherein the plurality of slave components determine whether to communicate with the master component via the enhanced serial peripheral device interface bus by driving the control line; wherein after a first slave element of the plurality of slave elements provides a first clock signal to each second slave element of the plurality of slave elements via the control line, each second slave element controls a second clock signal to have a phase difference with the first clock signal; The phase difference between the second clock signal and the first clock signal of each of the second slave components is different.

11. The bus system according to claim 10, characterized in that The first slave component drives the control line according to the first clock signal so as to communicate with the master component through the enhanced serial peripheral device interface bus.

12. The bus system according to claim 10, characterized in that A plurality of second slave components drive the control line respectively according to a plurality of second clock signals with different phase differences, so as to communicate with the master component through the enhanced serial peripheral device interface bus.

13. The bus system according to claim 10, characterized in that: The first slave component provides the first clock signal to each of the second slave components via the control line, so that the second clock signal of each of the second slave components is synchronized with the first clock signal.

14. The bus system according to claim 13, characterized in that After each of the second clock signals is synchronized with the first clock signal, each of the second slave components adjusts the phase of the second clock signal in a clock phase shifting stage so that the second clock signal has the phase difference with the first clock signal.

15. The bus system according to claim 10, characterized in that: The phase difference between the second clock signal of each of the second slave elements and the first clock signal is an integer multiple of a specific phase difference.

16. The bus system according to claim 15, characterized in that The specific phase difference is determined by the number of the plurality of slave elements.

17. The bus system according to claim 10, characterized in that: In a standby waiting stage, the first slave component has the highest priority among the plurality of slave components to communicate with the master component.

18. The bus system according to claim 17, characterized in that In the standby waiting stage, the priority of the second slave components to communicate with the master component is determined by the phase differences between the second clock signals and the first clock signal.

19. The bus system according to claim 18, characterized in that In the standby waiting stage, the phase difference between the second clock signal of the second slave element having the highest priority for communicating with the master element among the plurality of second slave elements and the first clock signal is the smallest.

20. The bus system according to claim 18, characterized in that The phase difference between the second clock signal of the second slave element having the lowest priority for communicating with the master element and the first clock signal among the plurality of second slave elements is the largest.

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