Equivalent traversal fault injection method for register error injection single event effect simulation

Abstract

The application provides an equivalent traversal fault injection method for register error injection single event effect simulation, and is used for solving the technical problem that simulation time consumption and simulation fault coverage exist in contradiction in single event effect simulation of a large-scale integrated circuit register unit. The method is based on a multi-register unit fault injection model, adopts a traversal fault injection file set simulation mode of all register units, maximally discovers a fault condition caused by a single event effect in a to-be-tested circuit, and deletes invalid fault injection files in a fault injection file set corresponding to a register associated group of a non-enabled register unit and an enabled register unit. Space dimension screening is performed on non-working register units in the entire simulation period, and time dimension screening is performed on non-working time of a specified register, so that the time and space costs of simulation are greatly reduced, and the single event fault simulation and evaluation requirements in the design stage of a large-scale space integrated circuit are met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of registers, and in particular to an equivalent traversal fault injection method for register single event effect simulation. BACKGROUND

[0002] The aerospace digital integrated circuit is an important component of the space electronic system, and its anti-radiation performance directly affects the stability of the space electronic system. In order to protect the anti-radiation ability of the aerospace digital integrated circuit, the widely used reinforcement method in engineering is to use the anti-radiation reinforced components and system reinforcement to protect the anti-radiation ability of the system, and the reinforcement effect can only be verified by test, and cannot be simulated and evaluated in the design process. At the same time, due to the limitation of the test system capacity, such as: the single particle energy is limited, which cannot penetrate the stacked structure chip, the number of particles (1e7) used in the single particle test cannot ensure that all units are hit by single particles, and the data obtained by the single particle test is difficult to be used for fault analysis and positioning, etc. The current test means is difficult to comprehensively evaluate the single particle effect reinforcement ability of the space system. There is an urgent need for an anti-radiation reinforcement performance evaluation method for aerospace digital microsystems at home and abroad.

[0003] Simulation technology has been widely used in the field of integrated circuit design for a long time. Many scholars at home and abroad have tried to develop integrated circuit single event effect simulation technology from different abstraction levels. However, current dynamic simulation or static simulation faces the dilemma of large-scale circuit single event effect analysis. First, the speed and scale of single event effect dynamic simulation scheme are not ideal: dynamic simulation can simulate the results caused by exact fault injection, which is convenient for fault positioning and fault reproduction. However, due to the high precision of device-level and tube-level single event effect dynamic simulation, the time consumption cost and storage space occupation cost are high, which makes it difficult to generate sufficient data for analyzing the overall single event sensitivity of the circuit. Even for digital circuit dynamic simulation, when dealing with large-scale circuits, the scale of fault injection points is too large, and the limited scale of random fault injection method also makes it difficult to achieve full coverage of circuit faults. Second, static simulation fault positioning and fault reproduction are difficult: static simulation can analyze the overall single event sensitivity of the circuit under the tolerable simulation time cost and storage space cost. However, static analysis is based on the structure of the circuit to calculate the probability, which makes it difficult to accurately locate the fault analysis and reproduce the fault, thus bringing challenges to the investigation of the cause of the circuit single event sensitivity.

[0004] In summary, on the basis of retaining the advantages of dynamic simulation fault location and fault reproduction, reducing the cost of fault injection simulation time consumption and storage space occupation cost has become a focus of the industry. This study needs to focus on a suitable research object that can represent the overall single event sensitivity of the circuit and reduce the size of dynamic simulation fault injection. Many institutions and universities at home and abroad believe that circuit registers are a suitable choice for three reasons: first, the lower register in the circuit pipeline latches the single event transient fault, which in turn causes a single event upset, which can reflect the severity of single event transient fault in the upper level combinatorial logic circuit, so the single event upset of the full chip register can effectively reflect the severity of the single event effect caused by the single event, which has important guiding significance for the simulation and evaluation of single event effects of the entire chip; second, the number of registers is less than the number of fault injection nodes in the entire circuit, which can reduce the size of the fault injection set and achieve simulation time acceleration; third, the register is composed of flip-flop units, has similar timing characteristics, and is easy to analyze and obtain, facilitating fault location and fault reproduction.

[0005] Based on the register injection error dynamic simulation scheme has become an important research direction of large-scale system circuit simulation, and has produced a large number of practical case analysis for aerospace integrated circuit applications.

[0006] In 2007, E. Touloupis et al. analyzed the single fault injection and double fault injection of LEON2 processor. This project chose a simulation-based method, and the fault injection was always synchronized with the clock period, and the occurrence time was expressed in clock cycles. When the period to be injected fault was reached, the selection signal of the multiplexer was changed, so that the wrong fault input was latched into the register. The fault injector read the characteristics (occurrence time and location) of each fault from the local file created before simulation started. When injecting one or more fault inputs, the fault injector reads the fault file again to select the next set of faults. Since the entire injection process is performed in one clock cycle, the fault injector can inject faults that occur in consecutive clock cycles. However, all fault injection experiments in this project are only for the pipeline execution unit of the microprocessor, and do not have fault accessibility for the registers present in other processors, and the fault injection method of this project needs to insert additional circuits into the original test circuit, using an invasive simulation method, which will inevitably cause differences in simulation results compared to the real environment.

[0007] In 2012, A. Mohammadi et al. ignored the system area and power consumption, embedded LEON2 in FPGA, and performed single event upset (SEU) fault injection tests on the system's latches and memory cells. The design achieves the purpose of reading or modifying memory data and internal node potentials through the memory editor (MCE) and system debug tools (SAP) controlled by the JTAG controller. The study describes in detail the structure of the FPGA internal fault injection board (FIB) and how to use SAP to inject faults and read data. When the scan chain is positioned at the register at the configured time, the value of the target register unit is flipped using the target register unit SAP. Wait for the scan to end, collect the value of the target register at the next trigger edge and compare it. FPGA takes into account both the flexibility of simulation and the high-speed characteristics of physical testing. The simulation method has good simulation observability and reachability, but the cost of hardware simulation components means that the simulation invasive design will change the critical path of the circuit, and using FPGA means that the simulation area and power consumption of ASIC do not have reference value.

[0008] In 2017, Bonnoit et al. analyzed the fault injection activities of the LEON3 processor integer unit, and the results of the exhaustive and random fault injection experiments performed at the register transfer level (RTL) were given, and the control bits of the LEON3 processor were targeted. Fault injection is achieved through an automatic netlist fault injection tool called NETFI-2. The impact of multiple errors caused by a single particle hitting the trigger of the control instruction execution process is studied. In this study, the sensitivity of LEON3 to soft errors is evaluated through two fault injections performed at the RTL level: the first is used to determine which of these registers are sensitive to single fault injection (SBU), and the second only selects registers that are not sensitive to SBU as targets for multiple fault injection (MBU). In both cases, the original version of the LEON3 register transfer level (RTL) code was used for fault injection. On the one hand, the classification of registers according to sensitivity in this study improves the controllability of fault injection, but on the other hand, the fault injection in this study is limited to state and control registers, and the reachability of pipeline registers and other registers is poor.

[0009] In 2018, R. Travessini et al. analyzed fault injection campaigns in the CPU registers of the LEON3 soft-core processor. This work used built-in simulator commands in TCL scripts to force bit flips when running three different workloads. The study set up and enabled simulation engine interactions that allowed manipulating signals (fault injection) and observing fault effects. The HDL simulator used for the experiment was Modelsim. The study focused on the LEON3 processor core (pipeline units and cache controller). The study focused on the effects of fault injection and how they were detected between the processor interface and other modules such as caches, main memory, and register files. Based on information about sensitive registers of LEON3, the study evaluated the fault tolerance and area / performance overhead of partial triple modular redundancy (TMR) techniques. The study implemented fault injection for all registers, with good reachability. Limited to single-bit upset (SBU), no solution was proposed for multiple-bit upsets that can exist in the circuit, and the simulation repeatability was poor through random injection of registers.

[0010] However, the current dynamic simulation scheme based on register fault injection has the following problems:

[0011] (1) The simulation method is generally invasive, and the simulation process has been modified for the circuit under test or the test program: In order to improve the simulation performance, the hardware simulation platform in the FPGA simulation method or the fault flip method using interrupt instructions has been modified without exception. The fault-free simulation result, additional area, power consumption or critical path delay, thus reducing the feasibility of simulation; solving the problem of simulation invasiveness requires eliminating the simulation platform design with the nature of modification to the circuit under test and the test program;

[0012] (2) The simulation method generally has weak fault reachability, and the simulation data cannot achieve perfect single event effect evaluation for the circuit under test: only a part of the target circuit under test is studied, or only single fault is studied, and the commonality between methods is poor;

[0013] (3) The simulation method uses a lot of random fault injection, and the simulation repeatability and controllability are poor: limited by the cost of simulation time consumption and the cost of storage space occupation, the simulation method uses a lot of random fault injection methods for statistical calculation, but in the case of insufficient number of samples, the difference between the two repeated results is large, and it is difficult to control the position and time of injection in the simulation process. SUMMARY

[0014] The application aims to solve the technical problem of contradiction between simulation time consumption and simulation fault coverage in single event effect simulation of large-scale integrated circuit register units, and proposes an equivalent traversal fault injection method for register error injection single event effect simulation.

[0015] In order to achieve the above-mentioned purpose, the technical concept and technical solution of the application are as follows:

[0016] Based on the multi-register unit fault injection model, the traversal fault injection file set simulation mode of all register units is adopted to maximize the discovery of the fault caused by single event effect in the circuit under test; at the same time, considering the huge calculation resource and storage resource problem of the traversal fault injection file set simulation, a set of perfect fault injection set equivalent reduction method is proposed to screen the non-working register units in the entire simulation period from the spatial dimension and to screen the non-working time of the specified register from the time dimension, which greatly reduces the time and space cost of simulation, and meets the single event fault simulation and evaluation requirements of large-scale aerospace integrated circuit design stage.

[0017] An equivalent traversal fault injection method for register error injection single event effect simulation, which is characterized by comprising the following steps:

[0018] 1】Construction of multi-register unit fault injection model

[0019] 1.1】According to the gate level netlist of the circuit under test, all register units of the circuit under test are obtained, and the standard cell structure corresponding to all register units of the circuit under test is obtained according to the logic synthesis library; the previous connection line of all register units of the circuit under test is analyzed according to all register units of the circuit under test and the standard cell structure corresponding to all register units of the circuit under test; all effective edges of the simulation test program are obtained.

[0020] 1.2】For any register unit previous connection line in the gate level netlist of the circuit under test, all register units sharing the previous connection line of the register are defined as a register associated group according to the register unit previous connection line name.

[0021] 1.3】For any register associated group in the gate level netlist of the circuit under test, any simulation period effective edge, the input port of each register unit in the register associated group is regarded as a fault injection position, the simulation period effective edge is regarded as a fault injection time, and a multi-register unit fault injection model is constructed according to the fault injection position and the fault injection time, and a register fault injection file of the fault injection position and the fault injection time is generated.

[0022] 2】Combine all register associated groups and all simulation period effective edges, and generate a traversal fault injection file set of all register units through the multi-register unit fault injection model.

[0023] 3】Pruning invalid fault injection files in the set of traversal fault injection files of all register units

[0024] The all register units of the circuit under test are divided into two categories: non-enabled register units and enabled register units; the corresponding pruning rules are established for the non-enabled register units and the enabled register units, so as to prune the invalid fault injection files in the set of fault injection files corresponding to the register association groups of the non-enabled register units and the enabled register units.

[0025] 4】According to the set of traversal fault injection files of the pruned all register units, the equivalent traversal fault injection of the all register units is completed.

[0026] Further, in step 3], the pruning rule of the non-enabled register units is that: the flip list of the all register units of the circuit under test under the simulation test program is obtained through fault-free injection simulation; if the corresponding register unit in the flip list does not occur flip within the valid simulation period, then the fault injection file corresponding to the register association group in which the register unit is located is an invalid fault injection file; if the corresponding register unit occurs flip once or more than once within the valid simulation period, then from the simulation start to the first flip, the fault injection file corresponding to the register association group in which the register unit is located within the valid simulation period is an invalid fault injection file; the pruning rule of the enabled register units is that: the enabled valid interval list of the all enabled register units of the circuit under test under the simulation test program is obtained through fault-free injection simulation; if the enabled input end of the corresponding enabled register unit in the enabled valid interval list is in the non-valid simulation period, then the fault injection file corresponding to the register association group in which the enabled register unit is located at the fault injection time is an invalid fault injection file.

[0027] Further, in step 3], when establishing the pruning rule of the non-enabled register units, a fault discrimination margin ε is set, and only the fault injection file before the flip time and before the period corresponding to the fault discrimination margin ε is regarded as an invalid fault injection file.

[0028] Further, in step 2], the set of traversal fault injection files of the all register units is obtained by the following formula:

[0029] U all_injection = U all_clk_active_edge × U all_reg_groups

[0030] Wherein, U all_clk_active_edge represents the set of all simulation period valid edges, and U all_reg_groups represents the set of all register association groups.

[0031] The beneficial effects of the present application compared to the prior art are:

[0032] 1. The equivalent traversal fault injection method for register error injection single event effect simulation provided by the present application, in view of the technical problem that the simulation scale of the current common large-scale aerospace integrated circuit single event effect simulation is insufficient and it is difficult to cover all single event effect caused faults, innovatively proposes an equivalent traversal fault injection method for the single event effect of the aerospace digital integrated circuit aiming at the traversal register; through a series of technical innovations such as a multi-register unit fault injection model, a fault injection set equivalent reduction method, and the like, the simulation scale and simulation speed problems faced by the single event effect simulation of the traversal register are solved, the time and space costs of the simulation are greatly reduced, the single event fault simulation and evaluation requirements of the large-scale aerospace integrated circuit design stage are met, and a performance optimization basis is provided for realizing the single event effect simulation and analysis of the digital integrated circuit of the traversal register.

[0033] 2. The equivalent traversal fault injection method for register error injection single event effect simulation provided by the present application, based on the fault injection simulation of the gate level netlist of the circuit under test, can obtain the standard cell structure corresponding to all register units of the circuit under test according to the logic synthesis technology library file, so that a general fault injection model becomes possible.

[0034] 3. The equivalent traversal fault injection method for register error injection single event effect simulation provided by the present application adopts the method of inserting a fault injection file in the simulation test platform, which can preserve the integrity of the original circuit under test and the simulation test program.

[0035] 4. The equivalent traversal fault injection method for register error injection single event effect simulation provided by the present application realizes the equivalent reduction of the fault injection set of the register unit in the circuit under the condition that the fault coverage rate of the register unit in the circuit caused by single event transient is basically consistent with the fault coverage rate of the full-circuit traversal fault injection, compared with the full-traversal fault injection method, the simulation time consumption of the present application is reduced, and compared with the random fault injection method, the coverage of the simulation result is improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 It is a flowchart of the equivalent traversal fault injection method for register error injection single event effect simulation;

[0037] Figure 2 It is a flowchart of the multi-register unit fault injection model in step 1 of the present application;

[0038] Figure 3 It is a schematic diagram of the multi-register unit flip phenomenon in step 1.2 of the present application;

[0039] Figure 4 This is a schematic diagram of the fault injection file content in step 1.3 of the present invention;

[0040] Figure 5 This is a flowchart of the fault injection process for traversing all register units in step 2 of the present invention.

[0041] Figure 6 This is a schematic diagram illustrating the single-event flip propagation blockage caused by the non-use of register units in step 3 of the present invention.

[0042] Figure 7 This is a schematic diagram illustrating the single-particle flip propagation blockage caused by the effective propagation time of the fault in step 3 of the present invention.

[0043] Figure 8 This refers to the method for deleting files containing invalid faults in the non-enable register unit in step 3 of this invention.

[0044] Figure 9 This refers to the method for deleting files due to invalid faults in the enable register unit in step 3 of this invention. Detailed Implementation

[0045] To make the advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] An equivalent ergodic fault injection method for single-event effect simulation of register injection errors, such as Figure 1 As shown, the specific steps include:

[0047] 1. Constructing a multi-register unit fault injection model

[0048] In the gate-level netlist of the circuit under test, the sequential flip-flop structure described using the standard cells corresponding to the logic synthesis technology library is called a register cell. For example... Figure 2 The diagram shows a flowchart for constructing a multi-register unit fault injection model. Register units sharing the same preceding stage connection are called register association groups, and the fault injection model determined by the register association groups is called a multi-register unit fault injection model. The construction steps are as follows:

[0049] 1.1】 Obtaining Relevant Structural Information about Register Units

[0050] Obtain the register cell hierarchy (reg_hierarchy) of the circuit under test (DUT) from the gate-level netlist; obtain the standard cell structure (reg_standcell) corresponding to the register cell from the logic synthesis library; determine the upstream wire of the register cell by looking up the standard cell structure (reg_stand_cell) corresponding to the register cell based on the instantiation name of the register cell contained in the register cell hierarchy; and obtain the active edge (clk_active_edge) of the simulation cycle from the simulation test case.

[0051] 1.2 Constructing Register Association Groups

[0052] Register cell toggling is caused by a single-event transient pulse transmitted through the preceding stage connection of the register cell. For example... Figure 3 As shown, multiple register units may flip simultaneously in the register unit of the circuit under test. When a single-event transient pulse propagates downstream along the pre-stage connection wire_1 of the register unit, register units DFF2-1 and DFF2-3 may flip simultaneously due to capturing the single-event transient pulse. However, when a single-event transient pulse propagates downstream along the pre-stage connection wire_2 of the register unit, only register unit DFF2-2 may flip.

[0053] For a group of register units that share the same pre-connection of a register unit, this group of register units is defined as a register association group. All register units and all pre-connections of register units will determine all register association groups (reg_groups). The specific method for obtaining them is as follows: for any pre-connection of a register unit, traverse the register unit hierarchy, find the register units that use the pre-connection of that register, and encode these register units into a group in sequence, which is called a register association group. After completing the traversal of the register unit hierarchy, continue to find the register association group corresponding to the pre-connection of the next register unit, and finally form all register association groups.

[0054] 1.3】Constructing a multi-register unit fault injection model

[0055] For any register unit in the gate-level netlist of the circuit to be tested, a unique register association group will be determined for the connection in front of the register unit, and the output port of each register unit in the register association group will be regarded as a fault injection position. For any simulation cycle effective edge, a unique time will be determined as the fault injection time. A multi-register unit fault injection model will be determined according to the fault injection position and the fault injection time, and one multi-register unit fault injection model will correspond to one fault injection file injection.txt. As shown in Figure 4 , it is the fault injection file content. The fault injection file is used to describe that for a specified fault injection time, the output port of the specified fault injection position is forced to flip for one cycle, and is released after one cycle.

[0056] 2】Generate the traversal fault injection file set of all register units

[0057] As shown in Figure 5 , it is the traversal fault injection flowchart of all register units. The input is the gate-level netlist of the circuit to be tested and the all register association group set (U all_reg_groups ) determined by the logic synthesis library, and the all simulation cycle effective edge set (U all_clk_active_edge ) determined by the simulation test program (testcase). The two sets are completely combined to form the combination set of the fault injection position and the fault injection time of the traversal fault injection. The combination set is processed by the multi-register unit fault injection model, and the traversal fault injection file set of all register units (U all_injection ) is output. The size of the traversal fault injection file set of all register units is shown in the following formula:

[0058] U all_injection = U all_clk_active_edge x U all_reg_groups

[0059] Wherein, U all_clk_active_edge represents the all simulation cycle effective edge set, and U all_reg_groups represents the all register association group set.

[0060] 3】Delete the invalid fault injection file in the traversal fault injection file set of all register units

[0061] Since the invalid fault injection file will account for the majority of the fault injection file set in the traversal fault injection file set of all register units, the present application greatly reduces the size of the traversal fault injection file set of all register units by deleting at the circuit structure level, so as to realize the equivalent traversal fault injection method.

[0062] Whether a fault injection in a register cell affects the circuit under test depends on whether the single-event upset (SWE) caused by a valid single-event transient pulse can propagate along the circuit. The blockage of SWE propagation is the main reason why SWE cannot propagate along the circuit.

[0063] A common case of single-event upset propagation blocking is as follows: Figure 6 The diagram illustrates how unused register units can disrupt single-event upset (SWE) propagation. Specifically, the register units involved in SWE are not used during the simulation test program. The output values ​​of unused register units do not affect the circuit results; therefore, identifying and removing fault injection files corresponding to these register units under the specified simulation test program will not affect the simulation results.

[0064] Another common case of single-event upset propagation blocking is as follows: Figure 7 The diagram illustrates how the effective propagation time of a fault leads to the blocking of single-event upset propagation. Specifically, the register cell is not used during the fault injection moment and the effective propagation period, but it is used at other times. Taking a processor as an example, a single-event simulation requires a complete read / write cycle to propagate a circuit output error. Since the maximum clock cycle required for read / write operations is fixed, a fault discrimination margin ε can be determined given the processor's operating frequency. This margin is greater than the maximum delay time that a single-event fault injection simulation can propagate and cause an erroneous logic state in the circuit output (for Leon2, at 100MHz, the fault discrimination margin ε must be greater than 280ns). The fault discrimination margin allows for the estimation of the time range during which fault injections might affect the normal operation of the circuit. Register cells outside this time range have no impact on the circuit's results; therefore, identifying and deleting fault injection files corresponding to these register cells in a specified simulation test program will not affect the simulation results.

[0065] The above analysis assumes that the register unit refreshes its output value on the effective edge of the simulation cycle. However, the timing characteristics of register units in actual circuits vary. Based on whether they contain an enable input, register units can be divided into two main categories: one is register units without an enable input, using DFF-type flip-flops as their standard units, called non-enable register units; the other is register units with an enable output, using EDFF-type flip-flops as their standard units, called enabled register units.

[0066] Based on the above analysis, the fault injection file corresponding to the register unit which does not affect the result is the invalid fault injection file in the traversal fault injection file set of the register unit of the circuit to be tested. According to the non-enabled register unit and the enabled register unit, the invalid fault injection file confirmation method is divided into the following two types:

[0067] I. Invalid fault injection file of non-enabled register unit

[0068] To confirm the invalid fault injection file in the non-enabled register unit, the non-enabled register unit which is not used at all or is not used for a long time in the simulation test program needs to be identified. Specifically, as shown in Figure 8 the switching_time_list of all register units of the circuit to be tested under the specified simulation test program is obtained through fault-free injection simulation; the switching_time_list describes the statistical results of the first two switching times of all register units, and each row of the switching_time_list is divided into three parts by the “|” symbol, which are the hierarchical structure of the register instantiation, the first switching time and the second switching time. Then, the invalid fault injection file of the non-enabled register unit is determined by reading the content of the switching_time_list, that is, whether the register unit is used during the running of the simulation test program (whether there is a first switching) and when the register unit is used (the time of the first switching) are determined by the first two switching times of the register unit. This part mainly aims at two types of register units: one type of register unit does not occur switching during the fault injection simulation, and this type of register unit is not used at all during the entire simulation, so the fault injection file corresponding to the register unit is an invalid fault injection file; the second type of register unit occurs one or more than one switching during the entire simulation, and the fault injection file corresponding to the register unit is an invalid fault injection file from the simulation period within the valid edge before the first switching. At the same time, since there may be a pipeline register unit, the propagation of which has an additional period delay, in order to be conservative, the present application sets a fault discrimination margin ε, and only the fault injection file before the fault discrimination margin ε corresponding to the period before the switching time is regarded as an invalid fault injection file.

[0069] II. Invalid fault injection file of enabled register unit

[0070] To confirm the invalid fault injection file of the enabled register unit, the register unit with an enable signal in the circuit needs to be identified. Specifically, as shown in Figure 9As shown, firstly, an enable register unit enable valid interval list (enable_time_list) of a register unit of a circuit under test is acquired through fault injection simulation; the enable valid interval list describes a time interval statistical result of an enable register unit signal input end E, wherein each row is respectively: a hierarchical structure of the register unit, each time enable valid interval (divided into two parts by "|", which are respectively a start cycle number and an end cycle number of enable validity). Then, it is judged whether the enable register unit enable input end E is in a non-valid cycle (a cycle in which the enable signal is pulled down), if in the non-valid cycle, the fault injection files corresponding to the register association group of the register unit in which the enable register unit is located at the fault injection time are all regarded as invalid fault injection files.

[0071] 4】According to the invalid fault injection files determined in step 3】, the all-register-unit traversal fault injection file set is pruned to obtain a pruned all-register-unit traversal fault injection file set. According to the pruned all-register-unit traversal fault injection file set, equivalent traversal fault injection simulation of the whole circuit register unit is completed.

[0072] The above description is only used to illustrate the technical solutions of the present application, and is not limited thereto. For ordinary skilled persons in the art, the specific technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced with equivalents, and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions protected by the present application.

Claims

1. An equivalent traversal fault injection method for single-event effect simulation of register injection errors, characterized by comprising the following steps:

1. Constructing a multi-register unit fault injection model 1.1 Obtain all register cells of the circuit under test (TBD) from the gate-level netlist; obtain the standard cell structure corresponding to all register cells of the TBD from the logic synthesis technology library; analyze the front-end connections of all register cells of the TBD from all register cells and the corresponding standard cell structures; obtain the effective edges of all simulation cycles from the simulation test program. 1.2】For any register cell in the gate netlist of the circuit under test, find all register cells that share the same register cell in the register cell according to the name of the register cell in ... 1.3 For any register association group in the gate-level netlist of the circuit under test, and any effective edge of the simulation cycle, the input port of each register unit in the register association group is regarded as the fault injection location, and the effective edge of the simulation cycle is regarded as the fault injection time. Based on the fault injection location and the fault injection time, a multi-register unit fault injection model is constructed, and a register fault injection file for the fault injection location and the fault injection time is generated. 2】Combine all register association groups and all effective edges of the simulation cycle, and generate a set of traversal fault injection files for all register units through the multi-register unit fault injection model; 3. Remove invalid fault injection files from the set of fault injection files that iterate through all register units. All register units of the circuit under test are divided into two categories: disabled register units and enabled register units. Corresponding deletion rules are constructed for each category to delete invalid fault injection files from the fault injection file sets corresponding to the register association groups of the disabled and enabled register units. The deletion rule for disabled register units is as follows: A flip list of all register units of the circuit under test is obtained through fault-free injection simulation under the simulation test program; if the corresponding register unit in the flip list does not flip within the valid edges of all simulation cycles, the fault injection file corresponding to the register association group containing that register unit is an invalid fault injection file; if... If a corresponding register cell undergoes one or more flips within all valid edges of the simulation clock, then the fault injection file corresponding to the register association group to which the register cell belongs within the valid edges of the simulation cycle from the start of the simulation to the first flip is an invalid fault injection file. The rule for deleting enable register cells is as follows: obtain a list of all enable register cells of the circuit under test under the simulation test program through fault-free injection simulation; if the enable input terminal of the corresponding enable register cell in the list of enable valid intervals is within an invalid valid edge of the simulation cycle, then the fault injection file corresponding to the register association group to which the enable register cell belongs at these fault injection times is an invalid fault injection file.

4. Based on the traversal fault injection file set of all register units after the deletion, complete the equivalent traversal fault injection of all register units.

2. The equivalent ergodic fault injection method for single-event effect simulation of register injection errors according to claim 1, characterized in that: In step 3, when establishing the deletion rules for the disabled register unit, a fault discrimination margin Ɛ is set, and only the fault injection file before the flip time, which corresponds to the period of the fault discrimination margin Ɛ, is considered an invalid fault injection file.

3. The equivalent ergodic fault injection method for single-event effect simulation of register injection errors according to claim 1 or 2, characterized in that: In step 2], the set of fault injection files for traversing all register units is obtained by the following formula: in, This represents the set of valid edges for all simulation cycles. This represents the set of all register association groups.

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