Pixel driving circuit and its driving method, display device

Abstract

This invention discloses a pixel driving circuit and its driving method, as well as a display device. The pixel driving circuit includes: a driving module, a first light-emitting control module, a second light-emitting control module, a data writing module, a first compensation module, a second compensation module, a first storage module, and a second storage module. The first compensation module is electrically connected to a first terminal of the driving module; the first compensation module is used to transmit a first reference voltage to the first terminal of the driving module; the second compensation module is connected between the control terminal and the second terminal of the driving module; a first initialization module is electrically connected to the second terminal of the driving module; the first storage module is electrically connected to the control terminal of the driving module; the first storage module is used to store the voltage of the control terminal of the driving module. Compared with the prior art, the embodiments of this invention improve display uniformity and reduce the problem of frequency switching flicker, thereby improving display quality.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel driving circuit and its driving method, and a display device. Background Technology

[0002] As display technology continues to develop, people have increasingly higher demands for display devices, such as higher resolution, higher screen-to-body ratio, and foldable displays. However, for mobile clients, there is one constant requirement: longer standby time.

[0003] In existing technologies, frequency switching technology can balance high-quality display effects with low power consumption requirements. For example, a lower refresh rate is used when displaying static images, and a higher refresh rate is used when displaying dynamic images. However, existing technologies suffer from poor display uniformity and frequency switching flicker, which hinders further improvements in display quality. Summary of the Invention

[0004] This invention provides a pixel driving circuit and driving method, as well as a display device, to improve display uniformity and reduce the problem of frequency switching flicker, thereby improving display quality.

[0005] To achieve the above technical objectives, the embodiments of the present invention provide the following technical solutions:

[0006] A pixel driving circuit, comprising:

[0007] The drive module generates drive current in response to the voltage at its control terminal;

[0008] A first light-emitting control module and a second light-emitting control module are connected in series with the driving module and the light-emitting device; the first light-emitting control module is used to transmit a first power signal to the driving module, and the second light-emitting control module is used to transmit the driving current to the light-emitting device.

[0009] A data writing module is electrically connected to the first terminal of the drive module; the data writing module is used to write data voltage to the control terminal of the drive module.

[0010] A first compensation module is electrically connected to a first terminal of the drive module; the first compensation module is used to transmit a first reference voltage to the first terminal of the drive module.

[0011] The second compensation module is connected between the control terminal and the second terminal of the drive module;

[0012] A first initialization module is electrically connected to the second terminal of the drive module; the first initialization module is used to transmit a second reference voltage to the second terminal of the drive module.

[0013] A first storage module is electrically connected to the control terminal of the drive module; the first storage module is used to store the voltage of the control terminal of the drive module.

[0014] The second storage module is electrically connected to the first terminal of the drive module; the second storage module is used to store the voltage at the first terminal of the drive module.

[0015] Optionally, the pixel driving circuit further includes:

[0016] The second initialization module is electrically connected to the light-emitting device; the second initialization module is used to transmit the third reference voltage to the light-emitting device.

[0017] Optionally, both the first light-emitting control module and the second light-emitting control module are connected to a light-emitting control signal and controlled by the light-emitting control signal;

[0018] The first compensation module is connected to the first scanning signal and is controlled by the first scanning signal;

[0019] The second compensation module is connected to the second scanning signal and is controlled by the second scanning signal;

[0020] The first initialization module is connected to and controlled by the third scanning signal;

[0021] The second initialization module is connected to the fourth scan signal and is controlled by the fourth scan signal;

[0022] The data writing module is connected to and controlled by the fifth scan signal;

[0023] Preferably, the pulse width of at least one of the first scanning signal, the second scanning signal, the third scanning signal, the fourth scanning signal, and the light emission control signal is adjustable;

[0024] Preferably, the first scan signal is multiplexed as the fourth scan signal.

[0025] Optionally, the driving module includes a first transistor, the gate of the first transistor serving as the control terminal of the driving module, the first electrode of the first transistor serving as the first terminal of the driving module, and the second electrode of the first transistor serving as the second terminal of the driving module.

[0026] The second compensation module includes a second transistor, the gate of the second transistor is connected to the second scan signal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the second transistor is electrically connected to the gate of the first transistor.

[0027] The first initialization module includes a third transistor, the gate of which is connected to the third scan signal, the first terminal of which is connected to the second reference voltage, and the second terminal of which is electrically connected to the first terminal of the second transistor.

[0028] The data writing module includes a fourth transistor, the gate of which is connected to the fifth scan signal, the first terminal of which is connected to the data voltage, and the second terminal of which is electrically connected to the first terminal of the first transistor.

[0029] The first light-emitting control module includes a fifth transistor, the gate of which is connected to the light-emitting control signal, the first terminal of which is connected to the first power supply signal, and the second terminal of which is electrically connected to the first terminal of the first transistor.

[0030] The second light-emitting control module includes a sixth transistor, the gate of which is connected to the light-emitting control signal, the first terminal of which is electrically connected to the second terminal of the first transistor, and the second terminal of which is electrically connected to the light-emitting device.

[0031] The first compensation module includes a seventh transistor, the gate of which is connected to the first scan signal, the first terminal of which is connected to the first reference voltage, and the second terminal of which is electrically connected to the first terminal of the first transistor.

[0032] The second initialization module includes an eighth transistor, the gate of which is connected to the fourth scan signal, the first terminal of which is connected to the third reference voltage, and the second terminal of which is electrically connected to the light-emitting device.

[0033] Preferably, the first transistor, the third transistor to the eighth transistor are all P-type transistors, and the second transistor is an N-type transistor.

[0034] Optionally, the first storage module includes a first capacitor, a first terminal of the first capacitor is connected to the first power signal, and a second terminal of the first capacitor is electrically connected to the control terminal of the drive module.

[0035] The second storage module includes a second capacitor, the first end of which is connected to the first power signal, and the second end of which is electrically connected to the first end of the drive module.

[0036] Accordingly, the present invention also provides a display device, including a pixel driving circuit as described in any embodiment of the present invention.

[0037] Accordingly, the present invention also provides a driving method for a pixel driving circuit, used to drive the pixel driving circuit as described in any embodiment of the present invention; the driving method includes writing a frame, and the driving process of the writing frame includes:

[0038] In the first compensation stage, the first compensation module and the second compensation module are turned on, and the first reference voltage is transmitted sequentially to the first terminal, the second terminal and the control terminal of the driving module to reset the driving module and pre-compensate the threshold voltage.

[0039] In the first reset phase, the first initialization module and the second compensation module are turned on to transmit the second reference voltage to the control terminal of the drive module.

[0040] During the data writing phase, the data writing module and the second compensation module are turned on, and the data voltage is written sequentially to the first terminal, the second terminal and the control terminal of the driving module, while the driving module is compensated for the threshold voltage.

[0041] In the second compensation phase, the second compensation module is turned on so that the data voltage stored at the first end of the drive module continues to charge its control end and compensate for the threshold voltage.

[0042] In the first light-emitting stage, the first light-emitting control module and the second light-emitting control module are turned on, and the driving module generates a driving current in response to the voltage at its control terminal.

[0043] Optionally, the pixel driving circuit further includes a second initialization module, the second initialization module being electrically connected to the light-emitting device; the driving method further includes:

[0044] During the first compensation phase, the second initialization module is turned on to transmit the third reference voltage to the light-emitting device in order to reset the light-emitting device.

[0045] Preferably, the write frame further includes a second reset phase, which is located after the second compensation phase and before the first light emission phase; in the second reset phase, the first compensation module and the second initialization module are controlled to be turned on, the first reference voltage is transmitted to the first terminal of the driving module, and the third reference voltage is transmitted to the light emission device;

[0046] Preferably, the times of the first compensation phase, the first reset phase, the second compensation phase, and the second reset phase are adjustable.

[0047] Optionally, the driving method further includes a holding frame; the driving process of the holding frame includes:

[0048] In the third reset phase, the first compensation module and the second initialization module are turned on, the first reference voltage is transmitted to the first terminal of the driving module, and the third reference voltage is transmitted to the light-emitting device.

[0049] In the second light-emitting stage, the first light-emitting control module and the second light-emitting control module are turned on, and the driving module generates a driving current in response to the voltage at its control terminal.

[0050] Preferably, the timing of the third reset phase and the second light emission phase is adjustable.

[0051] Optionally, the driving method includes high-frequency refresh and low-frequency refresh; the high-frequency refresh is composed of the write frame, and the low-frequency refresh is composed of the write frame and the hold frame;

[0052] Preferably, when performing the low-frequency refresh, the duration of the write frame and the hold frame are the same, or the duration of the write frame is an integer multiple of the duration of the hold frame.

[0053] This invention, in its embodiment, includes a driving module, a first light-emitting control module, a second light-emitting control module, a data writing module, a first compensation module, a second compensation module, a first initialization module, a first storage module, and a second storage module in the pixel driving circuit. Unlike existing technologies, the first compensation module is electrically connected to the first terminal of the driving module, the second compensation module is connected between the control terminal and the second terminal of the driving module, and the second storage module is electrically connected to the first terminal of the driving module. This configuration allows for a first compensation stage to be inserted before the data writing stage during the driving process to pre-compensate the threshold voltage of the driving module, simultaneously initializing the control terminal, the first terminal, and the second terminal of the driving module. This restores the transient characteristics of the driving module to consistency, thus helping to improve the problem of frequency switching flicker. Furthermore, the second compensation stage is inserted after the data writing stage and before the first light-emitting stage, allowing the data voltage stored at the first terminal of the driving module to continue charging its control terminal and compensating for the threshold voltage. This eliminates errors caused by insufficient data writing and threshold voltage compensation, improving the accuracy of data writing and threshold compensation, thereby enhancing the uniformity of the display. In summary, the embodiments of the present invention are applicable to display devices with switchable refresh rates, improving display uniformity, reducing flickering during frequency switching, and promoting further improvement in display quality.

[0054] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0057] Figure 2 A schematic diagram of the state of a pixel driving circuit in the first compensation stage provided in an embodiment of the present invention;

[0058] Figure 3 A schematic diagram of the state of a pixel driving circuit in the first reset stage provided in an embodiment of the present invention;

[0059] Figure 4 A schematic diagram of the state of a pixel driving circuit during the data writing stage, provided in an embodiment of the present invention;

[0060] Figure 5 A schematic diagram of the state of a pixel driving circuit in the second compensation stage, provided as an embodiment of the present invention;

[0061] Figure 6 A schematic diagram of the state of a pixel driving circuit in the first light-emitting stage provided in an embodiment of the present invention;

[0062] Figure 7 A schematic diagram of the state of a pixel driving circuit in the second reset stage provided in an embodiment of the present invention;

[0063] Figure 8 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0064] Figure 9 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0065] Figure 10 A schematic diagram of the driving timing of a pixel driving circuit provided in an embodiment of the present invention;

[0066] Figure 11 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention;

[0067] Figure 12 A schematic diagram of the driving timing of another pixel driving circuit provided in an embodiment of the present invention;

[0068] Figure 13A schematic diagram of the driving timing of another pixel driving circuit provided in an embodiment of the present invention;

[0069] Figure 14 A schematic diagram of the driving timing of another pixel driving circuit provided in an embodiment of the present invention;

[0070] Figure 15 This is a schematic diagram of the driving timing of another pixel driving circuit provided in an embodiment of the present invention. Detailed Implementation

[0071] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0072] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0073] As described in the background section, existing technologies suffer from poor display uniformity and flickering during frequency switching. The inventors have discovered that the uniformity problem arises because, in order to achieve a high PPI and refresh rate, the data writing phase duration is continuously compressed, resulting in insufficient data writing and threshold compensation in the pixel driving circuit. Specifically, the data voltages corresponding to high and low grayscale levels differ significantly, leading to varying degrees of adequacy in data writing and threshold compensation. For example, at high grayscale levels, data writing and threshold compensation are relatively sufficient; at low grayscale levels, they are insufficient. Therefore, existing technologies suffer from display uniformity issues.

[0074] In addition, the inventors also discovered during the research process that the reason for the frequency switching flicker in the prior art is that the transient characteristics of the driving transistors in the pixel driving circuit are inconsistent under different display modes (high frequency display and low frequency display), that is, the source and drain voltages of the driving transistors are inconsistent, which leads to the problem of frequency switching flicker.

[0075] In view of this, embodiments of the present invention provide a pixel driving circuit. Based on this pixel driving circuit and combined with a corresponding driving method, display uniformity can be improved and the problem of frequency switching flicker can be reduced. Figure 1 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention. See also... Figure 1 The pixel driving circuit includes: a driving module 100, a first light emission control module 210, a second light emission control module 220, a data writing module 300, a first compensation module 410, a second compensation module 420, a first initialization module 510, a first storage module 610, and a second storage module 620.

[0076] Specifically, the driving module 100 generates a driving current in response to the voltage at its control terminal 103. A first light-emitting control module 210, a second light-emitting control module 220, the driving module 100, and a light-emitting device D1 are connected in series; the first light-emitting control module 210 transmits a first power signal VDD to the driving module 100, and the second light-emitting control module 220 transmits the driving current to the light-emitting device D1. A data writing module 300 is electrically connected to the first terminal 101 of the driving module 100; the data writing module 300 writes a data voltage Vdata to the control terminal 103 of the driving module 100. A first compensation module 410 is electrically connected to the first terminal 101 of the driving module 100; the first compensation module 410 transmits a first reference voltage Vref1 to the first terminal 101 of the driving module 100. A second compensation module 420 is connected between the control terminal 103 and the second terminal 102 of the driving module 100. The first initialization module 510 is electrically connected to the second terminal 102 of the drive module 100; the first initialization module 510 is used to transmit the second reference voltage Vref2 to the second terminal 102 of the drive module 100. The first storage module 610 is electrically connected to the control terminal 103 of the drive module 100; the first storage module 610 is used to store the voltage of the control terminal 103 of the drive module 100. The second storage module 620 is electrically connected to the first terminal 101 of the drive module 100; the second storage module 620 is used to store the voltage of the first terminal 101 of the drive module 100.

[0077] For example, the operation of the pixel driving circuit includes: a first compensation stage, a first reset stage, a data writing stage, a second compensation stage, and a first light emission stage.

[0078] Figure 2This is a schematic diagram of the state of a pixel driving circuit in the first compensation stage, as provided in an embodiment of the present invention. See also... Figure 2 In the first compensation stage T1, the first compensation module 410 and the second compensation module 420 are turned on, and the first reference voltage Vref1 is sequentially transmitted to the first terminal 101, the second terminal 102, and the control terminal 103 of the drive module 100 to reset the drive module 100 and pre-compensate the threshold voltage. The process of compensating the threshold voltage of the drive module 100 involves making the voltage difference between the control terminal 103 and the first terminal 101 of the drive module 100 equal to the threshold voltage. Pre-compensating the drive module 100 helps shorten the subsequent threshold voltage compensation time and ensures more thorough threshold voltage compensation. Simultaneously, initializing the first terminal 101 and the second terminal 102 of the drive module 100 restores the transient characteristics of the drive module 100 to consistency, which helps improve the problem of frequency switching flicker.

[0079] Figure 3 This is a schematic diagram of the state of a pixel driving circuit in the first reset stage, as provided in an embodiment of the present invention. See also... Figure 3 In the first reset phase T2, the first initialization module 510 and the second compensation module 420 are turned on, transmitting the second reference voltage Vref2 to the control terminal 103 of the drive module 100 to reset the control terminal 103 of the drive module 100. Unlike the first compensation phase T1, in the first reset phase T2, only the control terminal 103 of the drive module 100 can be reset. Specifically, taking a P-type transistor as an example, the voltage value of the second reference voltage Vref2 should be lower than the voltage value of the first reference voltage Vref1 to ensure that the drive module 100 is in the on state during the data writing phase T3.

[0080] Figure 4 This is a schematic diagram illustrating the state of a pixel driving circuit during the data writing stage, as provided in an embodiment of the present invention. See also... Figure 4During the data writing phase T3, the control data writing module 300 and the second compensation module 420 are turned on, and the data voltage Vdata is sequentially written to the first terminal 101, the second terminal 102, and the control terminal 103 of the driver module 100 to perform data writing. Since the driver module 100 wrote the second reference voltage Vref2 during the first reset phase T2, the first terminal 101 of the driver module 100 is in a conducting state when writing the data voltage Vdata. This data writing process is also the threshold compensation process of the driver module 100, and the longer the data writing phase T3 lasts, the more sufficient the threshold compensation of the driver module 100. However, in practical applications, in order to achieve high PPI and high refresh rate, the duration of the data writing phase T3 is continuously compressed, resulting in insufficient data writing and threshold compensation by the driver module 100. The specific reasons are explained as follows. Taking the driving module 100 as a P-type transistor as an example, during the process of writing the data voltage Vdata to the control terminal 103 of the driving module 100, the voltage of the control terminal 103 gradually increases from the second reference voltage Vref2, approaching the data voltage Vdata. The voltage difference between the control terminal 103 and the first terminal 101 of the driving module 100 decreases, the turn-on degree of the driving module 100 decreases, and the current decreases. Therefore, it takes a relatively long time for the data voltage Vdata to be completely written to the control terminal 103 of the driving module 100. At the end of the data writing stage T3, the voltage of the control terminal 103 of the driving module 100 is Vdata + Vth + Error. Wherein, Vth is the threshold voltage of the driving module 100, and Error is the error amount when the data voltage Vdata is not fully written. In this embodiment of the invention, the second storage module 620 is configured to store the voltage of the first terminal 101 of the driving module 100. During the data writing stage T3, when the data writing module 300 is turned on, the storage module 620 stores the data voltage Vdata at the first terminal 101 of the driving module 100.

[0081] Figure 5 This is a schematic diagram of the state of a pixel driving circuit in the second compensation stage, as provided in an embodiment of the present invention. See also... Figure 5In the second compensation stage T4, the second compensation module 420 is turned on to continue charging and threshold voltage compensation of the data voltage Vdata stored at the first terminal 101 of the drive module 100. The second compensation stage T4 is a supplementary stage to the data writing stage T3. Since the voltage at the first terminal 101 of the drive module 100 maintains the data voltage Vdata, and the second compensation module 420 continues to be turned on, the data voltage Vdata can be transmitted to the control terminal 103 of the drive module 100 through the drive module 100 and the second compensation module 420 until the data voltage Vdata is fully written to the control terminal 103 of the drive module 100. At this time, the voltage at the control terminal 103 of the drive module 100 is Vdata + Vth, and the error is eliminated. Therefore, this embodiment of the invention improves the accuracy of data writing and threshold compensation. Whether it is a high grayscale display or a low grayscale display, sufficient data writing and threshold voltage compensation can be obtained, thereby improving the uniformity of the display. Furthermore, this embodiment of the invention does not require increasing the duration of the data writing stage T3, which is beneficial for achieving high refresh rates and high PPI.

[0082] Figure 6 This is a schematic diagram of the state of a pixel driving circuit in the first light-emitting stage, as provided in an embodiment of the present invention. See also... Figure 6 In the first light-emitting stage T5, the first light-emitting control module 210 and the second light-emitting control module 220 are turned on, and the driving module 100 generates a driving current I in response to the voltage at its control terminal 103. I = K*(V GS -Vth) 2 =K*(Vdata+Vth-VDD-Vth) 2 =K*(Vdata-VDD) 2 Among them, V GS K represents the voltage difference between the first terminal 101 and the control terminal 103 of the drive module 100. K is related to the size and mobility of the drive module 100 and is determined by the manufacturing process; Vdata and VDD are both set values. Therefore, because the data writing and threshold compensation at the control terminal 103 of the drive module 100 are sufficient, the error is eliminated, resulting in an accurate calculation of the final drive current formula, which is beneficial for precise control of the drive current.

[0083] This embodiment of the invention includes a driving module 100, a first light-emitting control module 210, a second light-emitting control module 220, a data writing module 300, a first compensation module 410, a second compensation module 420, a first initialization module 510, a first storage module 610, and a second storage module 620 in the pixel driving circuit. Unlike existing technologies, the first compensation module 410 is electrically connected to the first terminal 101 of the driving module 100, the second compensation module 420 is connected between the control terminal 103 and the second terminal 102 of the driving module 100, and the second storage module 620 is electrically connected to the first terminal 101 of the driving module 100. This configuration allows for pre-compensation of the threshold voltage of the driving module 100 during the driving process, before the data writing stage T3, and simultaneous initialization of the control terminal 103, the first terminal 101, and the second terminal 102 of the driving module 100. This restores the transient characteristics of the driving module 100 to a consistent state, thus helping to improve the problem of frequency switching flicker. Furthermore, a second compensation stage T4 is inserted after the data writing stage T3 and before the first light-emitting stage T5. This allows the data voltage Vdata stored at the first terminal 101 of the driving module 100 to continue charging its control terminal 103 and compensating for the threshold voltage. This eliminates the error caused by insufficient data writing and threshold voltage compensation, improving the accuracy of data writing and threshold compensation, thereby enhancing the uniformity of the display. In summary, the embodiments of the present invention are applicable to display devices with switchable refresh rates, improving display uniformity, mitigating the problem of frequency switching flicker, and contributing to further improvements in display quality.

[0084] Figure 7This is a schematic diagram of the state of a pixel driving circuit in the second reset stage according to an embodiment of the present invention. Optionally, based on the above embodiments, the driving process of the pixel driving circuit further includes a second reset stage T6, which is located after the second compensation stage T4 and before the first light-emitting stage T5. In the second reset stage T6, the first compensation module 410 is turned on, transmitting the second reference voltage Vref2 to the first terminal 101 and the second terminal 102 of the driving module 100 to reset the first terminal 101 and the second terminal 102 of the driving module 100. This configuration in the embodiment of the present invention is beneficial for further improving the uniformity of the display. The following analysis uses a P-type transistor as an example of the driving module 100. If the second reset stage T6 is not set before the first light-emitting stage T5, at the beginning of the first light-emitting stage T5, when the first light-emitting control module 210 is turned on, the voltage of the first terminal 101 of the driving module 100 rises from the data voltage Vdata to the first power signal VDD voltage, and the driving current generated by the driving module 100 gradually increases. In this embodiment of the invention, after the second compensation stage T4 and before the first light emission stage T5, the first terminal 101 and the second terminal 102 of the driving module 100 are reset, so that the driving module 100 can quickly generate a precise driving current at the beginning of the first light emission stage T5, thereby further improving the uniformity of the display.

[0085] Figure 8 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. See also... Figure 8 Based on the above embodiments, optionally, the pixel driving circuit further includes: a second initialization module 520, which is electrically connected to the light-emitting device D1; the second initialization module 520 is used to transmit the third reference voltage Vref3 to the light-emitting device D1. The light-emitting device D1 includes an anode and a cathode, and the connection relationship between the second initialization module 520 and the light-emitting device D1 varies depending on the location of the light-emitting device D1 in the pixel driving circuit. Figure 8 As shown, the anode of the light-emitting device D1 is electrically connected to other modules in the pixel driving circuit, and the cathode of the light-emitting device is connected to the second power signal VSS. The voltage of the first power signal VDD is higher than the voltage of the second power signal VSS. Correspondingly, the second initialization module 520 is electrically connected to the anode of the light-emitting device D1 and is used to reset the anode of the light-emitting device D1. In other embodiments, the voltage of the first power signal is lower than the second power signal, the anode of the light-emitting device D1 is connected to the second power signal, and the cathode of the light-emitting device D1 is electrically connected to the second initialization module 520. The second initialization module 520 is used to initialize the cathode of the light-emitting device D1.

[0086] During the driving process of the pixel driving circuit, the second initialization module 520 can be turned on in at least one of the first compensation stage T1, the first reset stage T2, the data writing stage T3, the second compensation stage T4, and the second reset stage T6 to reset the light-emitting device D1.

[0087] In the above embodiments, each module in the pixel driving circuit can be controlled by scanning signals and light emission control signals. The control signals corresponding to each module are described below. Figure 9 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. See also... Figure 9 In one embodiment of the present invention, optionally, the first light-emitting control module 210 and the second light-emitting control module 220 are both connected to the light-emitting control signal EM and controlled by the light-emitting control signal EM; the first compensation module 410 is connected to the first scan signal S1 and controlled by the first scan signal S1; the second compensation module 420 is connected to the second scan signal S2 and controlled by the second scan signal S2; the first initialization module 510 is connected to the third scan signal S3 and controlled by the third scan signal S3; the second initialization module 520 is connected to the fourth scan signal S4 and controlled by the fourth scan signal S4; and the data writing module 300 is connected to the fifth scan signal S5 and controlled by the fifth scan signal S5. Preferably, the first scan signal S1 is multiplexed as the fourth scan signal S4. It should be noted that when the first scan signal S1 and the fourth scan signal S4 are set separately, the stage for resetting the light-emitting device D1 can be at least one of the following: the first compensation stage T1, the first reset stage T2, the data writing stage T3, the second compensation stage T4, and the second reset stage T6. When the first scan signal S1 and the fourth scan signal S4 are multiplexed, the only stages for resetting the light-emitting device D1 are the first compensation stage T1 and the second reset stage T6.

[0088] In other embodiments, the first light-emitting control module 210 and the second light-emitting control module 220 may be controlled by different light-emitting control signals. In this embodiment of the invention, as a preferred embodiment, the first light-emitting control module 210 and the second light-emitting control module 220 are connected to the same light-emitting control signal EM, and the first compensation module 410 and the second initialization module 520 are both connected to the first scan signal S1. This reduces the number of control signal lines while achieving display uniformity and improving the driving requirements for frequency switching flicker, thereby simplifying the layout design of the display panel.

[0089] The driving method of the pixel driving circuit provided in the embodiments of the present invention will be described below with reference to the driving timing diagram. Figure 10 This is a schematic diagram of the driving timing of a pixel driving circuit provided in an embodiment of the present invention. (In conjunction with...) Figure 9 and Figure 10In one embodiment of the present invention, optionally, for each module, a low level is an effective level, that is, when the control signal is low, the corresponding module is turned on; conversely, when the control signal is high, the corresponding module is turned off.

[0090] In the first compensation stage T1, the first scan signal S1 and the second scan signal S2 are both at low level, while the third scan signal S3, the fifth scan signal S5, and the light emission control signal EM are all at high level. The third scan signal S3 controls the first initialization module 510 to disconnect, the fifth scan signal S5 controls the data writing module 300 to disconnect, and the light emission control signal EM controls the first light emission control module 210 and the second light emission control module 220 to disconnect. The first scan signal S1 controls the first compensation module 410 to turn on, and the second scan signal S2 controls the second compensation module 420 to turn on. The first reference voltage Vref1 passes sequentially through the first compensation module 410, the first terminal 101 and the second terminal 102 of the driving module 100, the second compensation module 420, and the control terminal 103 of the driving module 100 to reset the driving module 100 and pre-compensate the threshold voltage. At the same time, the first scan signal S1 controls the second initialization module 520 to turn on, writing the third reference voltage Vref3 into the anode of the light-emitting device D1, thus resetting the anode of the light-emitting device D1.

[0091] In the second reset phase T2, only the levels of the first scan signal S1 and the third scan signal S3 change, and the states of the corresponding modules change accordingly. The states of other modules remain consistent with those in the first compensation phase T1. Specifically, the first scan signal S1 switches from low to high, so the first compensation module 410 switches from the on state to the off state, and the first reference voltage Vref1 is no longer written to the pixel driving circuit. The third scan signal S3 switches from high to low, so the first initialization module 510 switches from the off state to the on state, and the second reference voltage Vref2 is written to the control terminal 103 of the driving module 100 via the first initialization module 510 and the second compensation module 420 to reset the control terminal 103 of the driving module 100.

[0092] During the data writing phase T3, only the levels of the third scan signal S3 and the fifth scan signal S5 change, corresponding to changes in the state of the modules. The states of other modules remain consistent with the first reset phase T2. Specifically, the third scan signal S3 switches from low to high, thus the first initialization module 510 switches from the on state to the off state, and the third reference voltage Vref3 is no longer written to the pixel driving circuit. The fifth scan signal S5 switches from high to low, thus the data writing module 300 switches from the off state to the on state. The data voltage Vdata is written to the control terminal of the driving module 100 via the data writing module 300, the first terminal 101 and the second terminal 102 of the driving module 100, and the second compensation module 420 to perform data writing. At the end of the data writing phase T3, the voltage at the control terminal of the driving module 100 is Vdata + Vth + Error, achieving threshold voltage compensation for the driving module 100. Simultaneously, the second storage module 620 can store the voltage at the first terminal 101 of the driving module 100, meaning the first terminal 101 of the driving module 100 remains at the data voltage Vdata.

[0093] In the second compensation stage T4, only the level of the fifth scan signal S5 changes, and the state of the corresponding data writing module 300 changes accordingly. The states of other modules remain consistent with those in the data writing stage T3. Specifically, the fifth scan signal S5 switches from a high level to a low level, so the data writing module 300 switches from an on state to an off state, and the data voltage Vdata is no longer written to the pixel driving circuit. However, due to the storage function of the second storage module 620, the voltage at the first terminal 101 of the driving module 100 remains at the data voltage Vdata. At the same time, the second compensation module 420 remains on, so that the data voltage Vdata continues to charge and compensate the threshold voltage at the control terminal 103 of the driving module 100 until the voltage at the control terminal of the driving module 100 is Vdata + Vth, and the error is eliminated.

[0094] During the second reset phase T6, only the levels of the first scan signal S1 and the second scan signal S2 change, and the states of the corresponding modules change accordingly. The states of other modules remain consistent with those during the second compensation phase T4. Specifically, the second scan signal S2 switches from a low level to a high level, thus the second compensation module 420 switches from an on state to an off state, and the connection between the second terminal 102 and the control terminal 103 of the drive module 100 is broken. The first scan signal S1 switches from a high level to a low level, and the first compensation module 410 switches from an off state to an on state, transmitting the second reference voltage Vref2 to the first terminal 101 and the second terminal 102 of the drive module 100 to reset the first terminal 101 and the second terminal 102 of the drive module 100. At the same time, the second initialization module 520 switches from an off state to an on state, writing the third reference voltage Vref3 into the anode of the light-emitting device D1 to reset the anode of the light-emitting device D1.

[0095] In the first light-emitting stage T5, the levels of the first scan signal S1 and the light-emitting control signal EM change, and the states of the corresponding modules change accordingly. The states of other modules remain consistent with the second reset stage T6. Specifically, the first scan signal S1 switches from low level to high level, so the first compensation module 410 and the second initialization module 520 switch from the on state to the off state, and the first reference voltage Vref1 and the third reference voltage Vref3 are no longer written to the pixel driving circuit. The light-emitting control signal EM switches from high level to low level, so the first light-emitting control module 210 and the second light-emitting control module 220 switch from the off state to the on state. The first power supply signal VDD is written to the first terminal 101 of the driving module 100 through the first light-emitting control module 210. The second terminal 102 of the driving module 100 is connected to the light-emitting device D1. The driving module 100 can generate a driving current according to the voltage of its control terminal 103. This driving current flows into the light-emitting device D1, thereby driving the light-emitting device D1 to emit light.

[0096] This invention, through its embodiment, controls the operation of the pixel driving circuit by setting the first light-emitting control module 210 and the second light-emitting control module 220 to be controlled by the light-emitting control signal EM; the first compensation module 410 to be controlled by the first scan signal S1; the second compensation module 420 to be controlled by the second scan signal S2; the first initialization module 510 to be controlled by the third scan signal S3; the second initialization module 520 to be controlled by the fourth scan signal S4; and the data writing module 300 to be controlled by the fifth scan signal S5, and by setting the timing of each control signal. Furthermore, this invention is applicable to display devices with switchable refresh rates, improving display uniformity, mitigating frequency switching flicker, and further enhancing display quality.

[0097] See also Figure 10Based on the above embodiments, optionally, the pulse width of at least one of the first scan signal S1, the second scan signal S2, the third scan signal S3, the fourth scan signal S4, and the light emission control signal EM is adjustable. Here, adjustable pulse width means that the pulse width of the effective level is adjustable, so as to... Figure 10 For example, the effective level of each control signal is low. In some embodiments, intermediate states exist between the first compensation stage T1 and the first reset stage T2, between the first reset stage T2 and the data writing stage T3, between the second compensation stage T4 and the second reset stage T6, and between the second reset stage T6 and the first light emission stage T5. This provides the possibility for adjusting the pulse width of each control signal. For example, by compressing the intermediate state between the first compensation stage T1 and the first reset stage T2, the pulse width of the first scan signal S1 (fourth scan signal S4) or the pulse width of the third scan signal S3 can be widened; similarly, by increasing the intermediate state between the first compensation stage T1 and the first reset stage T2, the pulse width of the first scan signal S1 (fourth scan signal S4) or the pulse width of the third scan signal S3 can be narrowed. This setting allows for adjustable pulse widths of each control signal without changing the row write time.

[0098] In this embodiment, the pulse width of the first scan signal S1 (fourth scan signal S4) determines the duration of the first compensation stage T1 and the second reset stage T6; the pulse width of the second scan signal S2 determines the total duration of the first compensation stage T1, the first reset stage T2, the data writing stage T3, and the second compensation stage T4; the pulse width of the third scan signal S3 determines the duration of the first reset stage T2; and the pulse width of the light emission control signal EM determines the duration of the first light emission stage T5. This embodiment of the invention allows for adjustable pulse widths of each control signal, enabling adjustments to the reset duration of the first, second, and control terminals of the driving module 100, as well as the threshold compensation duration of the driving module 100. In practical applications, these adjustments can be made as needed, thereby improving the application effect.

[0099] It should be noted that the pulse width of the fifth scan signal S5 determines the duration of the data writing stage T3. In practical applications, in order to achieve high PPI and high refresh rate, the duration of the data writing stage T3 is continuously compressed. Therefore, in this embodiment of the invention, the pulse width of the fifth scan signal S5 is set to be non-adjustable, which is beneficial to ensure the high PPI and high refresh rate of the display device.

[0100] It should also be noted that the above embodiments are described using a low-level signal as an example, and are not intended to limit the invention. In other embodiments, the control signals can be set according to the specific configuration of each module. Any technical solution that can achieve the above driving principle is within the protection scope of this invention.

[0101] In the above embodiments, there are various ways to set each module, which will be described in detail below, but this is not intended to limit the present invention.

[0102] Figure 11 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention. See also... Figure 11 In one embodiment, optionally, the driving module 100 includes a first transistor M1, the gate G of the first transistor M1 serving as the control terminal of the driving module 100, the first electrode of the first transistor M1 serving as the first terminal of the driving module 100, and the second electrode of the first transistor M1 serving as the second terminal of the driving module 100.

[0103] The first transistor M1 can be either a P-type transistor or an N-type transistor. For a P-type transistor, the electrode connected to a high voltage is the source (S), and the electrode connected to a low voltage is the drain (D). For an N-type transistor, the electrode connected to a high voltage is the drain (D), and the electrode connected to a low voltage is the source (S). Figure 11 In one embodiment, the first transistor M1 is a P-type transistor, the first power supply signal VDD is a positive voltage, the second power supply signal VSS is a negative voltage, and the first terminal of the first transistor M1 is electrically connected to the first light-emitting control module 210. Therefore, the first terminal of the first transistor M1 is the source (S), and the second terminal is the drain (D). In other embodiments, the first transistor M1 is an N-type transistor, the first power supply signal VDD is a positive voltage, the second power supply signal VSS is a negative voltage, and the second terminal of the first transistor M1 is electrically connected to the first light-emitting control module 210. Therefore, the first terminal of the first transistor M1 is the source (S), and the second terminal is the drain (D). Adaptively adjusting the connection relationships of each module for different types of first transistors M1 is common knowledge to those skilled in the art and will not be elaborated further.

[0104] See also Figure 11 In one embodiment, optionally, the second compensation module 420 includes a second transistor M2, the gate of which is connected to a second scan signal S2, the first terminal of the second transistor M2 being electrically connected to the second terminal of the first transistor M1, and the second terminal of the second transistor M2 being electrically connected to the gate of the first transistor M1. The second transistor M2 is either a P-type transistor or an N-type transistor. Compared to a P-type transistor, an N-type transistor has a smaller leakage current; therefore, it is preferable that the second transistor M2 is an N-type transistor to reduce the leakage current at the gate of the first transistor M1.

[0105] See also Figure 11In one embodiment, optionally, the first initialization module 510 includes a third transistor M3, the gate of the third transistor M3 is connected to a third scan signal S3, the first terminal of the third transistor M3 is connected to a second reference voltage Vref2, and the second terminal of the third transistor M3 is electrically connected to the first terminal of the second transistor M2. The third transistor M3 is either a P-type transistor or an N-type transistor.

[0106] See also Figure 11 In one embodiment, optionally, the data writing module 300 includes a fourth transistor M4, the gate of the fourth transistor M4 is connected to a fifth scan signal S5, the first terminal of the fourth transistor M4 is connected to a data voltage Vdata, and the second terminal of the fourth transistor M4 is electrically connected to the first terminal of the first transistor M1. The fourth transistor M4 is either a P-type transistor or an N-type transistor.

[0107] See also Figure 11 In one embodiment, optionally, the first light-emitting control module 210 includes a fifth transistor M5, the gate of the fifth transistor M5 is connected to a light-emitting control signal EM, the first terminal of the fifth transistor M5 is connected to a first power supply signal VDD, and the second terminal of the fifth transistor M5 is electrically connected to the first terminal of the first transistor M1. The fifth transistor M5 is either a P-type transistor or an N-type transistor.

[0108] See also Figure 11 In one embodiment, optionally, the second light-emitting control module 220 includes a sixth transistor M6. The gate of the sixth transistor M6 is connected to the light-emitting control signal EM. The first terminal of the sixth transistor M6 is electrically connected to the second terminal of the first transistor M1, and the second terminal of the sixth transistor M6 is electrically connected to the light-emitting device D1. The sixth transistor M6 is either a P-type transistor or an N-type transistor. Preferably, both the fifth transistor M5 and the sixth transistor M6 are either P-type transistors or both are N-type transistors, thus allowing them to share the light-emitting control signal EM.

[0109] See also Figure 11 In one embodiment, optionally, the first compensation module 410 includes a seventh transistor M7, the gate of the seventh transistor M7 is connected to a first scan signal S1, the first terminal of the seventh transistor M7 is connected to a first reference voltage Vref1, and the second terminal of the seventh transistor M7 is electrically connected to the first terminal of the first transistor M1. The seventh transistor M7 is either a P-type transistor or an N-type transistor.

[0110] See also Figure 11In one embodiment, optionally, the second initialization module 520 includes an eighth transistor M8. The gate of the eighth transistor M8 is connected to a fourth scan signal S4, the first terminal of the eighth transistor M8 is connected to a third reference voltage Vref3, and the second terminal of the eighth transistor M8 is electrically connected to a light-emitting device D1. The eighth transistor M8 is either a P-type transistor or an N-type transistor. Preferably, both the seventh transistor M7 and the eighth transistor M8 are either P-type transistors or both are N-type transistors, thus allowing them to share the first scan signal S1.

[0111] See also Figure 11 In one embodiment, optionally, the first storage module 610 includes a first capacitor Cst1, the first end of the first capacitor Cst1 is connected to a first power signal VDD, and the second end of the first capacitor Cst1 is electrically connected to the control terminal of the drive module 100.

[0112] See also Figure 11 In one embodiment, optionally, the second storage module 620 includes a second capacitor Cst2, the first end of the second capacitor Cst2 is connected to a first power signal VDD, and the second end of the second capacitor Cst2 is electrically connected to the first end of the drive module 100.

[0113] In this embodiment of the invention, each module includes a transistor or a capacitor, which has a simple structure and is easy to implement.

[0114] See also Figure 11 Preferably, the first transistor M1, the third transistor M3 to the eighth transistor M8 are all P-type transistors, and the second transistor M2 is an N-type transistor. Compared to N-type transistors, P-type transistors have better transient characteristics and faster switching speeds; compared to P-type transistors, N-type transistors have lower leakage currents. This configuration in this embodiment of the invention can reduce the gate leakage current of the first transistor M1 while ensuring the switching speed of each transistor, thus balancing the transient and steady-state characteristics of the pixel driving circuit.

[0115] It should be noted that, as Figure 11 As shown, the first transistor M1 is a P-type transistor, and in the first light-emitting stage T5, the first power supply signal VDD and the source of the first transistor M1 are turned on. Correspondingly, the first capacitor Cst1 is connected between the first power supply signal VDD and the gate of the first transistor M1, which is equivalent to maintaining the gate-source voltage difference of the first transistor M1 in the first light-emitting stage T5. In other embodiments, it is sufficient to simply connect the first capacitor Cst1 between the gate and the source of the first transistor M1. If the first transistor M1 is an N-type transistor, the first capacitor Cst1 is connected between the gate and the source of the first transistor M1, but not connected to the first power supply signal VDD.

[0116] The following section, in conjunction with the driver timing diagram, discusses... Figure 11 The driving method of the pixel driving circuit shown will be explained. Figure 12 This is a schematic diagram illustrating the driving timing of another pixel driving circuit provided in an embodiment of the present invention. Figure 12 In the process, the level changes of each control signal are related to Figure 11 The pixel driving circuit shown is matched, and the high level of the second scan signal S2 is an effective level. In one embodiment of the present invention, optionally, the driving method of the pixel driving circuit includes: a first compensation stage T1, a second reset stage T2, a data writing stage T3, a second compensation stage T4, a second reset stage T6, and a first light emission stage T5.

[0117] In the first compensation stage T1, the first scan signal S1 is low, while the second scan signal S2, the third scan signal S3, the fifth scan signal S5, and the light emission control signal EM are all high. The third scan signal S3 controls the third transistor M3 to turn off, the fifth scan signal S5 controls the fourth transistor M4 to turn off, and the light emission control signal EM controls the fifth transistor M5 and the sixth transistor M6 to turn off. The first scan signal S1 controls the seventh transistor M7 to turn on, and the second scan signal S2 controls the second transistor M2 to turn on. The first reference voltage Vref1 passes sequentially through the seventh transistor M7, the source S and drain D of the first transistor M1, the second transistor M2, and the gate G of the first transistor M1 to reset the first transistor M1 and pre-compensate the threshold voltage. Simultaneously, the first scan signal S1 controls the eighth transistor M8 to turn on, writing the third reference voltage Vref3 into the anode of the light-emitting device D1 to reset the anode of the light-emitting device D1.

[0118] In the second reset phase T2, only the levels of the first scan signal S1 and the third scan signal S3 change, and the states of the corresponding transistors change accordingly. The states of the other transistors remain consistent with those in the first compensation phase T1. Specifically, the first scan signal S1 switches from low to high, so the seventh transistor M7 switches from the on state to the off state, and the first reference voltage Vref1 is no longer written to this pixel driving circuit. The third scan signal S3 switches from high to low, so the third transistor M3 switches from the off state to the on state, and the second reference voltage Vref2 is written to the gate G of the first transistor M1 through the third transistor M3 and the second transistor M2 to reset the gate G of the first transistor M1.

[0119] During the data writing phase T3, only the levels of the third scan signal S3 and the fifth scan signal S5 change, corresponding to changes in the state of the transistors. The states of other transistors remain consistent with the first reset phase T2. Specifically, the third scan signal S3 switches from low to high, thus the third transistor M3 switches from the on state to the off state, and the third reference voltage Vref3 is no longer written to the pixel driving circuit. The fifth scan signal S5 switches from high to low, thus the fourth transistor M4 switches from the off state to the on state. The data voltage Vdata is written to the control terminal of the first transistor M1 via the fourth transistor M4, the source S and drain D of the first transistor M1, and the second transistor M2 to perform data writing. At the end of the data writing phase T3, the voltage at the control terminal of the first transistor M1 is Vdata + Vth + Error, achieving threshold voltage compensation for the first transistor M1. Simultaneously, the second capacitor Cst2 can store the voltage at the source S of the first transistor M1, that is, the source S of the first transistor M1 remains at the data voltage Vdata.

[0120] In the second compensation stage T4, only the level of the fifth scan signal S5 changes, correspondingly changing the state of the fourth transistor M4. The states of the other transistors remain consistent with those in the data writing stage T3. Specifically, the fifth scan signal S5 switches from high to low, thus the fourth transistor M4 switches from the on state to the off state, and the data voltage Vdata is no longer written to the pixel driving circuit. However, due to the storage effect of the second capacitor Cst2, the voltage at the source S of the first transistor M1 remains at the data voltage Vdata. At the same time, the second transistor M2 remains on, allowing the data voltage Vdata to continue charging the gate G of the first transistor M1 and performing threshold voltage compensation until the voltage at the control terminal of the first transistor M1 is Vdata + Vth, and the error is eliminated.

[0121] In the second reset phase T6, only the levels of the first scan signal S1 and the second scan signal S2 change, and the corresponding transistor states change accordingly. The states of other transistors remain consistent with the second compensation phase T4. Specifically, the second scan signal S2 switches from high to low, thus the second transistor M2 switches from the on state to the off state, and the connection between the drain D and gate G of the first transistor M1 is broken. The first scan signal S1 switches from high to low, and the seventh transistor M7 switches from the off state to the on state, transmitting the second reference voltage Vref2 to the source S and drain D of the first transistor M1 to reset the source S and drain D of the first transistor M1. At the same time, the eighth transistor M8 switches from the off state to the on state, writing the third reference voltage Vref3 into the anode of the light-emitting device D1 to reset the anode of the light-emitting device D1.

[0122] In the first light-emitting stage T5, the levels of the first scan signal S1 and the light-emitting control signal EM change, and the states of the corresponding transistors change accordingly. The states of the other transistors remain consistent with those in the second reset stage T6. Specifically, the first scan signal S1 switches from low to high, so the seventh transistor M7 and the eighth transistor M8 switch from the on state to the off state, and the first reference voltage Vref1 and the third reference voltage Vref3 are no longer written to the pixel driving circuit. The light-emitting control signal EM switches from high to low, so the fifth transistor M5 and the sixth transistor M6 switch from the off state to the on state. The first power supply signal VDD is written to the source S of the first transistor M1 through the fifth transistor M5, and the drain D of the first transistor M1 is connected to the light-emitting device D1. The first transistor M1 can generate a driving current according to the voltage of its gate G. This driving current flows into the light-emitting device D1, thereby driving the light-emitting device D1 to emit light.

[0123] Optionally, the second reference voltage Vref2 and the third reference voltage Vref3 are relatively low, for example, set between -3V and 0V, to ensure that the first transistor M1 and the light-emitting device D1 are reset. The first reference voltage Vref1 is relatively high to ensure that the first transistor M1 can be turned on during the first compensation phase T1. In other embodiments, the values ​​of the first reference voltage Vref1, the second reference voltage Vref2, and the third reference voltage Vref3 can be adjusted as needed, and this invention is not limited thereto.

[0124] The first compensation stage T1, the second reset stage T2, the data writing stage T3, the second compensation stage T4, the second reset stage T6, and the first light emission stage T5 described above are all driving processes of the pixel driving circuit during the write frame. A write frame refers to a frame in which data voltage is written.

[0125] For display devices with switchable refresh rates, the pixel driving circuit's driving method includes at least two refresh rates: high-frequency refresh and low-frequency refresh. For example, this pixel driving circuit can achieve a frequency adjustable from 1-120Hz. It uses 1Hz driving when displaying static images, 120Hz driving when displaying game or video images, and other frequencies as needed when displaying other images. The pixel driving circuit's driving process includes write frames and hold frames. Write frames refer to the driving process of the pixel driving circuit described in the foregoing embodiments, while hold frames are frames where no data voltage is written; they are only used to maintain the working state of the previous frame. In this embodiment, high-frequency refresh consists of write frames, meaning each driving frame is a write frame, and data needs to be written in each frame; for example, the refresh rate is 120Hz. Low-frequency refresh consists of write frames and hold frames, and the more hold frames there are, the lower the driving frequency of the display device; for example, refresh rates other than 120Hz, such as 1Hz. Thus, this embodiment achieves an adjustable refresh rate.

[0126] Figure 13 This is a schematic diagram illustrating the driving timing of another pixel driving circuit provided in an embodiment of the present invention. See also... Figure 13 This driving timing is the driving timing for hold frames. Combined with... Figure 11 and Figure 13 The frame-keeping driving process includes: the third reset phase T7 and the second emission phase T8.

[0127] In the third reset phase T7, the first compensation module 410 and the second initialization module 520 are turned on, transmitting the first reference voltage Vref1 to the first terminal of the drive module 100 and the third reference voltage Vref3 to the light-emitting device D1. The working principle of the third reset phase T7 is similar to that of the second reset phase T6, and will not be described again.

[0128] In the second light-emitting stage T8, the first light-emitting control module 210 and the second light-emitting control module 220 are turned on, and the driving module 100 generates a driving current in response to the voltage at its control terminal. The working principle of the second light-emitting stage T8 is similar to that of the first light-emitting stage T5, and will not be described again.

[0129] Therefore, unlike the write frame, the hold frame does not require the writing process of the data voltage Vdata. Thus, the data writing and threshold voltage compensation processes of the drive module 100 are unnecessary. During the drive process, the lower the refresh rate, the lower the execution frequency of the write frame, which is more beneficial for reducing display power consumption. In this embodiment of the invention, a third reset stage T7 is also performed in the hold frame to reset the source-drain voltage of the first transistor, ensuring consistent transient characteristics of the first transistor in each hold frame and further improving the problem of frequency switching flicker.

[0130] Based on the above embodiments, the duration of the write frame and the hold frame can be the same or different, and can be set as needed in practical applications. Figure 14 This is a schematic diagram illustrating the driving timing of another pixel driving circuit provided in an embodiment of the present invention. See also... Figure 14 In one embodiment of the present invention, optionally, the duration of the write frame and the hold frame are the same. Figure 14 It can be seen that the driving frequencies of the second scan signal S2, the third scan signal S3, and the fifth scan signal S5 are relatively low, consistent with the driving frequency of the write frame; the driving frequencies of the light emission control signal EM and the first scan signal S1 are relatively high, requiring driving in both the write frame and the hold frame. For example, the highest refresh rate of the display device is 120Hz, and the driving frequencies of both the light emission control signal EM and the first scan signal S1 are 120Hz.

[0131] Figure 15 This is a schematic diagram illustrating the driving timing of another pixel driving circuit provided in an embodiment of the present invention. See also... Figure 15 In one embodiment of the present invention, optionally, the duration of writing the frame is an integer multiple of the duration of the holding frame. For example, the highest refresh rate of the display device is 120Hz, and the driving frequencies of the light emission control signal EM and the first scan signal S1 are both 240Hz or 480Hz, etc.

[0132] It should be noted that in the above embodiments, the holding frame includes a third reset stage T7 and a second light-emitting stage T8 to reset the source-drain voltage of the first transistor, making the transient characteristics of the first transistor consistent in each holding frame, and further improving the problem of frequency switching flicker. In other embodiments, the holding frame can also be set to always remain on, which is not limited by this invention.

[0133] This invention also provides a display device, which can be a mobile phone, computer, tablet computer, wearable device, etc. The display device includes the pixel driving circuit provided in any embodiment of this invention, and its technical principle and effects are similar, so they will not be described again.

[0134] This invention also provides a driving method for a pixel driving circuit, applicable to the pixel driving circuit provided in any embodiment of this invention. (In conjunction with...) Figures 1-6 The driving method includes writing frames, and the driving process for writing frames includes:

[0135] In the first compensation stage T1, the first compensation module 410 and the second compensation module 420 are turned on, and the first reference voltage Vref1 is transmitted sequentially to the first terminal, the second terminal and the control terminal of the drive module 100 to reset the drive module 100 and pre-compensate the threshold voltage.

[0136] In the first reset phase T2, the first initialization module 510 and the second compensation module 420 are turned on to transmit the second reference voltage Vref2 to the control terminal of the drive module 100.

[0137] During the data writing stage T3, the control data writing module 300 and the second compensation module 420 are turned on, and the data voltage Vdata is written sequentially to the first terminal, the second terminal and the control terminal of the drive module 100.

[0138] In the second compensation stage T4, the second compensation module 420 is turned on so that the data voltage Vdata stored at the first terminal of the drive module 100 continues to charge its control terminal and compensate for the threshold voltage.

[0139] In the first light-emitting stage T5, the first light-emitting control module 210 and the second light-emitting control module 220 are turned on, and the driving module 100 generates a driving current in response to the voltage at its control terminal.

[0140] In various embodiments of the pixel driving circuit, different driving methods are specifically described for the pixel driving circuit provided in the embodiments of the present invention. These driving methods can all be considered as driving methods for the pixel driving circuit provided in the embodiments of the present invention, and repeated content will not be described here.

[0141] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0142] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel driving circuit, characterized in that, include: The drive module generates drive current in response to the voltage at its control terminal; A first light-emitting control module and a second light-emitting control module are connected in series with the driving module and the light-emitting device; the first light-emitting control module is used to transmit a first power signal to the driving module, and the second light-emitting control module is used to transmit the driving current to the light-emitting device. A data writing module is electrically connected to the first terminal of the drive module; the data writing module is used to write data voltage to the control terminal of the drive module. A first compensation module is electrically connected to a first terminal of the drive module; the first compensation module is used to transmit a first reference voltage to the first terminal of the drive module. The second compensation module is connected between the control terminal and the second terminal of the drive module; A first initialization module is electrically connected to the second terminal of the drive module; the first initialization module is used to transmit a second reference voltage to the second terminal of the drive module. The first storage module is electrically connected to the control terminal of the drive module; The first storage module is used to store the voltage at the control terminal of the drive module; The second storage module is electrically connected to the first terminal of the drive module; the second storage module is used to store the voltage at the first terminal of the drive module.

2. The pixel driving circuit according to claim 1, characterized in that, Also includes: A second initialization module is electrically connected to the light-emitting device. The second initialization module is used to transmit the third reference voltage to the light-emitting device.

3. The pixel driving circuit according to claim 2, characterized in that, Both the first light-emitting control module and the second light-emitting control module are connected to a light-emitting control signal and are controlled by the light-emitting control signal; The first compensation module is connected to the first scanning signal and is controlled by the first scanning signal; The second compensation module is connected to the second scanning signal and is controlled by the second scanning signal; The first initialization module is connected to and controlled by the third scanning signal; The second initialization module is connected to the fourth scan signal and is controlled by the fourth scan signal; The data writing module is connected to and controlled by the fifth scan signal.

4. The pixel driving circuit according to claim 3, characterized in that, The pulse width of at least one of the first scanning signal, the second scanning signal, the third scanning signal, the fourth scanning signal, and the light emission control signal is adjustable.

5. The pixel driving circuit according to claim 3, characterized in that, The first scan signal is multiplexed into the fourth scan signal.

6. The pixel driving circuit according to claim 3, characterized in that, The driving module includes a first transistor, the gate of the first transistor serves as the control terminal of the driving module, the first electrode of the first transistor serves as the first terminal of the driving module, and the second electrode of the first transistor serves as the second terminal of the driving module. The second compensation module includes a second transistor, the gate of the second transistor is connected to the second scan signal, the first terminal of the second transistor is electrically connected to the second terminal of the first transistor, and the second terminal of the second transistor is electrically connected to the gate of the first transistor. The first initialization module includes a third transistor, the gate of which is connected to the third scan signal, the first terminal of which is connected to the second reference voltage, and the second terminal of which is electrically connected to the first terminal of the second transistor. The data writing module includes a fourth transistor, the gate of which is connected to the fifth scan signal, the first terminal of which is connected to the data voltage, and the second terminal of which is electrically connected to the first terminal of the first transistor. The first light-emitting control module includes a fifth transistor, the gate of which is connected to the light-emitting control signal, the first terminal of which is connected to the first power supply signal, and the second terminal of which is electrically connected to the first terminal of the first transistor. The second light-emitting control module includes a sixth transistor, the gate of which is connected to the light-emitting control signal, the first terminal of which is electrically connected to the second terminal of the first transistor, and the second terminal of which is electrically connected to the light-emitting device. The first compensation module includes a seventh transistor, the gate of which is connected to the first scan signal, the first terminal of which is connected to the first reference voltage, and the second terminal of which is electrically connected to the first terminal of the first transistor. The second initialization module includes an eighth transistor, the gate of which is connected to the fourth scan signal, the first terminal of which is connected to the third reference voltage, and the second terminal of which is electrically connected to the light-emitting device.

7. The pixel driving circuit according to claim 6, characterized in that, The first transistor, the third transistor, and the eighth transistor are all P-type transistors, and the second transistor is an N-type transistor.

8. The pixel driving circuit according to claim 1, characterized in that, The first storage module includes a first capacitor, a first terminal of which is connected to the first power signal, and a second terminal of which is electrically connected to the control terminal of the drive module. The second storage module includes a second capacitor, the first end of which is connected to the first power signal, and the second end of which is electrically connected to the first end of the drive module.

9. A display device, characterized in that, include: The pixel driving circuit as described in any one of claims 1-8.

10. A driving method for a pixel driving circuit, characterized in that, For driving the pixel driving circuit as described in any one of claims 1-8; the driving method includes writing a frame, the driving process of writing the frame includes: In the first compensation stage, the first compensation module and the second compensation module are turned on, and the first reference voltage is transmitted sequentially to the first terminal, the second terminal and the control terminal of the driving module to reset the driving module and pre-compensate the threshold voltage. In the first reset phase, the first initialization module and the second compensation module are turned on to transmit the second reference voltage to the control terminal of the drive module. During the data writing phase, the data writing module and the second compensation module are turned on, and the data voltage is written sequentially to the first terminal, the second terminal and the control terminal of the driving module, while the driving module is compensated for the threshold voltage. In the second compensation phase, the second compensation module is turned on so that the data voltage stored at the first end of the drive module continues to charge its control end and compensate for the threshold voltage. In the first light-emitting stage, the first light-emitting control module and the second light-emitting control module are turned on, and the driving module generates a driving current in response to the voltage at its control terminal.

11. The driving method for the pixel driving circuit according to claim 10, characterized in that, The pixel driving circuit further includes a second initialization module, which is electrically connected to the light-emitting device; the driving method further includes: During the first compensation phase, the second initialization module is turned on to transmit the third reference voltage to the light-emitting device in order to reset the light-emitting device.

12. The driving method for the pixel driving circuit according to claim 11, characterized in that, The write frame further includes a second reset phase, which is located after the second compensation phase and before the first light emission phase. In the second reset phase, the first compensation module and the second initialization module are turned on to transmit the first reference voltage to the first terminal of the driving module and the third reference voltage to the light emission device.

13. The driving method for the pixel driving circuit according to claim 12, characterized in that, The times of the first compensation phase, the first reset phase, the second compensation phase, and the second reset phase are adjustable.

14. The driving method for the pixel driving circuit according to claim 10, characterized in that, It also includes a holding frame; the driving process of the holding frame includes: In the third reset phase, the first compensation module and the second initialization module are turned on, and the first reference voltage is transmitted to the first terminal of the driving module, and the third reference voltage is transmitted to the light-emitting device. In the second light-emitting stage, the first light-emitting control module and the second light-emitting control module are turned on, and the driving module generates a driving current in response to the voltage at its control terminal.

15. The driving method for the pixel driving circuit according to claim 14, characterized in that, The timing of the third reset phase and the second light emission phase is adjustable.

16. The driving method for the pixel driving circuit according to claim 14, characterized in that, It includes high-frequency refresh and low-frequency refresh; the high-frequency refresh is composed of the write frame, and the low-frequency refresh is composed of the write frame and the hold frame.

17. The driving method for the pixel driving circuit according to claim 16, characterized in that, When performing the low-frequency refresh, the duration of the write frame and the hold frame are the same, or the duration of the write frame is an integer multiple of the duration of the hold frame.

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