Display panel

Abstract

A display panel includes respective pixel driving circuits including a driving transistor, a first reset transistor, and a second reset transistor. First electrodes of adjacent first reset transistors in adjacent pixel driving circuits along a first direction are connected to each other by a first connection line. First electrodes of adjacent second reset transistors in the adjacent pixel driving circuits along the first direction are connected to each other by a second connection line. The first connection line and the second connection line are located in a semiconductor material layer. First electrodes of six adjacent first reset transistors in six adjacent pixel driving circuits along the first direction are connected to three adjacent first node reset signal lines respectively by three first vias. The first connection line and the second connection line extend along the first direction. The three adjacent first node reset signal lines extend along a second direction.

Description

[0001] Cross-references to related applications

[0002] This application is a continuation to U.S. Application No. 17 / 764,479, filed June 25, 2021, which is a national phase application pursuant to 35 U.SC § 371 of International Application No. PCT / CN2021 / 102249, also filed June 25, 2021. Each of the foregoing applications is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] This invention relates to display technology, and more particularly to a display panel. Background Technology

[0004] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illuminance. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the row in which the pixel unit is selected is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. This drives the OLED device to emit light of a corresponding brightness. Summary of the Invention

[0005] In one aspect, this disclosure provides a display panel, comprising: a plurality of pixel driving circuits configured to drive a plurality of light-emitting elements to emit light respectively; wherein each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a first reset transistor configured to reset a first node including the gate of the driving transistor, and a second reset transistor configured to reset the anode of each of the plurality of light-emitting elements; first electrodes of adjacent first reset transistors in adjacent pixel driving circuits along a first direction are connected to each other via a first connection line; first electrodes of adjacent second reset transistors in adjacent pixel driving circuits along the first direction are connected to each other via a second connection line; the first connection line and the second connection line are located in a semiconductor material layer; first electrodes of six adjacent first reset transistors in six adjacent pixel driving circuits along the first direction are respectively connected to three adjacent first node reset signal lines via three first vias; the first connection line and the second connection line extend along the first direction; and the three adjacent first node reset signal lines extend along a second direction, the first direction and the second direction intersecting each other.

[0006] Optionally, the first electrodes of the six adjacent second reset transistors in the six adjacent pixel driving circuits along the first direction are connected to the three adjacent anode reset signal lines through three second vias.

[0007] Optionally, the first node reset signal line is connected to the first connection line through a first via; and the anode reset signal line is connected to the second connection line through a second via.

[0008] Optionally, the display panel further includes a plurality of first high-voltage signal lines extending along the first direction and a plurality of second high-voltage signal lines extending along the second direction; and the plurality of first high-voltage signal lines and the plurality of second high-voltage signal lines are interconnected with each other through vias to form an interconnected network.

[0009] Optionally, each pixel driving circuit further includes a storage capacitor; the second capacitor electrodes of the storage capacitors of the pixel driving circuits along the first direction are connected to each other to form an integral structure; and the second capacitor electrodes of the storage capacitors are connected to a corresponding first high voltage signal line among the plurality of first high voltage signal lines or a corresponding second high voltage signal line among the plurality of second high voltage signal lines.

[0010] Optionally, the first node further includes a node connection line that connects the gate of the driving transistor in each pixel driving circuit to the first electrode of the compensation transistor; each of the plurality of first high-voltage signal lines includes a body and a protrusion protruding away from the body along the second direction; and the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the first node on the substrate.

[0011] Optionally, the orthographic projection of the combination of a corresponding first high-voltage signal line among the plurality of first high-voltage signal lines and a corresponding second high-voltage signal line among the plurality of second high-voltage signal lines on the substrate covers the orthographic projection of the node connection line on the substrate.

[0012] Optionally, the protrusion includes a connecting portion and a terminal portion; the terminal portion is connected to the body at least through the connecting portion; and the width of the terminal portion along the first direction is greater than the width of the connecting portion along the first direction.

[0013] Optionally, the display panel further includes a plurality of first low-voltage signal lines extending along the first direction and a plurality of second low-voltage signal lines extending along the second direction; wherein the plurality of first low-voltage signal lines and the plurality of second low-voltage signal lines are interconnected through vias.

[0014] Optionally, each pixel driving circuit further includes a storage capacitor and a shielding block; the shielding block and the second capacitor electrode of the storage capacitor are located on the same layer; and the shielding block includes a main body extending along the first direction, a first extension extending along the second direction, and a second extension extending along the second direction.

[0015] Optionally, the orthographic projection of the first extension onto the substrate covers the orthographic projection of a portion of the semiconductor material layer located between the two channels of the compensation transistor onto the substrate.

[0016] Optionally, the first node further includes a node connection line that connects the gate of the driving transistor in each pixel driving circuit to the first electrode of the compensation transistor; and the second extension at least partially overlaps the node connection line along the second direction.

[0017] Optionally, the first node further includes a node connection line that connects the gate of the driving transistor in each pixel driving circuit to the first electrode of the compensation transistor; and the second extension spacees the node connection line from each data line configured to provide data signals to each pixel driving circuit.

[0018] In another aspect, this disclosure provides a display panel including a plurality of sub-pixels, each sub-pixel including a corresponding light-emitting element and a corresponding pixel driving circuit; wherein the display panel includes: a plurality of light-emitting elements; and an interconnected first voltage supply network configured to provide a first voltage signal to the cathodes of the plurality of light-emitting elements; wherein the interconnected first voltage supply network includes signal lines in a display area of ​​the display panel, the display area being at least partially surrounded by a peripheral area; the signal lines include a plurality of first signal lines located in a first signal line layer and a plurality of second signal lines located in a second signal line layer; the display panel further includes a planarization layer located between the first signal line layer and the second signal line layer; and the plurality of first signal lines are electrically connected to the plurality of second signal lines.

[0019] Optionally, the interconnected first voltage supply network includes: a plurality of first-first voltage signal lines respectively along a first direction; and a plurality of second-first voltage signal lines respectively along a second direction; wherein the plurality of first-first voltage signal lines intersect with the plurality of second-first voltage signal lines respectively.

[0020] Optionally, the interconnected first voltage supply network includes a first sub-network formed by the plurality of first-first voltage signal lines and a second sub-network formed by the plurality of second-first voltage signal lines.

[0021] Optionally, a corresponding one of the plurality of first-first voltage signal lines is connected to at least a plurality of the plurality of second-first voltage signal lines; and a corresponding one of the plurality of second-first voltage signal lines is connected to at least a plurality of the plurality of first-first voltage signal lines.

[0022] Optionally, the plurality of first-first voltage signal lines and the plurality of second-first voltage signal lines are interconnected via first vias extending through the planarization layer, at least some of the first vias being in the display area; a corresponding one of the plurality of first-first voltage signal lines is connected to at least a plurality of the plurality of second-first voltage signal lines via a plurality of first vias extending through the planarization layer; and a corresponding one of the plurality of second-first voltage signal lines is connected to at least a plurality of the plurality of first-first voltage signal lines via a plurality of first vias extending through the planarization layer.

[0023] Optionally, the display panel further includes an array gate circuit in a peripheral region of the display panel; wherein the interconnected first voltage supply network includes a first peripheral first voltage line in the peripheral region on a first side of the display panel; and the orthographic projection of the first peripheral first voltage line on the substrate at least partially overlaps with the orthographic projection of the array gate circuit on the substrate.

[0024] Optionally, the display panel further includes an anode metal layer located on the side of the first peripheral first voltage line away from the array gate circuit; and a cathode layer located on the side of the anode metal layer away from the first peripheral first voltage line; wherein the cathode layer is connected to the anode metal layer through one or more first peripheral vias in the peripheral region and extending through a third planarization layer, and the anode metal layer is connected to the first peripheral first voltage line through one or more second peripheral vias in the peripheral region and extending through a second planarization layer, thereby providing the first voltage signal to the cathodes of the plurality of light-emitting elements; the one or more first peripheral vias connecting the cathode layer and the anode metal layer, and the one or more second peripheral vias connecting the anode metal layer and the interconnected first voltage supply network, are confined in the peripheral region and not in the display region; and the first peripheral first voltage line and the anode metal layer connected to the first peripheral first voltage line each partially surround the display region.

[0025] Optionally, the display panel further includes an interconnected reset signal supply network configured to provide reset signals to a plurality of pixel driving circuits; wherein the interconnected reset signal supply network includes signal lines in the display area of ​​the display panel.

[0026] Optionally, the interconnected reset signal supply network includes: a plurality of first reset signal lines respectively along a first direction; and a plurality of second reset signal lines respectively along a second direction; wherein the plurality of first reset signal lines intersect with the plurality of second reset signal lines respectively.

[0027] Optionally, a corresponding one of the plurality of first reset signal lines is connected to at least one of the plurality of second reset signal lines; and a corresponding one of the plurality of second reset signal lines is connected to at least one of the plurality of first reset signal lines.

[0028] Optionally, the minimum distance between a corresponding second reset signal line among the plurality of second reset signal lines and the corresponding second-first voltage signal line among the plurality of second-first voltage signal lines that is closest to the corresponding second reset signal line is less than the minimum distance between a corresponding second reset signal line and the corresponding data line among the plurality of data lines that is closest to the corresponding second reset signal line.

[0029] Optionally, a total of three data lines and a total of one second-first voltage signal line are located between the two nearest second reset signal lines among the plurality of second reset signal lines.

[0030] Optionally, the display panel includes a substrate; a semiconductor material layer on the substrate; a planarization layer located on the side of the semiconductor material layer away from the substrate; and a second signal line layer located on the side of the planarization layer away from the semiconductor material layer. The display panel further includes an interconnected reset signal supply network configured to provide reset signals to a plurality of pixel driving circuits. The interconnected reset signal supply network includes a plurality of first reset signal lines along a first direction and a plurality of second reset signal lines along a second direction. The semiconductor material layer includes the plurality of first reset signal lines, and the second signal line layer includes the plurality of second reset signal lines.

[0031] Optionally, the plurality of first reset signal lines and the plurality of second reset signal lines are interconnected via second vias extending through at least the planarization layer; wherein the display panel further includes: a gate insulating layer located on the side of the semiconductor material layer away from the substrate; an insulating layer located on the side of the gate insulating layer away from the semiconductor material layer; and an interlayer dielectric layer located on the side of the insulating layer away from the gate insulating layer; wherein the planarization layer is located on the side of the interlayer dielectric layer away from the insulating layer; and the plurality of first reset signal lines and the plurality of second reset signal lines are interconnected via second vias, each second via extending through the planarization layer, the interlayer dielectric layer, the insulating layer, and the gate insulating layer.

[0032] Optionally, a corresponding one of the plurality of first reset signal lines is connected to at least one of the plurality of second reset signal lines through a plurality of second vias extending through at least the planarization layer; and a corresponding one of the plurality of second reset signal lines is connected to at least one of the plurality of first reset signal lines through a plurality of second vias extending through at least the planarization layer.

[0033] Optionally, the plurality of first reset signal lines comprise semiconductor material; the plurality of second reset signal lines comprise metal material; and the plurality of first reset signal lines and at least the active layer of the plurality of thin-film transistors are located in the semiconductor material layer and comprise the same semiconductor material.

[0034] Optionally, the display panel further includes an interconnected second voltage supply network configured to provide second voltage signals to a plurality of pixel driving circuits; wherein the interconnected second voltage supply network includes: a plurality of first-second voltage signal lines respectively along a first direction; and a plurality of second-second voltage signal lines respectively along a second direction; wherein the plurality of first-second voltage signal lines intersect with the plurality of second-second voltage signal lines respectively.

[0035] Optionally, a corresponding one of the plurality of first-second voltage signal lines is connected to at least a plurality of the plurality of second-second voltage signal lines; and a corresponding one of the plurality of second-second voltage signal lines is connected to at least a plurality of the plurality of first-second voltage signal lines.

[0036] Optionally, the display panel includes: a substrate; a first signal line layer on the substrate; a planarization layer located on the side of the first signal line layer away from the substrate; and a second signal line layer located on the side of the planarization layer away from the first signal line layer; wherein the interconnected second voltage supply network includes a plurality of first-second voltage signal lines and a plurality of second-second voltage signal lines respectively along a first direction; wherein the first signal line layer includes the plurality of first-second voltage signal lines, and the second signal line layer includes the plurality of second-second voltage signal lines.

[0037] Optionally, the plurality of first-second voltage signal lines and the plurality of second-second voltage signal lines are interconnected via third vias extending through the planarization layer; a corresponding one of the plurality of first-second voltage signal lines is connected to at least a plurality of the plurality of second-second voltage signal lines via a plurality of third vias extending through the planarization layer; and a corresponding one of the plurality of second-second voltage signal lines is connected to at least a plurality of the plurality of first-second voltage signal lines via a plurality of third vias extending through the planarization layer.

[0038] Optionally, a corresponding one of the plurality of first-second voltage signal lines includes: a body extending along a first direction; a first protrusion protruding away from the body along a second direction; and a second protrusion protruding away from the first protrusion along the second direction; wherein the second protrusion is connected to the body via the first protrusion; the first protrusion is a portion of a corresponding one of the plurality of first-second voltage signal lines, in which the corresponding one of the plurality of first-second voltage signal lines is connected to a second capacitor electrode; and the second protrusion is a portion of a corresponding one of the plurality of first-second voltage signal lines, in which the corresponding one of the plurality of first-second voltage signal lines is connected to the source of a fourth transistor of a corresponding pixel driving circuit, the drain of the fourth transistor being connected to the source of a driving transistor.

[0039] Optionally, the display panel further includes at least a plurality of second-second voltage signal lines in the display area; and a peripheral second voltage signal line in the peripheral area on the second side of the display panel; wherein the interconnected first voltage supply network includes: at least a plurality of first-first voltage signal lines and a plurality of second-first voltage signal lines in the display area; and a second peripheral first voltage signal line and a third peripheral first voltage signal line in the peripheral area on the second side of the display panel; wherein one or more of the plurality of second-second voltage signal lines are connected to the peripheral second voltage signal line; one or more of the plurality of second-first voltage signal lines are connected to the second peripheral first voltage signal line; the second peripheral first voltage signal line and the third peripheral first voltage signal line are connected to each other by a plurality of bridges; the plurality of first-first voltage signal lines, the peripheral second voltage signal lines and the plurality of bridges are in a first signal line layer; the plurality of second-second voltage signal lines and the second peripheral first voltage signal line are in a second signal line layer; and the third peripheral first voltage signal line is included in a first sub-layer in the first signal line layer and a second sub-layer in the second signal line layer.

[0040] Optionally, the display panel further includes a plurality of gate lines; wherein, a corresponding gate line among the plurality of gate lines includes a plurality of metal blocks spaced apart from each other in a first conductive layer and a metal line along a first direction in the first signal line layer, and the signal line along the first direction is respectively connected to the plurality of metal blocks.

[0041] Optionally, the display panel further includes a plurality of first reset control signal lines and a plurality of second reset control signal lines; the corresponding first reset control signal lines and the corresponding second reset control signal lines are respectively configured as the gate of a reset driving transistor and the anode of a corresponding light-emitting element; the corresponding first reset control signal line includes a plurality of first metal blocks spaced apart from each other in a first conductive layer, and a first metal line in the first signal line layer along a first direction, the first metal line along the first direction being respectively connected to the plurality of first metal blocks; and the corresponding second reset control signal line includes a plurality of second metal blocks spaced apart from each other in the first conductive layer, and a second metal line in the first signal line layer along the first direction, the second metal line along the first direction being respectively connected to the plurality of second metal blocks.

[0042] Optionally, each of the plurality of first-first voltage signal lines includes a first linear portion, a second linear portion, and a connecting portion connecting the first linear portion and the second linear portion; the virtual extension portion of the first linear portion intersects with the plurality of first metal blocks of the corresponding first reset control signal line; and the orthographic projection of the second linear portion on the substrate is spaced apart from the orthographic projection of the plurality of first metal blocks on the substrate.

[0043] Optionally, the display panel further includes a second capacitor electrode of a storage capacitor in a second conductive layer; the second capacitor electrode includes an extension extending away from the electrode body of the second capacitor electrode; the orthographic projection of the extension on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the substrate; and a portion of the extension is located between a first node of the corresponding pixel driving circuit and a corresponding data line, configured to prevent interference of signals to the first node via the corresponding data line, the first node being configured to have the same voltage level as the gate of the driving transistor. Attached Figure Description

[0044] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0045] Figure 1 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure.

[0046] Figure 2 This is a plan view of a display panel according to some embodiments of the present disclosure.

[0047] Figure 3 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0048] Figure 4A This is a diagram illustrating the structure of a three-pixel driving circuit for driving three light-emitting elements of a display panel to emit light, according to some embodiments of the present disclosure.

[0049] Figure 4B It is shown Figure 4A A diagram showing the structure of the semiconductor material layer in the display panel.

[0050] Figure 4C It is shown Figure 4A A diagram showing the structure of the first conductive layer in the display panel.

[0051] Figure 4D It is shown Figure 4A A diagram showing the structure of the second conductor layer in the display panel.

[0052] Figure 4E It is shown Figure 4A A diagram showing the structure of the first signal line layer in the display panel.

[0053] Figure 4F It is shown Figure 4A The diagram shows the structure of the second signal line layer in the display panel.

[0054] Figure 4G This is a diagram illustrating the structure of a corresponding one of a plurality of first high-voltage signal lines according to some embodiments of the present disclosure.

[0055] Figure 4H This is a diagram illustrating the layout of the anode of a light-emitting element relative to the pixel driving circuitry of a display panel in some embodiments of the present disclosure.

[0056] Figure 4I This is a diagram illustrating the structure of the anode, the first signal line layer, and the second signal line layer in a display panel according to some embodiments of the present disclosure.

[0057] Figure 4J This is a diagram showing the relative position of a corresponding one of a plurality of first low voltage signal lines and a plurality of first metal blocks of a corresponding first reset control signal line in some embodiments of the present disclosure.

[0058] Figure 5A It is along Figure 4A A cross-sectional view of line A-A' in the diagram.

[0059] Figure 5B It is along Figure 4A A cross-sectional view of line B-B' in the diagram.

[0060] Figure 5C It is along Figure 4A A cross-sectional view of the C-C' line in the diagram.

[0061] Figure 5D It is along Figure 4A A cross-sectional view of the D-D' line in the diagram.

[0062] Figure 5E It is along Figure 4A A cross-sectional view of the E-E' line in the diagram.

[0063] Figure 6A This is a diagram illustrating the structure of interconnected low-voltage supply networks, interconnected reset signal supply networks, and interconnected high-voltage supply networks in a display panel according to some embodiments of the present disclosure.

[0064] Figure 6B This is a diagram illustrating the structure of an interconnected low-voltage supply network in a display panel according to some embodiments of the present disclosure.

[0065] Figure 6C This is a diagram illustrating the structure of an interconnected reset signal supply network in a display panel according to some embodiments of the present disclosure.

[0066] Figure 6D This is a diagram illustrating the structure of an interconnected high-voltage supply network in a display panel according to some embodiments of the present disclosure.

[0067] Figure 7A It is shown Figure 1 A schematic diagram of the structure in the first region ZR1.

[0068] Figure 7B It is shown Figure 7A A diagram showing the structure of the first signal line layer in the first region ZR1.

[0069] Figure 7C It is shown Figure 7A A diagram showing the structure of the second signal line layer in the first region ZR1.

[0070] Figure 7D It is shown Figure 7A A diagram showing the structure of the second planarization layer in the first region ZR1.

[0071] Figure 7E It is shown Figure 7A A diagram showing the structure of the anode layer in the first region ZR1.

[0072] Figure 7F It is shown Figure 7A A diagram showing the structure of the third planarization layer in the first region ZR1.

[0073] Figure 7G It is shown Figure 7AA diagram showing the structure of the cathode layer in the first region ZR1.

[0074] Figure 8 It is along Figure 7A A cross-sectional view of line F-F' in the diagram.

[0075] Figure 9A The IR drop in a display panel is shown in some embodiments according to this disclosure.

[0076] Figure 9B This illustrates the IR drop in a relevant display panel in the absence of an interconnected low-voltage supply network.

[0077] Figure 10A It is shown Figure 1 A schematic diagram of the structure in the second enlarged region ZR2.

[0078] Figure 10B It is shown Figure 10A A schematic diagram of the structure of the low-voltage signal line in the diagram.

[0079] Figure 10C It is shown Figure 10A A schematic diagram of the structure of the high-voltage signal line in the diagram.

[0080] Figure 10D It is shown Figure 10A A schematic diagram of the structure of the reset signal line.

[0081] Figure 11A This is a diagram illustrating the structure of a first sub-network of an interconnected low-voltage supply network according to some embodiments of the present disclosure.

[0082] Figure 11B This is a diagram illustrating the structure of a second subnetwork of an interconnected low-voltage supply network according to some embodiments of the present disclosure.

[0083] Figure 11C This is a diagram illustrating the structure of a low-voltage supply network including the interconnection of a first subnetwork and a second subnetwork according to some embodiments of the present disclosure.

[0084] Figure 12A This is a diagram illustrating the structure of a plurality of first low-voltage signal lines of an interconnected low-voltage supply network according to some embodiments of the present disclosure.

[0085] Figure 12B This is a diagram illustrating the structure of a subnetwork of multiple second low-voltage signal lines of an interconnected low-voltage supply network according to some embodiments of the present disclosure.

[0086] Figure 12CThis is a diagram illustrating the structure of an interconnected low-voltage supply network according to some embodiments of the present disclosure, the low-voltage supply network including a subnetwork of a plurality of first low-voltage signal lines and a plurality of second low-voltage signal lines. Detailed Implementation

[0087] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0088] This disclosure provides, in particular, a display panel that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a display panel comprising a plurality of sub-pixels. Each sub-pixel includes a corresponding light-emitting element and a corresponding pixel driving circuit. In some embodiments, the display panel includes a plurality of light-emitting elements and an interconnected first voltage supply network configured to provide a first voltage signal to the cathodes of the plurality of light-emitting elements. Optionally, the interconnected first voltage supply network includes signal lines in a display area of ​​the display panel. The display area is at least partially surrounded by a peripheral area. The signal lines include a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer. The display panel also includes a planarization layer located between the first signal line layer and the second signal line layer. The plurality of first signal lines are electrically connected to the plurality of second signal lines. In one example, the first voltage signal lines are low-voltage signal lines, and the second voltage signal lines are high-voltage signal lines.

[0089] As used herein, the term "display area" refers to the area of ​​a display panel that actually displays an image. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel (e.g., the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting display). An inter-subpixel area refers to the area between adjacent subpixel areas, such as the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting display. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas of two adjacent pixels.

[0090] As used herein, the term "peripheral area" refers to the area of ​​a display panel that provides various circuits and wires to transmit signals to the display substrate. To increase the transparency of the display panel, opaque or non-opaque components of the display panel (e.g., batteries, printed circuit boards, metal frames) may be arranged in the peripheral area rather than in the display area.

[0091] Various suitable light-emitting elements can be used in this array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro OLEDs. Optionally, the light-emitting element is a micro OLED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0092] Figure 1 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 1 In some embodiments, the display panel includes interconnected low-voltage supply networks (VSSNs). The interconnected VSSNs are configured to provide low-voltage signals to the cathodes of a plurality of light-emitting elements. The interconnected VSSNs include signal lines in the display area DA of the display panel. The display panel also includes one or more integrated circuits (e.g., IC1, IC2, IC3, and IC4) in the peripheral area PA. The display panel also includes one or more high-voltage signal lines VDD, one or more reset signal lines VIN, and a gate-on-array circuit GOA.

[0093] In some embodiments, the interconnected low-voltage supply network (VSSN) includes a plurality of first low-voltage signal lines Vss1 respectively along a first direction DR1; and a plurality of second low-voltage signal lines Vss2 respectively along a second direction DR2. The first direction DR1 and the second direction DR2 are different from each other. The plurality of first low-voltage signal lines Vss1 intersect with the plurality of second low-voltage signal lines Vss2 respectively.

[0094] Figure 2 This is a plan view of a display panel according to some embodiments of this disclosure. (Refer to...) Figure 2 The display panel includes an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The display panel includes multiple gate lines GL, multiple data lines DL, and multiple high-voltage signal lines Vdd. The light emission of each subpixel is driven by the corresponding pixel driving circuit PDC. In one example, a high-voltage signal is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding high-voltage signal line among the multiple high-voltage signal lines Vdd; a low-voltage signal is input to the cathode of the light-emitting element. The voltage difference between the high-voltage signal (e.g., VDD signal) and the low-voltage signal (e.g., VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0095] In some embodiments, the display panel includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes respective first sub-pixels, respective second sub-pixels, respective third sub-pixels, and respective fourth sub-pixels. Optionally, each pixel of the display panel includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The plurality of sub-pixels in the display panel are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, S3 represents each third sub-pixel, and S4 represents each fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C4 represents each fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents the first sub-pixels of the first color, C2 represents the second sub-pixels of the second color, C3 represents the third sub-pixels of the third color, and C2' represents the fourth sub-pixels of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, each third sub-pixel is a blue sub-pixel, and each fourth sub-pixel is a green sub-pixel.

[0096] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the display panel includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the respective first sub-pixel, each of the respective second sub-pixel, each of the respective third sub-pixel, and each of the respective fourth sub-pixels includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0097] Various suitable pixel driving circuits can be used in this display panel. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, a corresponding one of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in this display panel. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro OLEDs. Optionally, the light-emitting element is a micro OLED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0098] Figure 3This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 3 In some embodiments, each pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding first reset control signal line of a plurality of first reset control signal lines rst1, a source connected to a corresponding reset signal line VintN of the current stage of a plurality of reset signal lines, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line of a plurality of gate lines GL, a source connected to a corresponding data line of a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line and a source connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td. A fourth transistor T4 has its gate connected to a corresponding light-emitting control signal line among a plurality of light-emitting control signal lines em, its source connected to a corresponding voltage supply line among a plurality of high-voltage signal lines Vdd, and its drain connected to the source of the driving transistor Td and the drain of the second transistor T2; a fifth transistor T5 has its gate connected to a corresponding light-emitting control signal line, its source connected to the drain of the driving transistor Td and the drain of the third transistor T3, and its drain connected to the anode of the light-emitting element LE; and a sixth transistor T6 has its gate connected to a corresponding second reset control signal line among a plurality of second reset control signal lines rst2, its source connected to the reset signal line Vint(N+1) in the next adjacent stage of the plurality of reset signal lines, and its drain connected to the drain of the fifth transistor and the anode of the light-emitting element LE. A second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source of the fourth transistor T4.

[0099] refer to Figure 3 In some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor intersects the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line intersects the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 intersects the corresponding gate line of the plurality of gate lines GL twice (alternatively, the corresponding gate line intersects the active layer of the third transistor T3 twice).

[0100] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the source of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2, and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the drain of the third transistor T3, and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0101] Figure 4A This is a diagram illustrating the structure of a three-pixel driving circuit for driving three light-emitting elements of a display panel to emit light, according to some embodiments of the present disclosure. (Refer to...) Figure 4A In some embodiments, the display panel includes a plurality of gate lines GL extending along a first direction DR1, a plurality of data lines DL extending along a second direction DR2, a plurality of first high-voltage signal lines Vdd1 extending along the first direction DR1, a plurality of second high-voltage signal lines Vdd2 extending along the second direction DR2, a plurality of first low-voltage signal lines Vss1 extending along the first direction DR1, a plurality of second low-voltage signal lines Vss2 extending along the second direction DR2, a plurality of first reset signal lines Vint1 extending along the first direction DR1, and a plurality of second reset signal lines Vint2 extending along the second direction DR2. The plurality of first low-voltage signal lines Vss1 intersect with the plurality of second low-voltage signal lines Vss2. The plurality of first reset signal lines Vint1 intersect with the plurality of second reset signal lines Vint2. The plurality of first high-voltage signal lines Vdd1 intersect with the plurality of second high-voltage signal lines Vdd2. Optionally, the display panel further includes a plurality of first reset control signal lines rst1 extending along the first direction DR1; a plurality of second reset control signal lines rst2 extending along the first direction DR1; and a plurality of light emission control signal lines em extending along the first direction DR1. The corresponding positions of the plurality of transistors in each pixel driving circuit are... Figure 4A The PDC described in the document. Each pixel driving circuit PDC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0102] Figure 4B It is shown Figure 4A A diagram showing the structure of the semiconductor material layer in the display panel. Figure 4C It is shown Figure 4A A diagram showing the structure of the first conductive layer in the display panel. Figure 4D It is shown Figure 4AA diagram showing the structure of the second conductor layer in the display panel. Figure 4E It is shown Figure 4A A diagram showing the structure of the first signal line layer in the display panel. Figure 4F It is shown Figure 4A The diagram shows the structure of the second signal line layer in the display panel. Figure 5A It is along Figure 4A A cross-sectional view of line A-A' in the diagram. (Reference) Figures 4A to 4F as well as Figure 5A In some embodiments, the display panel includes a substrate BS, a semiconductor material layer SML on the substrate BS, a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS, a first conductive layer CT1 located on the side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on the side of the first conductive layer away from the gate insulating layer GI, a second conductive layer CT2 located on the side of the insulating layer IN away from the first conductive layer CT1, an interlayer dielectric layer ILD located on the side of the second conductive layer CT2 away from the insulating layer IN, a first signal line layer SL1 located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2, a planarization layer PLN located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD, and a second signal line layer SL2 located on the side of the planarization layer PLN away from the first signal line layer SL1.

[0103] Reference Figure 3 , Figure 4A and Figure 4B In some embodiments, the semiconductor material layer has a unitary structure. Figure 4BIn the diagram, each pixel driving circuit is labeled with a region corresponding to a plurality of transistors, including transistors T1, T2, T3, T4, T5, T6, and a driving transistor Td. Each pixel driving circuit is also labeled with a component indicating each of the transistors. For example, transistor T1 includes an active layer ACT1, a source S1, and a drain D1. Transistor T2 includes an active layer ACT2, a source S2, and a drain D2. Transistor T3 includes an active layer ACT3, a source S3, and a drain D3. Transistor T4 includes an active layer ACT4, a source S4, and a drain D4. Transistor T5 includes an active layer ACT5, a source S5, and a drain D5. Transistor T6 includes an active layer ACT6, a source S6, and a drain D6. Driving transistor Td includes an active layer ACTd, a source Sd, and a drain Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), sources (S1, S2, S3, S4, S5, S6, and Sd), and drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are in the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), sources (S1, S2, S3, S4, S5, S6, Ss, and Sd), and drains (D1, D2, D3, D4, D5, D6, and Dd) of transistors (T1, T2, T3, T4, T5, T6, and Td) are in the same layer.

[0104] Reference Figure 4B In some embodiments, the overall structure of the semiconductor material layer further includes a plurality of first reset signal lines Vint1. The plurality of first reset signal lines Vint1 are located in the same layer as at least the active layer (e.g., ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of one or more transistors (e.g., T1, T2, T3, T4, T5, T6, and Td).

[0105] As used herein, an active layer refers to an assembly of a transistor comprising at least a portion of a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. As used herein, a source refers to an assembly of a transistor connected to one side of the active layer, and a drain refers to an assembly of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., the third transistor T3), an active layer refers to an assembly of a transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, the orthographic projection of the first portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of the second portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the case of a dual-gate transistor, a source refers to an assembly of a transistor connected to the side of the first portion away from the third portion, and a drain refers to an assembly of a transistor connected to the side of the second portion away from the third portion.

[0106] Reference Figure 3 , Figure 4A and Figure 4C In some embodiments, the first conductive layer includes the gate G1 of a first transistor T1, the gate G3 of a third transistor T3, the gate G6 of a sixth transistor T6, a plurality of light-emitting control signal lines em, and the first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the gate G1 of the first transistor T1, the gate G3 of the third transistor T3, the gate G6 of the sixth transistor T6, the plurality of light-emitting control signal lines em, and the first capacitor electrode Ce1 are in the same layer.

[0107] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, multiple light-emitting control signal lines em and a first capacitor electrode Ce1 are located in the same layer when they are formed by one or more steps of the same patterning process performed on the same material layer. In another example, multiple light-emitting control signal lines em and a first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple light-emitting control signal lines em and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view.

[0108] In some embodiments, a respective gate line among the plurality of gate lines comprises a plurality of metal blocks spaced apart from each other in a first conductive layer (e.g., Figure 4C G3 in the first signal line layer, and metal lines along the first direction in the first signal line layer (e.g., Figure 4E (GL in the first layer). Signal lines along the first direction are connected to multiple metal blocks respectively. The metal lines in the first signal line layer can be made of a metal material with relatively low resistance compared to the metal material in the first conductive layer. This design reduces the total resistance of the gate lines.

[0109] Reference Figure 3 , Figure 4A and Figure 4D In some embodiments, the second conductive layer includes a second capacitor electrode Ce2 for the storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0110] refer to Figure 3 , Figure 4A and Figure 4E In some embodiments, the first signal line layer includes a plurality of first low-voltage signal lines Vss1, a plurality of first reset control signal lines rst1, a plurality of gate lines GL, a plurality of first high-voltage signal lines Vdd1, a plurality of second reset control signal lines rst2, and node connection lines Cln. (Refer to...) Figure 5A The node connection line Cln connects the first capacitor electrode Ce1 in each pixel driving circuit to the source S3 of the third transistor T3. Various suitable conductive materials and manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple first low-voltage signal lines Vss1, multiple first reset control signal lines rst1, multiple gate lines GL, multiple first high-voltage signal lines Vdd1, multiple second reset control signal lines rs2, and the node connection line Cln are in the same layer.

[0111] In some embodiments, each first reset control signal line rst1 includes a plurality of first metal blocks spaced apart from each other in a first conductive layer, and a first metal line in a first signal line layer along a first direction, the first metal line along the first direction being respectively connected to the plurality of first metal blocks. In some embodiments, each second reset control signal line includes a plurality of second metal blocks spaced apart from each other in a first conductive layer, and a second metal line in a first signal line layer along a first direction, the second metal line along the first direction being respectively connected to the plurality of second metal blocks.

[0112] In some embodiments, each of the plurality of first low-voltage signal lines Vss1 includes a first linear portion, a second linear portion, and a connecting portion connecting the first linear portion and the second linear portion. A virtual extension of the first linear portion connects to a plurality of first metal blocks (e.g., ...) of each first reset control signal line rst1. Figure 4C The virtual extension of the second linear section intersects with the plurality of first metal blocks, for example, not with the plurality of first metal blocks of each first reset control signal line rst1 (e.g., Figure 4C The second linear portion intersects with G1 in the matrix. The orthographic projection of the second linear portion on the substrate is spaced apart from the orthographic projections of the plurality of first metal blocks. Figure 4J This is a diagram illustrating the relative positions of a corresponding one of a plurality of first low-voltage signal lines and a plurality of first metal blocks of a corresponding first reset control signal line according to some embodiments of the present disclosure. (See reference...) Figure 4J Each of the plurality of first low-voltage signal lines Vss1 includes a first linear portion LP1, a second linear portion LP2, and a connecting portion CP connecting the first linear portion LP1 and the second linear portion LP2. The virtual extension VE of the first linear portion LP1 intersects with the plurality of first metal blocks (G1) of each of the first reset control signal lines rst1. The virtual extension of the second linear portion LP2 is spaced apart from the plurality of first metal blocks, for example, it does not intersect with the plurality of first metal blocks (G1) of each of the first reset control signal lines rst1.

[0113] Reference Figure 3 , Figure 4A and Figure 4FIn some embodiments, the second signal line layer includes a plurality of data lines DL, a plurality of second low-voltage signal lines Vss2, a plurality of second reset signal lines Vint2, and a plurality of second high-voltage signal lines Vdd2. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of data lines DL, the plurality of second low-voltage signal lines Vss2, the plurality of second reset signal lines Vint2, and the plurality of second high-voltage signal lines Vdd2 are in the same layer.

[0114] See Figure 4F In some embodiments, the minimum distance between a corresponding second reset signal line of the plurality of second reset signal lines Vint2 and the corresponding second low voltage signal line of the plurality of second low voltage signal lines Vss2 that is closest to the corresponding second reset signal line is less than the minimum distance between a corresponding second reset signal line and the corresponding data line of the plurality of data lines DL that is closest to the corresponding second reset signal line. In some embodiments, a total of three data lines and a total of one second low voltage signal line are located between the two closest second reset signal lines of the plurality of second reset signal lines Vint2. Optionally, a total of three data lines, a total of one second low voltage signal line, and a total of three second high voltage signal lines are located between the two closest second reset signal lines of the plurality of second reset signal lines Vint2.

[0115] Reference Figure 3 , Figure 4D , Figure 4E and Figure 5AIn some embodiments, except for the hole region H in which a portion of the second capacitor electrode Ce2 is not present, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS completely covers the orthographic projection of the first capacitor electrode Ce1 on the substrate BS with a margin. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located in the same layer as a plurality of first low-voltage signal lines Vss1, a plurality of first reset control signal lines rst1, a plurality of gate lines GL, a plurality of first high-voltage signal lines Vdd1, and a plurality of second reset control signal lines rst2. Optionally, the display panel further includes a first connection via cv1 located in the hole region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first connection via cv1. In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the substrate BS. Optionally, the display panel further includes a first connection via cv1 and a second connection via cv2. The first connection via cv1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second connection via cv2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first connection via cv1, and the node connection line Cln is connected to the semiconductor material layer SML through the second connection via cv2. Optionally, the node connection line Cln is connected to the source S3 of the third transistor T3, such as... Figure 5A As shown.

[0116] In some embodiments, reference Figure 4D The second capacitor electrode Ce2 includes an extension E that extends away from the electrode body emb of the second capacitor electrode Ce2. (Refer to...) Figure 4A The orthographic projection of the extension E onto the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor T3 of the corresponding pixel driving circuit. A portion of the extension E is located between the first node N1 of the corresponding pixel driving circuit and a corresponding data line among the plurality of data lines DL, and is configured to prevent interference of signals to the first node N1 via the corresponding data lines.

[0117] Figure 6AThis diagram illustrates the structure of interconnected low-voltage supply networks, interconnected reset signal supply networks, and interconnected high-voltage supply networks in a display panel according to some embodiments of the present disclosure. The interconnected low-voltage supply networks include signal lines in the display area of ​​the display panel. The interconnected low-voltage supply networks are configured to provide low-voltage signals to the cathodes of a plurality of light-emitting elements. The interconnected reset signal supply networks are configured to provide reset signals to a plurality of pixel driving circuits. The interconnected reset signal supply networks include signal lines in the display area of ​​the display panel. The interconnected high-voltage supply networks are configured to provide high-voltage signals to the plurality of pixel driving circuits. The interconnected high-voltage supply networks include signal lines in the display area of ​​the display panel. In one example, a first voltage signal line is a low-voltage signal line, and a second voltage signal line is a high-voltage signal line.

[0118] Figure 6B This is a diagram illustrating the structure of an interconnected low-voltage supply network in a display panel according to some embodiments of the present disclosure. Reference Figure 6A and Figure 6B In some embodiments, the interconnected low-voltage supply network includes a plurality of first low-voltage signal lines Vss1 respectively along a first direction DR1; and a plurality of second low-voltage signal lines Vss2 respectively along a second direction DR2. The plurality of first low-voltage signal lines Vss1 intersect the plurality of second low-voltage signal lines Vss2. A corresponding one of the plurality of first low-voltage signal lines Vss1 is connected to at least a plurality of the plurality of second low-voltage signal lines Vss2. A corresponding one of the plurality of second low-voltage signal lines Vss2 is connected to at least a plurality of the plurality of first low-voltage signal lines Vss1.

[0119] Figure 5B It is along Figure 4A A cross-sectional view of line B-B' in the diagram. See also... Figure 5B , Figure 6A and Figure 6B In some embodiments, a first signal line layer SL1 includes a plurality of first low-voltage signal lines Vss1, and a second signal line layer SL2 includes a plurality of second low-voltage signal lines Vss2. The plurality of first low-voltage signal lines Vss1 and the plurality of second low-voltage signal lines Vss2 are interconnected via first vias v1s extending through a planarization layer PLN, respectively. At least some of the first vias are located in the display area. A corresponding one of the plurality of first low-voltage signal lines Vss1 is connected to at least a plurality of the plurality of second low-voltage signal lines Vss2 via a plurality of first vias extending through the planarization layer PLN. A corresponding one of the plurality of second low-voltage signal lines Vss2 is connected to at least a plurality of the plurality of first low-voltage signal lines Vss1 via a plurality of first vias extending through the planarization layer PLN.

[0120] Figure 6C This is a diagram illustrating the structure of an interconnected reset signal supply network in a display panel according to some embodiments of the present disclosure. See also Figure 6A and Figure 6C In some embodiments, the interconnected reset signal supply network includes a plurality of first reset signal lines Vint1 respectively along a first direction DR1; and a plurality of second reset signal lines Vint2 respectively along a second direction DR2. The plurality of first reset signal lines Vint1 intersect the plurality of second reset signal lines Vint2. A corresponding one of the plurality of first reset signal lines Vint1 is connected to at least a plurality of the plurality of second reset signal lines Vint2. A corresponding one of the plurality of second reset signal lines Vint2 is connected to at least a plurality of the plurality of first reset signal lines Vint1.

[0121] Figure 5C It is along Figure 4A A cross-sectional view of line C-C' in the diagram. (Refer to...) Figure 5C , Figure 6A and Figure 6C In some embodiments, the semiconductor material layer SML includes a plurality of first reset signal lines Vint1, and the second signal line layer SL2 includes a plurality of second reset signal lines Vint2. The plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are interconnected via second vias v2s extending through at least a planarization layer PLN. In one example, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are interconnected via second vias v2s, each second via extending through the planarization layer PLN, the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. A corresponding first reset signal line Vint1 is connected to at least a plurality of second reset signal lines Vint2 via a plurality of second vias extending through at least the planarization layer PLN. A corresponding second reset signal line Vint2 is connected to at least a plurality of first reset signal lines Vint1 via a plurality of second vias extending through at least the planarization layer PLN.

[0122] Optionally, the plurality of first reset signal lines Vint1 comprise semiconductor material; and the plurality of second reset signal lines Vint2 comprise metallic material. Optionally, the plurality of first reset signal lines Vint1 and at least the active layers (e.g., ACTd and ACT1 to ACT6) of the plurality of thin-film transistors (e.g., Td and T1 to T6) are located in a semiconductor material layer SML and comprise the same semiconductor material.

[0123] Alternatively, the reset signal lines (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) can be disposed in the first conductive layer. Alternatively, the reset signal lines (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) can be disposed in the first signal line layer. Alternatively, the reset signal lines (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) can be disposed in the second conductive layer. Alternatively, the reset signal lines (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) can be disposed in the second signal line layer. Alternatively, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are located on the same layer and interconnected to form a network.

[0124] Figure 6D This is a diagram illustrating the structure of an interconnected high-voltage supply network in a display panel according to some embodiments of the present disclosure. (Reference) Figure 6A and Figure 6D In some embodiments, the interconnected high-voltage supply network includes a plurality of first high-voltage signal lines Vdd1 respectively along a first direction DR1; and a plurality of second high-voltage signal lines Vdd2 respectively along a second direction DR2. The plurality of first high-voltage signal lines Vdd1 intersect the plurality of second high-voltage signal lines Vdd2. A corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to at least a plurality of the plurality of second high-voltage signal lines Vdd2. A corresponding one of the plurality of second high-voltage signal lines Vdd2 is connected to at least a plurality of the plurality of first high-voltage signal lines Vdd1.

[0125] Figure 5D It is along Figure 4A A cross-sectional view of line D-D' in the diagram. See also... Figure 5D , Figure 6A and Figure 6D In some embodiments, the first signal line layer SL1 includes a plurality of first high-voltage signal lines Vdd1, and the second signal line layer SL2 includes a plurality of second high-voltage signal lines Vdd2. A corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to a second capacitor electrode via one or more third vias v3s extending through the interlayer dielectric layer ILD. A corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to at least a plurality of the plurality of second high-voltage signal lines Vdd2 via a plurality of third vias extending through the planarization layer PLN. A corresponding one of the plurality of second high-voltage signal lines Vdd2 is connected to at least a plurality of the plurality of first high-voltage signal lines Vdd1 via a plurality of third vias extending through the planarization layer PLN.

[0126] Figure 5EIt is along Figure 4A A cross-sectional view of line E-E' in the diagram. See also... Figure 5E , Figure 6A and Figure 6D In some embodiments, the first signal line layer SL1 includes a plurality of first high-voltage signal lines Vdd1, and the second signal line layer SL2 includes a plurality of second high-voltage signal lines Vdd2. A corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to a second capacitor electrode via one or more third vias v3s extending through the interlayer dielectric layer ILD. A corresponding one of the plurality of second high-voltage signal lines Vdd2 is connected to a corresponding one of the plurality of first high-voltage signal lines Vdd1 via one or more fourth vias v4s extending through the planarization layer PLN. A corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to the source S4 of a fourth transistor via a third connection via cv4 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0127] Figure 4G This is a diagram illustrating the structure of a corresponding one of a plurality of first high-voltage signal lines according to some embodiments of the present disclosure. Reference Figure 4G In some embodiments, a corresponding one of the plurality of first high-voltage signal lines Vdd1 includes a body md extending along a first direction DR1, a first protrusion pd1 protruding away from the body md along a second direction DR2, and a second protrusion pd2 protruding away from the first protrusion pd1 along the second direction DR2. The second protrusion pd2 is connected to the body md through the first protrusion pd1. The first protrusion pd1 is a portion of a corresponding one of the plurality of first high-voltage signal lines Vdd1, in which the corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to a second capacitor electrode. The second protrusion pd2 is a portion of a corresponding one of the plurality of first high-voltage signal lines Vdd1, in which the corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to the source of a fourth transistor. The drain of the fourth transistor is connected to the source of a driving transistor.

[0128] Figure 4H This is a diagram illustrating the layout of the anode of a light-emitting element relative to the pixel driving circuitry of a display panel in some embodiments of the present disclosure. Figure 4I This is a diagram illustrating the structure of the anode, first signal line layer, and second signal line layer in a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 4H and Figure 4I In some embodiments, the display panel further includes multiple anodes of multiple light-emitting elements, such as Figure 4H As shown, the first anode AD1, the second anode AD2, and the third anode AD3 are shown. Each anode extends through the second planarization layer (e.g., Figures 5A to 5EThe through-hole of PLN2 is connected to the anode contact pad, and the anode contact pad extends through the planarization layer (e.g., Figures 5A to 5E The vias of the PLN are connected to the relay electrode. The relay electrode is connected to the N4 node (e.g., the drain of the fifth transistor) through vias extending through the interlayer dielectric layer.

[0129] refer to Figure 4H , Figure 4I , Figure 4E and Figure 4F In one example, the first anode AD1 is connected to the first anode contact pad ACP1 via a through-hole extending through the second planarization layer, and the first anode contact pad ACP1 is connected to the first relay electrode RE1 via a through-hole extending through the planarization layer; the second anode AD2 is connected to the second anode contact pad ACP2 via a through-hole extending through the second planarization layer, and the second anode contact pad ACP2 is connected to the second relay electrode RE2 via a through-hole extending through the planarization layer; the third anode AD3 is connected to the third anode contact pad ACP3 via a through-hole extending through the second planarization layer, and the third anode contact pad ACP3 is connected to the third relay electrode RE3 via a through-hole extending through the planarization layer.

[0130] In some embodiments, refer to Figure 1 The display panel also includes an array gate circuit (GOA) located in the peripheral region PA of the display panel. The interconnecting low-voltage supply network (VSSN) includes a first peripheral low-voltage line (pvss1) on the first side S1 of the display panel in the peripheral region PA. Figure 7A It is shown Figure 1 A schematic diagram of the structure in the first region ZR1. Figure 7B It is shown Figure 7A A diagram showing the structure of the first signal line layer in the first region ZR1. Figure 7C It is shown Figure 7A A diagram showing the structure of the second signal line layer in the first region ZR1. Figure 7D It is shown Figure 7A A diagram showing the structure of the second planarization layer in the first region ZR1. Figure 7E It is shown Figure 7A A diagram showing the structure of the anode layer in the first region ZR1.

[0131] Figure 7F It is shown Figure 7A A diagram showing the structure of the third planarization layer in the first region ZR1. Figure 7G It is shown Figure 7A A diagram showing the structure of the cathode layer in the first region ZR1. (Refer to...) Figures 7A to 7G as well as Figure 1In the peripheral region PA on the first side S1 of the display panel, the display panel includes an array gate circuit GOA located on the substrate in the first signal line layer, a first peripheral low voltage line pvss1 located on the side of the array gate circuit GOA away from the substrate in the second signal line layer, a second planarization layer PLN2 located on the side of the first peripheral low voltage line pvss1 away from the array gate circuit GOA, an anode metal layer AML located on the side of the second planarization layer PLN2 away from the first peripheral low voltage line pvss1 in the anode layer, a third planarization layer PLN3 located on the side of the anode metal layer AML away from the second planarization layer PLN2, and a cathode layer CDL located on the side of the third planarization layer PLN3 away from the anode metal layer AML.

[0132] Figure 8 It is along Figure 7A The cross-sectional view of line F-F' in the diagram. (Refer to...) Figure 1 , Figure 7A and Figure 8 In some embodiments, the orthographic projection of the first peripheral low voltage line pvss1 on the substrate BS at least partially overlaps with the orthographic projection of the array gate circuit GOA on the substrate BS. Optionally, the orthographic projection of the first peripheral low voltage line pvss1 on the substrate BS overlaps with the orthographic projection of the array gate circuit GOA on the substrate BS by at least 80% (e.g., at least 85%, at least 90%, at least 95%, at least 99%).

[0133] refer to Figure 8 The cathode layer CDL is connected to the anode metal layer AML via one or more first peripheral vias pv1 extending through the third planarization layer PLN3 in the peripheral region, and the anode metal layer AML is connected to the first peripheral first voltage line pvss1 via one or more second peripheral vias pv2 extending through the second planarization layer PLN2 in the peripheral region, thereby providing a first voltage signal to the cathodes of the plurality of light-emitting elements. The display panel includes a plurality of first gas release vias grev1 extending through the first peripheral first voltage line pvss1 for releasing gas in the underlying insulating layer (e.g., the planarization layer PLN) during the manufacturing process of the display panel. The display panel also includes a plurality of second gas release vias grev2 extending through the anode metal layer AML to release gas in the underlying insulating layer (e.g., the second planarization layer PLN2) during the manufacturing process of the display panel.

[0134] In some embodiments, the cathode layer CDL is a monolithic cathode layer that extends substantially throughout the entire display panel and serves as the cathode for multiple light-emitting elements. Optionally, one or more vias connecting the cathode layer CDL and the anode metal layer AML are confined in the peripheral region PA, and not in the display region DA. The cathode layer CDL is connected to the interconnected low-voltage supply network VSSN only through the anode metal layer AML.

[0135] In this display panel, the low-voltage lines share the same space as the array gate circuit (GOA). The display panel can be made with a very narrow bezel. In one example, this display panel has a bezel width of approximately 1.5 mm on the first side S1 (or the side opposite to the first side S1) compared to 2.5 mm in a related display panel.

[0136] Furthermore, in this display panel, the connection between the low-voltage line and the cathode layer CDL (through the anode metal layer) can be made only in the peripheral area PA (e.g., in the GOA region), thus eliminating the need to fabricate vias (or any processes) in the display area DA to connect the low-voltage line and the cathode layer CDL. The display panel can be manufactured with significantly less complexity, substantially reducing the occurrence of defects in the display panel.

[0137] The inventors of this disclosure have discovered, surprisingly and unexpectedly, that the implementation of an interconnected low-voltage supply network significantly reduces the voltage drop of low-voltage signals (e.g., VSS signals) across the entire display panel. Figure 9A The IR drop in a display panel is shown in some embodiments according to this disclosure. Figure 9B This illustrates the IR drop in a relevant display panel in the absence of an interconnected low-voltage supply network. Figure 9A and Figure 9B In the image, darkness indicates the degree of IR drop in a localized region. (Comparison) Figure 9A and Figure 9B The voltage drop in the embodiments according to this disclosure is significantly reduced compared to the voltage drop in related display panels without interconnected low-voltage supply networks. Overall, the IR drop is reduced from 1.5641V to 1.2337V (a reduction of more than 20%). The advantages of this display panel are particularly significant for large-size display panels. In related display panels without interconnected low-voltage supply networks, such as... Figure 9B As shown, the VSS current is concentrated at the outermost two ports, leading to problems such as high-current burns. For example, in a display panel with an unconnected low-voltage supply network, the VSS current at the outermost port is approximately 26.6% of the total VSS current. In display panels according to some embodiments of this disclosure, the VSS current at any port is less than 11% of the total VSS current, avoiding the problem of high-current burns.

[0138] To accommodate the interconnecting networks in this display panel, the layers and signal lines in the peripheral area employ a novel and unique structure that facilitates further reduction of bezel width, improves voltage uniformity across the entire display panel, and minimizes defects in the display panel. Figure 10A It is shown Figure 1 A schematic diagram of the structure in the second enlarged region ZR2. Figure 10B It is shown Figure 10A A schematic diagram of the structure of a medium- and low-voltage signal line. Figure 10C It is shown Figure 10A A schematic diagram of the structure of the high-voltage signal line in the diagram. (Refer to...) Figure 1 , Figure 10A , Figure 10B as well as Figure 10C In some embodiments, the display panel includes a peripheral high-voltage signal line pvdd, a second peripheral low-voltage signal line pvss2, and a third peripheral low-voltage signal line pvss3 located in the peripheral region PA on the second side S2 of the display panel. One or more of the plurality of second high-voltage signal lines Vdd2 are connected to the peripheral high-voltage signal line pvdd. One or more of the plurality of second low-voltage signal lines Vss2 are connected to the second peripheral low-voltage signal line pvss2. The second peripheral low-voltage signal lines pvss2 and the third peripheral low-voltage signal line pvss3 are connected to each other through a plurality of bridges bg. Optionally, the plurality of first low-voltage signal lines, the peripheral high-voltage signal line pvdd, and the plurality of bridges are located within the first signal line layer SL1 (e.g., refer to...). Figure 5A (Layer arrangement of the display panel in the image). Optionally, a plurality of second high-voltage signal lines Vdd2 and second peripheral low-voltage signal lines pvss2 are located in the second signal line layer SL2. Optionally, the third peripheral low-voltage signal line pvss3 is included in the first sub-layer in the first signal line layer SL1 and the second sub-layer in the second signal line layer SL2.

[0139] Figure 10D It is shown Figure 10A A schematic diagram of the reset signal line structure. (Refer to...) Figure 1 , Figure 10A and Figure 10DIn some embodiments, the display panel includes a peripheral reset signal line pvint located on the second side S2 of the display panel in the peripheral region PA. One or more of a plurality of second reset signal lines Vint2 are connected to the peripheral reset signal line pvint. Optionally, the peripheral reset signal line pvint is located in a different layer than the peripheral high-voltage signal line pvdd and the peripheral low-voltage signal line pvss2. Optionally, the peripheral reset signal line pvint is located in the same layer as the plurality of second reset signal lines Vint2. Optionally, the peripheral reset signal line pvint is located in a different layer than the plurality of second reset signal lines Vint2. In some embodiments, the peripheral reset signal line pvint includes a first portion p1 and a second portion p2. Optionally, the first portion p1 includes a single layer of conductive material in the same layer as the second signal line layer. Optionally, the second portion has a double-layer structure, the double-layer structure including conductive materials located in the first signal line layer and the second signal line layer, respectively.

[0140] Reference Figure 10A In some embodiments, the display panel further includes an anode metal layer AML. In some embodiments, the anode metal layer AML is connected to a peripheral low-voltage signal line pvss2 via a via extending through one or more insulating layers.

[0141] Various suitable implementations of interconnected low-voltage supply networks can be practiced based on this disclosure. Figure 11A This is a diagram illustrating the structure of a first sub-network of an interconnected low-voltage supply network according to some embodiments of the present disclosure. Figure 11B This is a diagram illustrating the structure of a second subnetwork of an interconnected low-voltage supply network according to some embodiments of the present disclosure. Figure 11C This is a diagram illustrating the structure of a low-voltage supply network including the interconnection of a first subnetwork and a second subnetwork according to some embodiments of the present disclosure. (See reference...) Figures 11A to 11C In some embodiments, the interconnected low-voltage supply network includes a first sub-network formed by a plurality of first low-voltage signal lines Vss1 and a second sub-network formed by a plurality of second low-voltage signal lines Vss2. Optionally, the first sub-network is located in a first signal line layer, and the second sub-network is located in a second signal line layer. The plurality of first signal lines Vss1 are electrically connected to the plurality of second signal lines Vss2.

[0142] In some embodiments, a plurality of first low-voltage signal lines Vss1 form a subnetwork, while a plurality of second low-voltage signal lines Vss2 do not form a subnetwork.

[0143] Figure 12AThis is a diagram illustrating the structure of a plurality of first low-voltage signal lines of an interconnected low-voltage supply network according to some embodiments of the present disclosure. Figure 12B This is a diagram illustrating the structure of a subnetwork of multiple second low-voltage signal lines of an interconnected low-voltage supply network according to some embodiments of the present disclosure. Figure 12C This is a diagram illustrating the structure of an interconnected low-voltage supply network according to some embodiments of the present disclosure, the low-voltage supply network including a subnetwork of multiple first low-voltage signal lines and multiple second low-voltage signal lines. Reference Figures 12A to 12C Multiple first low-voltage signal lines Vss1 are separate from each other and do not form a subnetwork, while multiple second low-voltage signal lines Vss2 form a subnetwork. The multiple first signal lines Vss1 are electrically connected to the multiple second signal lines Vss2.

[0144] In another aspect, this disclosure provides a display panel. In some embodiments, the display panel includes a plurality of pixel driving circuits configured to drive a plurality of light-emitting elements to emit light, respectively. (See also...) Figure 3 , Figures 4A to 4I Each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor Td, a first reset transistor (first transistor T1) configured to reset a first node N1 including the gate of the driving transistor Td, and a second reset transistor (sixth transistor T6) configured to reset the anode of each of the plurality of light-emitting elements LE. Optionally, the first electrodes of adjacent first reset transistors in adjacent pixel driving circuits along the first direction DR1 are connected to each other via a first connection line (e.g., a first adjacent first reset signal line in a plurality of first reset signal lines Vint1); the first electrodes of adjacent second reset transistors in adjacent pixel driving circuits along the first direction are connected to each other via a second connection line (e.g., a second adjacent first reset signal line in a plurality of first reset signal lines Vint1). Optionally, the first connection line and the second connection line are located in a semiconductor material layer. Optionally, refer to Figures 4A to 4I as well as Figure 6A The first electrodes of the six adjacent first reset transistors in the six adjacent pixel driving circuits along the first direction are respectively connected to three adjacent first node reset signal lines (e.g., three adjacent second reset signal lines in a plurality of second reset signal lines Vint2) through three first vias. The first connecting line and the second connecting line extend along the first direction DR1. The three adjacent first node reset signal lines extend along the second direction DR2. The first direction DR1 and the second direction DR2 intersect each other.

[0145] The inventors of this disclosure have discovered that by connecting the first electrodes of adjacent first reset transistors in adjacent pixel driving circuits along the first direction DR1 to each other through a first connection line, the manufacturing process can be simplified, the number of vias connecting the reset transistors and the reset signal lines can be reduced, and the resistance in the reset signal lines can be lowered.

[0146] Optionally, the first electrodes of the six adjacent second reset transistors in the six adjacent pixel driving circuits along the first direction DR1 are respectively connected to three adjacent anode reset signal lines (e.g., three adjacent second reset signal lines in a plurality of second reset signal lines Vint2) through three second vias. In one example, the three adjacent first node reset signal lines are the same as the three adjacent anode reset signal lines.

[0147] The inventors of this disclosure have discovered that by connecting the first electrodes of adjacent second reset transistors in adjacent pixel driving circuits along the first direction DR1 to each other through a second connection line, the manufacturing process can be simplified, the number of vias connecting the reset transistors and the reset signal lines can be reduced, and the resistance in the reset signal lines can be lowered.

[0148] Optionally, refer to Figure 6A Three adjacent first node reset signal lines are connected to the first connection line through three first vias; and three adjacent anode reset signal lines are connected to the second connection line through three second vias. A first node reset signal line is connected to the first connection line through one first via. An anode reset signal line is connected to the second connection line through one second via.

[0149] Optionally, the display panel further includes a plurality of first high-voltage signal lines Vdd1 extending along a first direction DR1 and a plurality of second high-voltage signal lines Vdd2 extending along a second direction DR2. The plurality of first high-voltage signal lines Vdd1 and the plurality of second high-voltage signal lines Vdd2 are interconnected with each other through vias to form an interconnected network. The inventors of this disclosure have discovered that by providing an interconnected network, the resistance of the high-voltage signal lines can be reduced.

[0150] Optionally, refer to Figure 3 as well as Figures 4A to 4I Each pixel driving circuit also includes a storage capacitor Cst. Optionally, the second capacitor electrodes of the storage capacitors of the pixel driving circuits along the first direction DR1 are connected to each other to form an integral structure. Optionally, the second capacitor electrode of the storage capacitor Cst is connected to one of the corresponding first high voltage signal lines among the plurality of first high voltage signal lines Vdd1 or one of the corresponding second high voltage signal lines Vdd2.

[0151] Optionally, the first node N1 further includes a node connection line Cln, which connects the gate of the driving transistor Td in each pixel driving circuit to the first electrode of the compensation transistor (e.g., the third transistor T3). Optionally, each of the plurality of first high-voltage signal lines Vdd1 includes a body md and a protrusion protruding away from the body md along the second direction DR2. Optionally, the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the first node N1 on the substrate. The inventors of this disclosure have discovered that by making the orthographic projection of the protrusion on the substrate at least partially overlap with the orthographic projection of the first node N1 on the substrate, the voltage level at the first node N1 can be stabilized.

[0152] Optionally, the orthographic projection of the combination of a corresponding first high-voltage signal line in a plurality of first high-voltage signal lines Vdd1 and a corresponding second high-voltage signal line in a plurality of second high-voltage signal lines Vdd2 onto the substrate covers the orthographic projection of the node connection line Cln onto the substrate. The inventors of this disclosure have discovered that by making the orthographic projection of the combination of a corresponding first high-voltage signal line in a plurality of first high-voltage signal lines Vdd1 and a corresponding second high-voltage signal line in a plurality of second high-voltage signal lines Vdd2 onto the substrate covers the orthographic projection of the node connection line Cln onto the substrate, the voltage level at the first node N1 can be stabilized.

[0153] Optionally, the protrusion includes a connecting portion and a terminal portion. The terminal portion is connected to the body md at least via the connecting portion. Optionally, the width of the terminal portion along the first direction is greater than the width of the connecting portion along the first direction.

[0154] Optionally, the display panel further includes a plurality of first low-voltage signal lines Vss1 extending along a first direction DR1, and a plurality of second low-voltage signal lines Vss2 extending along a second direction DR2. Optionally, the plurality of first low-voltage signal lines Vss1 and the plurality of second low-voltage signal lines Vss2 are interconnected via vias. The inventors of this disclosure have discovered that by interconnecting the plurality of first low-voltage signal lines Vss1 and the plurality of second low-voltage signal lines Vss2, the resistance of the low-voltage signal lines can be reduced.

[0155] Optionally, each pixel driving circuit also includes a storage capacitor and a shielding block. Figure 4D (E is used to represent this). Optionally, the second capacitor electrode of the storage capacitor and the shielding block are located on the same layer. Optionally, the second capacitor electrode of the storage capacitor and the shielding block are part of an integral structure. Optionally, the shielding block includes a main body extending along the first direction DR1, a first extension extending along the second direction DR2, and a second extension extending along the second direction DR2.

[0156] Optionally, refer to Figure 3 , Figures 4A to 4I as well as Figures 5A to 5E The orthographic projection of the first extension on the substrate covers the orthographic projection of a portion of the semiconductor material layer located between the two channels of the compensation transistor (e.g., the third transistor T3) on the substrate. The inventors of this disclosure have discovered that by making the orthographic projection of the first extension on the substrate cover the orthographic projection of a portion of the semiconductor material layer located between the two channels of the compensation transistor on the substrate, the compensation transistor can be shielded from irradiation.

[0157] Optionally, the second extension at least partially overlaps with the node connection line Cln along the second direction. The inventors of this disclosure have discovered that by making the second extension at least partially overlap with the node connection line Cln along the second direction, the first node N1 can be at least partially shielded from interference from at least some signal lines extending along the first direction DR1.

[0158] Optionally, the first node further includes a node connection line Cln that connects the gate of the driving transistor Td in each corresponding pixel driving circuit to the first electrode of a compensation transistor (e.g., a third transistor T3). Optionally, a second extension spaces the node connection line Cln apart from the respective data lines configured to provide data signals to the corresponding pixel driving circuits. The inventors of this disclosure have discovered that by making the second extension space the node connection line Cln apart from the respective data lines, the first node N1 can be at least partially shielded from interference from the respective data lines.

[0159] In another aspect, the present invention provides a display device comprising a display panel manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the display panel. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a liquid crystal display (LCD) device.

[0160] In another aspect, the present invention provides a method for manufacturing a display panel. In some embodiments, the method includes forming a plurality of light-emitting elements; and forming an interconnected low-voltage supply network configured to provide low-voltage signals to the cathodes of the plurality of light-emitting elements. Optionally, forming the interconnected low-voltage supply network includes forming signal lines in a display area of ​​the display panel.

[0161] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A display panel, comprising: Multiple pixel driving circuits are configured to drive multiple light-emitting elements to emit light respectively; Each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a first reset transistor configured to reset a first node of the gate of the driving transistor, and a second reset transistor configured to reset the anode of each of the plurality of light-emitting elements. The first electrodes of adjacent first reset transistors in adjacent pixel driving circuits along the first direction are connected to each other via a first connection line. The first electrodes of adjacent second reset transistors in the adjacent pixel driving circuit along the first direction are connected to each other via a second connection line. The first connection line and the second connection line are located in a semiconductor material layer; The first electrodes of the six adjacent first reset transistors in the six adjacent pixel driving circuits along the first direction are respectively connected to the three adjacent first node reset signal lines through three first vias. The first connecting line and the second connecting line extend along the first direction; and The three adjacent first node reset signal lines extend along the second direction, and the first direction and the second direction intersect each other.

2. The display panel according to claim 1, wherein, The first electrodes of the six adjacent second reset transistors in the six adjacent pixel driving circuits along the first direction are connected to the three adjacent anode reset signal lines through three second vias.

3. The display panel according to claim 2, wherein, The first node reset signal line is connected to the first connection line through a first via; as well as The anode reset signal line is connected to the second connection line through a second via.

4. The display panel according to claim 1, further comprising a plurality of first high-voltage signal lines extending along the first direction and a plurality of second high-voltage signal lines extending along the second direction; and The plurality of first high-voltage signal lines and the plurality of second high-voltage signal lines are interconnected with each other through vias to form an interconnected network.

5. The display panel according to claim 4, wherein, Each pixel driving circuit also includes a storage capacitor; The second capacitor electrodes of the storage capacitor of the pixel driving circuit along the first direction are connected to each other to form an integral structure; as well as The second capacitor electrode of the storage capacitor is connected to a corresponding first high voltage signal line among the plurality of first high voltage signal lines or a corresponding second high voltage signal line among the plurality of second high voltage signal lines.

6. The display panel according to claim 4, wherein, The first node also includes a node connection line that connects the gate of the driving transistor in each pixel driving circuit to the first electrode of the compensation transistor. Each of the plurality of first high-voltage signal lines includes a body and a protrusion that protrudes away from the body along the second direction; as well as The orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the first node on the substrate.

7. The display panel according to claim 6, wherein, The orthographic projection of the combination of a corresponding first high-voltage signal line among the plurality of first high-voltage signal lines and a corresponding second high-voltage signal line among the plurality of second high-voltage signal lines on the substrate covers the orthographic projection of the node connection line on the substrate.

8. The display panel according to claim 6, wherein, The protrusion includes a connecting portion and a terminal portion; The terminal portion is connected to the body at least via the connecting portion; and The width of the terminal portion along the first direction is greater than the width of the connecting portion along the first direction.

9. The display panel according to claim 1, further comprising a plurality of first low-voltage signal lines extending along the first direction and a plurality of second low-voltage signal lines extending along the second direction; in, The plurality of first low-voltage signal lines and the plurality of second low-voltage signal lines are interconnected via vias.

10. The display panel according to claim 1, wherein, Each pixel driving circuit also includes a storage capacitor and a shielding block; The shielding block and the second capacitor electrode of the storage capacitor are located on the same layer; as well as The shielding block includes a main body extending along the first direction, a first extension extending along the second direction, and a second extension extending along the second direction.

11. The display panel according to claim 10, wherein, The orthographic projection of the first extension onto the substrate covers the orthographic projection of a portion of the semiconductor material layer located between the two channels of the compensation transistor onto the substrate.

12. The display panel according to claim 10, wherein, The first node further includes a node connection line that connects the gate of the driving transistor in each pixel driving circuit to the first electrode of the compensation transistor; and The second extension at least partially overlaps with the node connection line along the second direction.

13. The display panel according to claim 10, wherein, The first node further includes a node connection line that connects the gate of the driving transistor in each pixel driving circuit to the first electrode of the compensation transistor; and The second extension spacees the node connection line from each data line configured to provide data signals to each pixel driving circuit.

14. The display panel according to claim 1, wherein, The display panel includes: Multiple light-emitting elements; and An interconnected first voltage supply network is configured to provide a first voltage signal to the cathodes of the plurality of light-emitting elements; The interconnected first voltage supply network includes signal lines in the display area of ​​the display panel, the display area being at least partially surrounded by a peripheral area; The signal lines include a plurality of first signal lines located in a first signal line layer and a plurality of second signal lines located in a second signal line layer; The display panel further includes a planarization layer located between the first signal line layer and the second signal line layer; and The plurality of first signal lines are electrically connected to the plurality of second signal lines.

15. The display panel according to claim 14, wherein, The interconnected first voltage supply network includes: Multiple first-first voltage signal lines respectively along a first direction; and Multiple second-first voltage signal lines respectively along the second direction; The plurality of first-first voltage signal lines intersect with the plurality of second-first voltage signal lines respectively.

16. The display panel according to claim 15, wherein, The interconnected first voltage supply network includes a first sub-network formed by the plurality of first-first voltage signal lines and a second sub-network formed by the plurality of second-first voltage signal lines.

17. The display panel according to claim 15, wherein, A corresponding one of the plurality of first-first voltage signal lines is connected to at least a plurality of the plurality of second-first voltage signal lines; as well as One of the plurality of second-first voltage signal lines is connected to at least one of the plurality of first-first voltage signal lines.

18. The display panel according to claim 15, wherein, The plurality of first-first voltage signal lines and the plurality of second-first voltage signal lines are interconnected by first vias extending through the planarization layer, at least some of the first vias being in the display area; Each of the plurality of first-first voltage signal lines is connected to at least one of the plurality of second-first voltage signal lines through a plurality of first vias extending through the planarization layer; as well as Each of the plurality of second-first voltage signal lines is connected to at least one of the plurality of first-first voltage signal lines via a plurality of first vias extending through the planarization layer.

19. The display panel according to claim 14, further comprising an array gate circuit in the peripheral region of the display panel; in, The interconnected first voltage supply network includes a first peripheral first voltage line in the peripheral region on the first side of the display panel; as well as The orthographic projection of the first peripheral voltage line on the substrate at least partially overlaps with the orthographic projection of the array gate circuit on the substrate.

20. A display device comprising a display panel according to any one of claims 1 to 19, and one or more integrated circuits connected to the display panel.

Images