A method for improving the switching speed of a trench-type SIC MOSFET device

Abstract

The application discloses a method for improving the switching speed of a trench type SICMOSFET device, belongs to the technical field of semiconductor devices, and can form a trench on the surface of a SIC epitaxial layer, grow a gate oxide film on the bottom and sidewall of the trench, deposit a polysilicon thin film on the formed gate oxide film, etch the polysilicon film on the bottom of the trench, deposit Nitride on the polysilicon thin film, etch the Nitride in the trench, grow an oxide layer on the polysilicon from which the Nitride is etched, then remove the remaining Nitride, and deposit a layer of polysilicon on the basis to form a new device structure method for reducing Cgd, so that the technical effects of avoiding excessive Cgd, reducing the switching speed of the device and reducing the loss of the device are achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a method for improving the switching speed of a trench-type SIC MOSFET device. Background Art

[0002] Generally speaking, SiC MOSFET devices offer lower on-resistance, higher temperature resistance, and higher switching speeds compared to Si MOSFET devices, offering significant advantages in applications such as automotive, transportation, and high-voltage frequency conversion. However, the structural characteristics of the trench bottom of trench SiC MOSFET devices still result in slower switching speeds, which are determined by the trench bottom capacitance and gate charge.

[0003] The capacitance value of the trench SICMOSFET device is nonlinear, which is related to the structure, shape and related voltage of the device. In the trench SICMOSFET structure, there are three types of capacitance, namely gate-source capacitance (Cgs), gate-drain capacitance (Cgd), and source-drain capacitance (Csd), namely input capacitance, output capacitance and reverse capacitance. The expressions are Cgd = Crss, Cgs = Ciss-Crss, and Cds = Coss-Crss. (Ciss is the input capacitance, Coss is the output capacitance, and Crss is the reverse capacitance.) Assuming that the source-drain and gate-source terminals are disconnected, there is only reverse capacitance (Crss), and in this case, Crss = Cgd. Figure 2 As shown, the reverse capacitance is related to the morphology of the trench bottom.

[0004] When Ig>0, the gate-source capacitance and gate-drain capacitance are charging. When the gate voltage increases, the gate-source voltage is equal to the turn-on voltage. At this time, the device will form a conductive channel, and the gate current will flow to the drain. Due to the gate-drain capacitance, part of the gate current will be used, and the gate-source voltage will reflect a certain value in a certain period of time, resulting in switching delay. Figure 3 The state between points B and C is shown in Figure 1. We call this delay period the Miller platform. To further increase the switching speed, we need to shorten this delay period. After that, if we want to further increase the gate voltage, the device will turn on. At this time, the gate voltage is only affected by the on-resistance and drain current, as shown in Figure 1. Figure 3 Middle point D state.

[0005] Therefore, in order to avoid excessive Cgd, further slow down the switching rate of the device, and reduce the loss of the device, the device structure method is particularly important. Traditional device structure methods include the following two methods:

[0006] First, a trench is formed on the SIC epitaxial layer; second, an implantation pattern is formed on the SIC epitaxial layer; third, a large amount of ions are implanted at the bottom of the trench; third, a dielectric layer is grown at the bottom of the trench; and finally, polysilicon is grown. Although the above method can grow a thick oxide film at the bottom of the trench, the implantation will cause the trench sidewall gate oxide to be more than 70% thicker than the target setting value, which in turn affects the quality of the trench sidewall oxide layer.

[0007] 2. First, a trench is formed on the SIC epitaxial layer; second, Nitride is grown on the sidewalls and bottom of the trench; third, the Nitride at the bottom of the trench is etched; third, a dielectric layer is grown at the bottom of the etched trench; finally, excess Nitride is etched away and polysilicon is grown; although the above method will not make the sidewall oxide layer as thick as in option 1, a "bird's beak" phenomenon will occur.

[0008] A new device structure method is now proposed to solve the above problems. Summary of the Invention

[0009] In view of the deficiencies of the prior art, the present invention provides a method for improving the switching speed of a trench SIC MOSFET device, thereby solving the above-mentioned problems.

[0010] To achieve the above objectives, the present invention is implemented through the following technical solutions: A method for improving the switching speed of a trench SICMOSFET device, comprising the following steps:

[0011] S1, forming a groove on the surface of the SIC epitaxial layer;

[0012] S2, growing gate oxide film on the bottom and sidewalls of the trench;

[0013] S3, depositing a polysilicon film on the gate oxide film, and etching the polysilicon film at the bottom of the trench;

[0014] S4, depositing Nitride on the etched polysilicon film;

[0015] S5, etching the Nitride groove;

[0016] S6, growing an oxide layer on the polysilicon film etched with Nitride;

[0017] S7, remove the remaining Nitride;

[0018] S8, after completing the operation of S7, a layer of polysilicon is grown in the trench.

[0019] Wherein, the thickness of the polysilicon film is The thickness of Nitride deposited on the polysilicon film is

[0020] On the basis of the above technical solutions, the present invention also provides the following optional technical solutions:

[0021] Further technical solution: The thickness ratio of the polysilicon film to the Nitride is 1:1.67 to 1:1.5.

[0022] Further technical solution: The type of the SiC epitaxial layer can be the same as or different from that of the SiC wafer, wherein the SiC wafer is oriented and is N-type or P-type.

[0023] Further technical solution: The method of etching the Nitride in the groove in S5 is dry etching.

[0024] Further technical solution: the groove is U-shaped as a whole, and the groove smoothly transitions to the SIC epitaxial layer.

[0025] Application of the above method for improving the switching speed of trench SIC MOSFET devices in the manufacture of SIC MOSFET devices

[0026] Beneficial effects

[0027] The present invention provides a method for improving the switching speed of a trench SIC MOSFET device, which has the following advantages compared to the prior art:

[0028] 1. A new device structure method for reducing Cgd can be formed by forming a trench on the surface of the SIC epitaxial layer and growing a gate oxide film at the bottom and sidewalls of the trench, depositing a polysilicon film on the formed gate oxide film, etching the polysilicon film at the bottom of the trench, and depositing Nitride on the polysilicon film. Then, the Nitride in the trench is etched and an oxide layer is grown on the polysilicon from which the Nitride has been etched. Finally, the remaining Nitride is removed and a layer of polysilicon is grown on this basis to form a new device structure method for reducing Cgd. This method achieves the technical effects of avoiding excessive Cgd, slowing down the device switching rate, and reducing device loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the steps of the present invention.

[0030] Figure 2 This is a diagram showing the relationship between reverse capacitance and trench bottom morphology.

[0031] Figure 3 V GS Graph of relationship with time.

[0032] Figure 4 Polysilicon etching morphology. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0034] The specific implementation of the present invention is described in detail below with reference to specific embodiments.

[0035] See also Figure 1 , according to an embodiment of the present invention, a method for improving the switching speed of a trench SIC MOSFET device comprises the following steps:

[0036] S1. Form a groove on the surface of the SIC epitaxial layer, such as Figure 1 As shown in (a), the groove is formed by dry etching.

[0037] S2, growing a gate oxide film at the bottom and sidewalls of the trench, such as Figure 1 As shown in (b), the trench bottom and sidewall films are formed into silicon dioxide by thermal oxidation.

[0038] S3, depositing a thin polysilicon film on the gate oxide film, and etching the polysilicon at the bottom of the trench by dry etching (the purpose of etching the polysilicon at the bottom of the trench by dry etching is to avoid the edge effect caused by chemical penetration when removing the nitride by wet chemical method in the subsequent S7 operation, because adding a thin polysilicon film can prevent the edge effect). Figure 1 As shown in (c);

[0039] S4, depositing Nitride (nitride) on the polysilicon film;

[0040] S5, etching the Nitride at the bottom of the trench;

[0041] S6, grow an oxide layer at the bottom of the trench where Nitride is etched, such as Figure 1 As shown in (d), the oxide layer is a silicon dioxide oxide layer;

[0042] S7, remove the remaining Nitride, such as Figure 1 As shown in (e);

[0043] S8. After completing the operation of S7, a layer of polysilicon is grown in the trench, such as Figure 1 As shown in (f).

[0044] Specifically, the thickness of the polysilicon film deposited in S3 is The purpose of this setting is that if the thickness of polysilicon is greater than If the amount of polysilicon etching is too much, it will affect the thickness of the oxide layer at the bottom of the trench. If the etching amount is too small, both will lead to the phenomenon of poor polysilicon etching morphology, such as Figure 4 As shown:

[0045] Specifically, the Nitride deposited on the polysilicon film in S4 is In order to avoid aggravating the "bird's beak" phenomenon during the dry engraving process, this thickness can weaken the "bird's beak" phenomenon;

[0046] Specifically, the thickness ratio of the polysilicon film to the nitride is 1:1.67 to 1:1.5, which allows the polysilicon to better buffer the edge problems caused by the nitride.

[0047] Specifically, the trench is U-shaped as a whole, and the trench smoothly transitions to the SIC epitaxial layer.

[0048] Specifically, the gate oxide film is formed using a conventional silicon gate oxidation process.

[0049] Preferably, the type of the SiC epitaxial layer may be the same as or different from that of the SiC wafer, wherein the SiC wafer has a crystal orientation and may be N-type or P-type.

[0050] Specifically, the method for etching the Nitride in the groove in S5 is dry etching. Relevant technicians in this field should know that the purpose of this setting is to etch the Nitride formed in the groove. Therefore, in some embodiments, other etching methods can also be used to achieve this effect. For example, in some embodiments, the method for etching the Nitride in the groove in S5 can also be photolithography or chemical etching.

[0051] In an embodiment of the present invention, a new device structure method for reducing Cgd can be formed by forming a trench on the surface of the SIC epitaxial layer and growing a gate oxide film at the bottom and sidewalls of the trench, depositing a polysilicon film on the formed gate oxide film, etching the polysilicon film at the bottom of the trench, and depositing Nitride on the polysilicon film. Then, the trench Nitride is etched and an oxide layer is grown on the polysilicon from which the Nitride has been etched. The remaining Nitride is then removed and a layer of polysilicon is grown on this basis to form a new device structure method for reducing Cgd. This method can achieve the technical effects of avoiding excessive Cgd, slowing down the device switching rate, and reducing device loss.

[0052] A method for improving the switching speed of a trench SIC MOSFET device is applied in the manufacture of the SIC MOSFET device.

[0053] It should be noted that, in this document, relational terms such as A and B are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include," "comprise," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0054] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for improving the switching speed of a trench SIC MOSFET device, characterized in that: The following steps are involved: S1, forming a groove on the surface of the SIC epitaxial layer; S2, growing a gate oxide film on the bottom and sidewalls of the trench; S3, depositing a polysilicon film on the gate oxide film, and etching the polysilicon film at the bottom of the trench; S4, depositing nitride on the etched polysilicon film; S5, etching the nitride at the bottom of the trench; S6, growing an oxide layer at the bottom of the trench where the nitride is etched away; S7, removing the remaining nitride; S8, growing a layer of polysilicon in the trench after completing the operation of S7; Wherein, the thickness of the polysilicon film is 100~300 The thickness of the nitride deposited on the polysilicon film is 500~510 .

2. The method for improving the switching speed of a trench SIC MOSFET device according to claim 1, wherein: The thickness ratio of the polysilicon film to the nitride is 1:1.67 to 1:1.

5.

3. The method for improving the switching speed of a trench SIC MOSFET device according to claim 1, wherein: The conductivity type of the SIC epitaxial layer is N-type or P-type, which is the same as or different from that of the SIC wafer.

4. The method for improving the switching speed of a trench SIC MOSFET device according to claim 1, wherein: The method of etching the nitride in the trench in S5 is dry etching.

5. The method for improving the switching speed of a trench SIC MOSFET device according to claim 1, wherein: The trench is U-shaped as a whole, and the sidewall of the trench smoothly transitions to the surface of the SIC epitaxial layer.

6. Use of the method for improving the switching speed of a trench SIC MOSFET device according to any one of claims 1 to 5 in the manufacture of SIC MOSFET devices.

Images