Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate, the substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first active region, and the second surface comprising a second active region; a first transistor located on the first surface of the substrate, the first transistor comprising a first gate structure located on the substrate of the first active region, and a first source-drain doped region located in the first active region on both sides of the first gate structure; and a second transistor located on the second surface of the substrate, the second transistor comprising a second gate structure located on the substrate of the second active region, and a second source-drain doped region located in the second active region on both sides of the second gate structure. According to the embodiment of the present application, transistors are formed on both surfaces of the substrate, which is conducive to improving the density and integration of the transistors, and is also conducive to improving the diversity of the transistor types, so as to meet the diversified requirements of the devices and the performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, and the development of semiconductor process nodes follows Moore's Law, with the number of nodes continuously decreasing. Transistors, as the most basic semiconductor devices, are currently widely used.

[0003] However, the density and integration of transistors still need to be improved. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the density and integration of transistors.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate, the substrate including a first side and a second side facing away from each other, the first side including a first active region, and the second side including a second active region; a first transistor located on the first side of the substrate, the first transistor including a first gate structure located on the substrate in the first active region, and first source / drain doped regions located in the first active regions on both sides of the first gate structure; and a second transistor located on the second side of the substrate, the second transistor including a second gate structure located on the substrate in the second active region, and second source / drain doped regions located in the second active regions on both sides of the second gate structure.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first side and a second side facing away from each other, the first side including a first active region, and the second side including a second active region; forming a first transistor on the first side of the substrate, the first transistor including a first gate structure located on the substrate of the first active region, and a first source / drain doped region located in the first active regions on both sides of the first gate structure; and forming a second transistor on the second side of the substrate, the second transistor including a second gate structure located on the substrate of the second active region, and a second source / drain doped region located in the second active regions on both sides of the second gate structure.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] The semiconductor structure provided in this embodiment of the invention has a first transistor formed on a first surface of the substrate and a second transistor formed on a second surface of the substrate, so that transistors are formed on both surfaces of the substrate. This is beneficial for improving the density and integration of transistors, as well as for increasing the diversity of transistor types to meet the needs of device diversification and performance diversification.

[0009] In the semiconductor structure formation method provided by the embodiments of the present invention, a first transistor is formed on a first surface of the substrate, and a second transistor is formed on a second surface of the substrate, thereby forming transistors on both surfaces of the substrate. This is beneficial for improving the density and integration of transistors, as well as for increasing the diversity of transistor types to meet the needs of device diversification and performance diversification. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;

[0012] Figures 3 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] As can be seen from the background technology, the density and integration of current devices still need to be improved.

[0014] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure in which a first transistor is formed on a first surface of the substrate and a second transistor is formed on a second surface of the substrate, thereby forming transistors on both surfaces of the substrate. This is beneficial for increasing the density and integration of transistors, as well as for increasing the diversity of transistor types to meet the needs of device diversification and performance diversification.

[0015] To address the aforementioned technical problems, embodiments of the present invention also provide a method for forming a semiconductor structure, wherein a first transistor is formed on a first surface of the substrate and a second transistor is formed on a second surface of the substrate, thereby forming transistors on both surfaces of the substrate. This method is beneficial for increasing the density and integration of transistors, as well as for increasing the diversity of transistor types to meet the needs of device diversification and performance diversification.

[0016] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figure 1 A cross-sectional schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Specifically, Figure 1A schematic diagram of the cross-sectional structure along the direction perpendicular to the extension of the channel is shown.

[0017] like Figure 1 As shown, in this embodiment, the semiconductor structure includes: a substrate 10, which includes a first surface 101 and a second surface 102 facing away from each other. The first surface 101 includes a first active region 103, and the second surface 101 includes a second active region 104; a first transistor 100, located on the first surface 101 of the substrate 10, which includes a first gate structure 110 located on the substrate 10 in the first active region 103, and first source / drain doped regions (not shown) located in the first active regions 103 on both sides of the first gate structure 110; and a second transistor 200, located on the second surface 102 of the substrate 10, which includes a second gate structure 210 located on the substrate 10 in the second active region 104, and second source / drain doped regions (not shown) located in the second active regions 104 on both sides of the second gate structure 210.

[0018] Substrate 10 is used to provide a process platform for the formation of semiconductor structures.

[0019] In this embodiment, the material of the substrate 10 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. As an example, the material of the substrate 10 is single-crystal silicon.

[0020] The first surface 101 is opposite to the second surface 102.

[0021] The first surface 101 is used to provide a process platform for forming the first transistor 100; the second surface 102 is used to provide a process platform for forming the second transistor.

[0022] In one embodiment, the first surface 101 is the front side of the substrate 10, and the second surface 102 is the back side of the substrate 10. In other embodiments, the first surface may be the front side of the substrate, and the second surface may be the back side of the substrate.

[0023] The first surface 101 includes a first active region 103, which is used to define the formation region of the first transistor 100.

[0024] The second surface 102 includes a second active region 104, which defines the formation region of the second transistor 200.

[0025] The first transistor 100 is located on the first surface 101 of the substrate 10.

[0026] The first transistor 100 can be a transistor of various structural types. For example, the first transistor 100 includes: a planar transistor, a fin field-effect transistor, a fully enclosed gate transistor, or a fork gate transistor.

[0027] As one embodiment, the first transistor 100 is a FinFET. By employing a three-dimensional FinFET structure, the first gate structure 110 can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the first gate structure 110 has stronger channel control capability, can effectively suppress short-channel effects, and FinFETs have better compatibility with existing integrated circuit manufacturing.

[0028] Therefore, in this embodiment, the second active region 104 is a discrete fin. Specifically, multiple fins are discretely mounted on the first surface 101.

[0029] The first transistor 100 includes one or both of NMOS transistors and PMOS transistors.

[0030] For ease of illustration and explanation, this embodiment is illustrated by having two first transistors 100, which include a first NMOS transistor 100 (N) and a first PMOS transistor 100 (P).

[0031] In this embodiment, the semiconductor structure further includes a first isolation layer 120, which is located on the first surface 101 and surrounds the fin and covers a portion of the sidewall of the fin.

[0032] The first isolation layer 120 is used to achieve insulation between the first gate structure 110 and the substrate 10.

[0033] The material of the first insulating layer 120 is an electrically insulating material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0034] The first gate structure 110 is used to control the opening and closing of the conductive channel of the first transistor 100.

[0035] In this embodiment, the first gate structure 110 is located on the first isolation layer 120, and spans the fin and covers part of the top and part of the sidewall of the fin.

[0036] In this embodiment, the first gate structure 110 includes a first gate dielectric layer (not shown) and a first gate electrode layer (not shown) located on the first gate dielectric layer.

[0037] The first gate dielectric layer is used to achieve electrical isolation between the first gate electrode layer and the conductive channel.

[0038] The material of the first gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0039] The first gate electrode layer is used as an external electrode of the first gate structure 110.

[0040] The material of the first gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

[0041] In this embodiment, a first gate sidewall 130 is also formed on the sidewall of the first gate structure 110 to protect the sidewall of the first gate structure 110 and to define the formation location of the first source / drain doped region.

[0042] In this embodiment, the material of the first gate sidewall 130 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbon oxynitride, boron nitride, boron carbonitride, low-k materials, and ultra-low-k materials. The first gate sidewall 130 is a single-layer or multi-layer structure. As an example, the first gate sidewall 130 is a single-layer structure, and the material of the first gate sidewall 130 is silicon nitride.

[0043] The first source-drain doped region is used as the source or drain of the first transistor 100. When the first transistor 100 is working, the first source-drain doped region is used to provide a carrier source for the first transistor 100.

[0044] In this embodiment, the first source / drain doped region includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0045] Specifically, when the first transistor 100 is an NMOS transistor, the material of the first source-drain doped region is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0046] When the first transistor 100 is a PMOS transistor, the material of the first source-drain doped region is a stress layer doped with P-type ions. The material of the stress layer includes Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0047] A first interlayer dielectric layer 140 is also formed on the isolation layer 120 on the side of the first gate sidewall 130, covering the first source and drain doped region.

[0048] The first interlayer dielectric layer 140 is used to achieve electrical isolation between adjacent devices.

[0049] In this embodiment, the material of the first interlayer dielectric layer 140 is silicon oxide. The material of the first interlayer dielectric layer 140 can also be other insulating materials.

[0050] In this embodiment, the semiconductor structure further includes: a first source-drain interconnect structure (not shown), located on the first transistor 100 and electrically connected to the first source-drain doped region; and a first gate interconnect structure (not shown), located on the first transistor and electrically connected to the first gate structure.

[0051] The first source-drain interconnect structure is used to realize the electrical connection between the first source-drain doped region and the external circuit.

[0052] In this embodiment, the material of the first source-drain interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0053] The first gate interconnect structure is used to realize the electrical connection between the first gate structure 110 and the external circuit.

[0054] In this embodiment, the material of the first gate interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0055] The second transistor 200 is located on the second surface 102 of the substrate 10.

[0056] The second transistor 200 can be a transistor of various structural types. For example, the second transistor 100 includes: a planar transistor, a fin field-effect transistor, a fully enclosed gate transistor, or a fork gate transistor.

[0057] As one embodiment, the second transistor 200 is a planar transistor.

[0058] Therefore, in this embodiment, the second surface 102 of the substrate 10 is formed with a plurality of isolation trenches (not shown), and the substrate 10 between the isolation trenches is the second active region 104.

[0059] In this embodiment, a second isolation layer 220 is also formed within the isolation trench. The second isolation layer 220 is used to achieve isolation between the second active regions 104.

[0060] The material of the second isolation layer 220 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0061] The second transistor 200 includes one or both of NMOS transistors and PMOS transistors.

[0062] For ease of illustration and explanation, this embodiment uses two second transistors 200 as an example. The second transistor 200 includes a second NMOS transistor 200(N) and a second PMOS transistor 200(P).

[0063] The channel conductivity type of the second transistor 200 and the channel conductivity type of the first transistor 100 may be the same or different.

[0064] The second gate structure 210 is used to control the opening and closing of the conductive channel of the second transistor 200.

[0065] In this embodiment, the second gate structure 210 is located on the second surface 102 and the second isolation layer 220 of the substrate 10.

[0066] In this embodiment, the second gate structure 210 includes a first gate dielectric layer (not shown) and a second gate electrode layer (not shown) located on the second gate dielectric layer.

[0067] The second gate dielectric layer is used to achieve electrical isolation between the second gate electrode layer and the conductive channel.

[0068] The material of the second gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0069] The second gate electrode layer is used as an external electrode of the second gate structure 210.

[0070] The material of the second gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0071] In this embodiment, a second gate sidewall 230 is also formed on the sidewall of the second gate structure 210 to protect the sidewall of the second gate structure 210 and to define the formation location of the second source / drain doped region.

[0072] In this embodiment, the material of the second gate sidewall 230 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbon oxynitride, boron nitride, boron carbonitride, low-k materials, and ultra-low-k materials. The second gate sidewall 230 is a single-layer or multi-layer structure. As an example, the second gate sidewall 230 is a single-layer structure, and the material of the second gate sidewall 230 is silicon nitride.

[0073] The second source-drain doped region is used as the source or drain of the second transistor 200. When the second transistor 200 is working, the second source-drain doped region is used to provide a carrier source for the second transistor 200.

[0074] In this embodiment, the second source / drain doped region includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0075] Specifically, when the second transistor 200 is an NMOS transistor, the material of the second source / drain doped region is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0076] When the second transistor 200 is a PMOS transistor, the material of the second source / drain doped region is a stress layer doped with P-type ions. The material of the stress layer includes Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0077] In this embodiment, a second interlayer dielectric layer 240 is also formed on the isolation layer 120 on the side of the second gate sidewall 230 and on the second surface 102, covering the second source / drain doped region.

[0078] The second interlayer dielectric layer 240 is used to achieve electrical isolation between adjacent devices.

[0079] In this embodiment, the material of the second interlayer dielectric layer 240 is silicon oxide. The material of the second interlayer dielectric layer 240 can also be other insulating materials.

[0080] In this embodiment, the semiconductor structure further includes: a second source-drain interconnect structure (not shown), located on the second transistor 200 and electrically connected to the second source-drain doped region; and a second gate interconnect structure (not shown), located on the second transistor 200 and electrically connected to the second gate structure.

[0081] The second source-drain interconnect structure is used to realize the electrical connection between the second source-drain doped region and the external circuit.

[0082] In this embodiment, the material of the second source-drain interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0083] The second gate interconnect structure is used to realize the electrical connection between the second gate structure 110 and the external circuit.

[0084] In this embodiment, the material of the second gate interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0085] Figure 2 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. The similarities between the semiconductor structure of this embodiment and the previous embodiment will not be repeated here. The difference between this embodiment and the previous embodiment is that the semiconductor structure further includes: a through-hole (not shown), located between the first transistor 100 and the second transistor 200; and a through-hole interconnect structure 250, located within the through-hole and connecting the first transistor 100 and the second transistor 200.

[0086] The vias (not shown) are used to provide spatial location for the via interconnect structure 250.

[0087] The through-hole interconnect structure 250 is used to electrically connect the first transistor 100 and the second transistor 200.

[0088] In this embodiment, the through-hole interconnect structure 250 is a through-silicon via (TSV) interconnect structure.

[0089] The material of the through-hole interconnect structure 250 is a conductive material. In this embodiment, the material of the through-hole interconnect structure 250 includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0090] As one embodiment, the via interconnect structure 250 penetrates the first isolation layer 120, the substrate 10, and the second isolation layer 220 located between the first gate structure 110 and the second gate structure 210, and the via interconnect structure 250 is in contact with the first gate structure 110 and the second gate structure 210 respectively.

[0091] Accordingly, in this embodiment, the through-hole interconnect structure 250 is used to electrically connect the first gate structure 110 and the second gate structure 210.

[0092] In this embodiment, the example of the through-hole interconnect structure 250 electrically connecting the first gate structure 110 and the second gate structure 210 is used for illustration. In other embodiments, based on actual process requirements, the through-hole interconnect structure can also electrically connect other components corresponding to the first transistor and the second transistor to achieve electrical connection between the first transistor and the second transistor.

[0093] In this embodiment, the electrical connection between the first transistor 100 and the second transistor 200 via a via interconnect structure 250 is used as an example for illustration.

[0094] In other embodiments, the via interconnect structure may be omitted from the semiconductor structure, and the first transistor and the second transistor may be electrically connected in other ways. That is, the first transistor and the second transistor do not need to be connected through a via interconnect structure; the first transistor and the second transistor are connected externally. For example, in a specific implementation, the first transistor and the second transistor can be electrically connected through wiring on a circuit board (PCB).

[0095] In other embodiments, based on actual process requirements, the first transistor and the second transistor may not need to be electrically connected.

[0096] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0097] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0098] refer to Figure 3 A substrate 10 is provided, the substrate 10 including a first surface 101 and a second surface 102 opposite to each other, the first surface 101 including a first active region 103, and the second surface 102 including a second active region 104.

[0099] Substrate 10 is used to provide a process platform for forming semiconductor structures.

[0100] In this embodiment, the material of the substrate 10 includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. As an example, the material of the substrate 10 is single-crystal silicon.

[0101] The first surface 101 is opposite to the second surface 102.

[0102] The first surface 101 is used to provide a process platform for the subsequent formation of the first transistor; the second surface 102 is used to provide a process platform for the subsequent formation of the second transistor.

[0103] In one embodiment, the first surface 101 is the front side of the substrate 10, and the second surface 102 is the back side of the substrate 10. In other embodiments, the first surface may be the front side of the substrate, and the second surface may be the back side of the substrate.

[0104] The first surface 101 includes a first active region 103, which is used to define the formation region of the first transistor.

[0105] As one embodiment, the first transistor subsequently formed on the first surface 101 is a FinFET. Therefore, in this embodiment, the second active region 104 is a discrete fin. Specifically, multiple fins are discretely disposed on the first surface 101.

[0106] The second surface 102 includes a second active region 104, which is used to define the formation region of the second transistor.

[0107] Continue to refer to Figure 3 A first transistor 100 is formed on the first surface 101 of the substrate 10. The first transistor 100 includes a first gate structure 110 located on the substrate 10 in the first active region 103, and first source / drain doped regions (not shown) located in the first active regions 103 on both sides of the first gate structure 110.

[0108] The first transistor 100 can be a transistor of various structural types. For example, the first transistor 100 includes: a planar transistor, a fin field-effect transistor, a fully enclosed gate transistor, or a fork gate transistor.

[0109] As one embodiment, the first transistor 100 is a FinFET. By employing a three-dimensional FinFET structure, the first gate structure 110 can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the first gate structure 110 has stronger channel control capability, can effectively suppress short-channel effects, and has better compatibility with existing integrated circuit manufacturing processes.

[0110] The first transistor 100 includes one or both of NMOS transistors and PMOS transistors.

[0111] For ease of illustration and explanation, this embodiment uses two first transistors 100 as an example. The first transistor 100 includes a first NMOS transistor 100(N) and a first PMOS transistor 100(P).

[0112] In this embodiment, a first isolation layer 120 is also formed on the first surface 101, surrounding the fin and covering part of the sidewall of the fin.

[0113] The first isolation layer 120 is used to achieve insulation between the first gate structure 110 and the substrate 10.

[0114] The material of the first insulating layer 120 is an electrically insulating material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0115] The first gate structure 110 is used to control the opening and closing of the conductive channel of the first transistor 100.

[0116] In this embodiment, the first gate structure 110 is located on the first isolation layer 120, and spans the fin and covers part of the top and part of the sidewall of the fin.

[0117] In this embodiment, the first gate structure 110 includes a first gate dielectric layer (not shown) and a first gate electrode layer (not shown) located on the first gate dielectric layer.

[0118] The first gate dielectric layer is used to achieve electrical isolation between the first gate electrode layer and the conductive channel.

[0119] The material of the first gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0120] The first gate electrode layer is used as an external electrode of the first gate structure 110.

[0121] The material of the first gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

[0122] In this embodiment, a first gate sidewall 130 is also formed on the sidewall of the first gate structure 110 to protect the sidewall of the first gate structure 110 and to define the formation location of the first source / drain doped region.

[0123] In this embodiment, the material of the first gate sidewall 130 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbon oxynitride, boron nitride, boron carbonitride, low-k materials, and ultra-low-k materials. The first gate sidewall 130 is a single-layer or multi-layer structure. As an example, the first gate sidewall 130 is a single-layer structure, and the material of the first gate sidewall 130 is silicon nitride.

[0124] The first source-drain doped region is used as the source or drain of the first transistor 100. When the first transistor 100 is working, the first source-drain doped region is used to provide a carrier source for the first transistor 100.

[0125] In this embodiment, the first source / drain doped region includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0126] Specifically, when the first transistor 100 is an NMOS transistor, the material of the first source-drain doped region is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0127] When the first transistor 100 is a PMOS transistor, the material of the first source-drain doped region is a stress layer doped with P-type ions. The material of the stress layer includes Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0128] A first interlayer dielectric layer 140 is also formed on the isolation layer 120 on the side of the first gate sidewall 130, covering the first source and drain doped region.

[0129] The first interlayer dielectric layer 140 is used to achieve electrical isolation between adjacent devices.

[0130] In this embodiment, the material of the first interlayer dielectric layer 140 is silicon oxide. The material of the first interlayer dielectric layer 140 can also be other insulating materials.

[0131] refer to Figure 4 The first surface 101 of the substrate 10 is bonded to the carrier wafer 20.

[0132] The first surface 101 is bonded to the carrier wafer 20, thereby flipping the second surface 102 upward so that the second surface 102 can be used as the process operation surface, and then the second transistor can be formed on the second surface 102. At the same time, the carrier wafer 20 can provide support for the substrate 10.

[0133] As an example, after forming a first transistor 100 on a first surface 101 of the substrate 10, the first surface 101 of the substrate 10 is bonded to a carrier wafer 20 so that a second transistor can be subsequently formed on a second surface 102 of the substrate 10.

[0134] Specifically, in this embodiment, the top surface of the first transistor 100 on the first surface 101 of the substrate 10 is bonded to the carrier wafer 20.

[0135] In this embodiment, the bonding layer 150 is used to achieve the bonding between the first surface 101 of the substrate 10 and the carrier wafer 20.

[0136] More specifically, in this embodiment, the bonding between the first surface 101 of the substrate 10 and the carrier wafer is achieved by glass bonding, and correspondingly, the material of the bonding layer 150 is glass.

[0137] In other embodiments, other suitable bonding processes can be used to achieve bonding between the first surface and the carrier wafer, such as anodic bonding, eutectic bonding, etc.

[0138] It should be noted that the reference Figure 5 In this embodiment, the method for forming the semiconductor structure further includes: thinning the second surface 102 of the substrate 10.

[0139] The second surface 102 is thinned to reduce the thickness of the substrate 10, which in turn helps to reduce the thickness of the device and facilitates the miniaturization and micro-miniaturization of the device.

[0140] Specifically, a grinding process can be used to thin the second surface 102.

[0141] refer to Figure 6 A second transistor 200 is formed on the second surface 102 of the substrate 10. The second transistor 200 includes a second gate structure 210 located on the substrate 10 of the second active region 104, and second source / drain doped regions (not shown) located in the second active regions 104 on both sides of the second gate structure 210.

[0142] The second transistor 200 can be a transistor of various structural types. For example, the second transistor 100 includes: a planar transistor, a fin field-effect transistor, a fully enclosed gate transistor, or a fork gate transistor.

[0143] As one embodiment, the second transistor 200 is a planar transistor.

[0144] Therefore, in this embodiment, the second surface 102 of the substrate 10 is formed with a plurality of isolation trenches (not shown), and the substrate 10 between the isolation trenches is the second active region 104.

[0145] In this embodiment, a second isolation layer 220 is also formed within the isolation trench. The second isolation layer 220 is used to achieve isolation between the second active regions 104, thereby achieving isolation between adjacent second transistors.

[0146] The material of the second isolation layer 220 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0147] The second transistor 200 includes one or both of NMOS transistors and PMOS transistors.

[0148] For ease of illustration and explanation, this embodiment uses two second transistors 200 as an example. The second transistor 200 includes a second NMOS transistor 200(N) and a second PMOS transistor 200(P).

[0149] The channel conductivity type of the second transistor 200 and the channel conductivity type of the first transistor 100 may be the same or different.

[0150] The second gate structure 210 is used to control the opening and closing of the conductive channel of the second transistor 200.

[0151] In this embodiment, the second gate structure 210 is located on the second surface 102 of the substrate 10 and the second isolation layer 220.

[0152] In this embodiment, the second gate structure 210 includes a first gate dielectric layer (not shown) and a second gate electrode layer (not shown) located on the second gate dielectric layer.

[0153] The second gate dielectric layer is used to achieve electrical isolation between the second gate electrode layer and the conductive channel.

[0154] The material of the second gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide.

[0155] The second gate electrode layer is used as an external electrode of the second gate structure 210.

[0156] The material of the second gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0157] In this embodiment, a second gate sidewall 230 is also formed on the sidewall of the second gate structure 210 to protect the sidewall of the second gate structure 210 and to define the formation location of the second source / drain doped region.

[0158] In this embodiment, the material of the second gate sidewall 230 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbon oxynitride, boron nitride, boron carbonitride, low-k materials, and ultra-low-k materials. The second gate sidewall 230 is a single-layer or multi-layer structure. As an example, the second gate sidewall 230 is a single-layer structure, and the material of the second gate sidewall 230 is silicon nitride.

[0159] The second source-drain doped region is used as the source or drain of the second transistor 200. When the second transistor 200 is working, the second source-drain doped region is used to provide a carrier source for the second transistor 200.

[0160] In this embodiment, the second source / drain doped region includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0161] Specifically, when the second transistor 200 is an NMOS transistor, the material of the second source / drain doped region is a stress layer doped with N-type ions. The material of the stress layer includes Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0162] When the second transistor 200 is a PMOS transistor, the material of the second source / drain doped region is a stress layer doped with P-type ions. The material of the stress layer includes Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0163] In this embodiment, a second interlayer dielectric layer 240 is also formed on the isolation layer 120 on the side of the second gate sidewall 230 and on the second surface 102, covering the second source / drain doped region.

[0164] The second interlayer dielectric layer 240 is used to achieve electrical isolation between adjacent devices.

[0165] In this embodiment, the material of the second interlayer dielectric layer 240 is silicon oxide. The material of the second interlayer dielectric layer 240 can also be other insulating materials.

[0166] In this embodiment, the step of forming the second transistor 200 includes: forming an isolation trench (not shown) in the substrate 10 between the second active regions 104; forming a second isolation layer 220 in the isolation trench; forming a second gate structure 210 on the second active regions 104; forming second source / drain doped regions in the second active regions 104 on both sides of the second gate structure 210; and forming a second interlayer dielectric layer 240 on the active regions 104 and the second isolation layer 220 on the side of the second gate structure 210.

[0167] It should be noted that in this embodiment, the formation of the second transistor 200 on the second surface 102 of the substrate 10 after the formation of the first transistor 100 on the first surface 101 of the substrate 10 is used as an example for illustration. In other embodiments, the first transistor may be formed on the first surface of the substrate after the formation of the second transistor.

[0168] refer to Figure 7 In this embodiment, the method for forming the semiconductor structure further includes: forming a via interconnect structure 250 located between the first transistor 100 and the second transistor 200, wherein the via interconnect structure 250 connects the first transistor 100 and the second transistor 200.

[0169] The through-hole interconnect structure 250 is used to electrically connect the first transistor 100 and the second transistor 200.

[0170] In this embodiment, the through-hole interconnect structure 250 is a through-silicon via (TSV) interconnect structure.

[0171] The material of the through-hole interconnect structure 250 is a conductive material. In this embodiment, the material of the through-hole interconnect structure 250 includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0172] Specifically, in this embodiment, a via (not shown) is formed between the first transistor 100 and the second transistor 200; a via interconnect structure 250 is formed in the via, and the via interconnect structure 250 connects the first transistor and the second transistor.

[0173] As one embodiment, a via interconnect structure 250 is formed that penetrates the first isolation layer 120, the substrate 10, and the second isolation layer 220 located between the first gate structure 110 and the second gate structure 210, and the via interconnect structure 250 is in contact with the first gate structure 110 and the second gate structure 210.

[0174] Accordingly, in this embodiment, the through-hole interconnect structure 250 is used to electrically connect the first gate structure 110 and the second gate structure 210.

[0175] In this embodiment, the example of the through-hole interconnect structure 250 electrically connecting the first gate structure 110 and the second gate structure 210 is used for illustration. In other embodiments, based on actual process requirements, the through-hole interconnect structure can also electrically connect other components corresponding to the first transistor and the second transistor to achieve electrical connection between the first transistor and the second transistor.

[0176] In this embodiment, the electrical connection between the first transistor 100 and the second transistor 200 via a via interconnect structure 250 is used as an example for illustration.

[0177] In other embodiments, the via interconnect structure may be omitted from the semiconductor structure, and the first transistor and the second transistor may be electrically connected in other ways. That is, the first transistor and the second transistor do not need to be connected through a via interconnect structure; the first transistor and the second transistor are connected externally. For example, in a specific implementation, the first transistor and the second transistor can be electrically connected through wiring on a circuit board (PCB).

[0178] In other embodiments, based on actual process requirements, the first transistor and the second transistor may not need to be electrically connected.

[0179] refer to Figure 8 In this embodiment, the method for forming the semiconductor structure further includes: removing the carrier wafer 20 after forming the second transistor 200.

[0180] Specifically, the carrier wafer 20 is removed through a debonding process.

[0181] It should be noted that, in this embodiment, the method for forming the semiconductor structure further includes: after forming the first transistor 100, forming a first source-drain interconnect structure (not shown) and a first gate interconnect structure (not shown) on the first transistor 100, wherein the first source-drain interconnect structure is electrically connected to the first source-drain doped region, and the first gate interconnect structure is electrically connected to the first gate structure 110.

[0182] The first source-drain interconnect structure is used to realize the electrical connection between the first source-drain doped region and the external circuit.

[0183] In this embodiment, the material of the first source-drain interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0184] The first gate interconnect structure is used to realize the electrical connection between the first gate structure 110 and the external circuit.

[0185] In this embodiment, the material of the first gate interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0186] It should be noted that, in this embodiment, the method for forming the semiconductor structure further includes: after forming the second transistor 200, forming a second source-drain interconnect structure (not shown) and a second gate interconnect structure (not shown) on the second transistor 200, wherein the second source-drain interconnect structure is electrically connected to the second source-drain doped region, and the second gate interconnect structure is electrically connected to the second gate structure 210.

[0187] The second source-drain interconnect structure is used to realize the electrical connection between the second source-drain doped region and the external circuit.

[0188] In this embodiment, the material of the second source-drain interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0189] The second gate interconnect structure is used to realize the electrical connection between the second gate structure 110 and the external circuit.

[0190] In this embodiment, the material of the second gate interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

[0191] It should be noted that, in specific implementations, the first source-drain interconnect structure and the first gate interconnect structure can be formed after the second source-drain interconnect structure and the second gate interconnect structure are formed.

[0192] Alternatively, the second source-drain interconnect structure and the second gate interconnect structure may be formed after the first source-drain interconnect structure and the first gate interconnect structure are formed. Specifically, the first source-drain interconnect structure and the first gate interconnect structure may be formed after the first transistor is formed and before the second transistor is formed.

[0193] After forming the first transistor and the second transistor, a first source-drain interconnect structure and a first gate interconnect structure are formed, and a second source-drain interconnect structure and a second gate interconnect structure are formed.

[0194] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first surface and a second surface facing away from each other, the first surface including a first active region and the second surface including a second active region; A first transistor is located on a first surface of the substrate. The first transistor includes a first gate structure located on the substrate of a first active region and a first source / drain doped region located in the first active region on both sides of the first gate structure. The second transistor is located on the second surface of the substrate. The second transistor includes a second gate structure located on the substrate of the second active region, and a second source / drain doped region located in the second active region on both sides of the second gate structure. A first isolation layer, located on a first surface of the substrate, is used to achieve insulation between the first gate structure and the substrate; The second isolation layer is located on the second surface of the substrate and is used to achieve isolation between the second active regions. The second gate structure is located on the second surface of the substrate and the second isolation layer. The via interconnect structure penetrates the first isolation layer, the substrate, and the second isolation layer located between the first gate structure and the second gate structure, and is in contact with the first gate structure and the second gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a via located between the first transistor and the second transistor; and a via interconnect structure located within the via and connecting the first transistor and the second transistor. Alternatively, the first transistor and the second transistor are connected externally.

3. The semiconductor structure as described in claim 1, characterized in that, The first transistor includes: a planar transistor, a fin field-effect transistor, a fully enclosed gate transistor, or a fork gate transistor; The second transistor includes: a planar transistor, a fin field-effect transistor, a fully enclosed gate transistor, or a fork gate transistor.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a first source-drain interconnect structure located on the first transistor and electrically connected to the first source-drain doped region; and a first gate interconnect structure located on the first transistor and electrically connected to the first gate structure. The second source-drain interconnect structure is located on the second transistor and electrically connected to the second source-drain doped region; the second gate interconnect structure is located on the second transistor and electrically connected to the second gate structure.

5. The semiconductor structure as described in claim 4, characterized in that, The material of the first source-drain interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN; The material of the first gate interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN; The material of the second source-drain interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN; The material of the second gate interconnect structure includes one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

6. The semiconductor structure as described in claim 1, characterized in that, The substrate material includes one or more of the following: single-crystal silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride; The material of the first source / drain doped region includes one or more of Si, SiC, and SiGe; The material of the second source / drain doped region includes one or more of Si, SiC, and SiGe.

7. The semiconductor structure as described in claim 1, characterized in that, The materials for the via interconnect structure include one or more of the following: Co, W, Ru, Al, Ir, Rh, Os, Pd, Cu, Pt, Ni, Ta, TaN, Ti, and TiN.

8. The semiconductor structure as described in claim 1, characterized in that, The first gate structure includes a first gate dielectric layer and a first gate electrode layer located on the first gate dielectric layer; The second gate structure includes a second gate dielectric layer and a second gate electrode layer located on the second gate dielectric layer.

9. The semiconductor structure as described in claim 8, characterized in that, The material of the first gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide; The material of the first gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni; The material of the second gate dielectric layer includes one or more of the following: HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, Al2O3, silicon oxide, and nitrogen-doped silicon oxide; The material of the second gate electrode layer includes any one or more of TiAl, TiALC, TaAlN, TiAlN, MoN, TaCN, AlN, Ta, TiN, TaN, TaSiN, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

10. The semiconductor structure as claimed in claim 1, characterized in that, The first transistor includes one or both of NMOS transistors and PMOS transistors; the second transistor includes one or both of NMOS transistors and PMOS transistors. The channel conductivity type of the first transistor and the channel conductivity type of the second transistor may be the same or different.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first surface and a second surface opposite to each other, the first surface including a first active region and the second surface including a second active region; A first transistor is formed on a first surface of the substrate. The first transistor includes a first gate structure located on the substrate of a first active region and first source / drain doped regions located in the first active regions on both sides of the first gate structure. A first isolation layer is formed on the first surface of the substrate to achieve insulation between the first gate structure and the substrate; A second transistor is formed on the second surface of the substrate. The second transistor includes a second gate structure located on the substrate of the second active region, and second source / drain doped regions located in the second active regions on both sides of the second gate structure. A second isolation layer is formed on the second surface of the substrate to achieve isolation between the second active regions, and the second gate structure is located on the second surface of the substrate and the second isolation layer; A through-hole interconnect structure is formed, which penetrates the first isolation layer, the substrate, and the second isolation layer between the first gate structure and the second gate structure and is in contact with the first gate structure and the second gate structure.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The via interconnect structure is formed between the first transistor and the second transistor, and the via interconnect structure connects the first transistor and the second transistor.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The first side is the front side, and the second side is the back side; after the first transistor is formed on the front side of the substrate, the second transistor is formed on the back side of the substrate.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the first transistor and before forming the second transistor, the method for forming the semiconductor structure further includes bonding a first side of the substrate to a carrier wafer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method for forming the semiconductor structure further includes removing the carrier wafer after forming the second transistor.

16. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming a first transistor on a first surface of the substrate, a second transistor is formed on a second surface of the substrate; The method for forming the semiconductor structure further includes: after forming a first transistor on a first surface of the substrate and before forming a second transistor on a second surface of the substrate, thinning the second surface of the substrate.

17. The method for forming a semiconductor structure as described in claim 11, characterized in that, The first transistor includes: a planar transistor, a fin field-effect transistor, a fully enclosed gate transistor, or a fork-type gate transistor; The second transistor includes: a planar transistor, a fin field-effect transistor, a fully enclosed gate transistor, or a fork-type gate transistor.

18. The method for forming a semiconductor structure as described in claim 11, characterized in that, The number of the first transistors is one or more, and the first transistors include one or both of NMOS transistors and PMOS transistors; the number of the second transistors is one or more, and the second transistors include one or both of NMOS transistors and PMOS transistors. The channel conductivity type of the first transistor and the channel conductivity type of the second transistor may be the same or different.

19. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the semiconductor structure further includes: after forming the first transistor, forming a first source-drain interconnect structure and a first gate interconnect structure on the first transistor, wherein the first source-drain interconnect structure is electrically connected to the first source-drain doped region, and the first gate interconnect structure is electrically connected to the first gate structure. After the second transistor is formed, a second source-drain interconnect structure and a second gate interconnect structure are formed on the second transistor. The second source-drain interconnect structure is electrically connected to the second source-drain doped region, and the second gate interconnect structure is electrically connected to the second gate structure.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, After forming the first transistor and the second transistor, a first source-drain interconnect structure and a first gate interconnect structure are formed, and a second source-drain interconnect structure and a second gate interconnect structure are formed.

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