Package substrate, package chip, electronic device and chip packaging method

Abstract

The packaging substrate, packaging chip and electronic device provided by the embodiments of the present application relate to the field of chip packaging technology. In the packaging substrate, a groove is provided on the packaging substrate, the bottom wall of the packaging substrate corresponding to the groove is formed as the substrate bottom layer, the side wall of the packaging substrate corresponding to the groove is formed as a retaining wall, and one of the retaining walls on the two opposite sides of the groove is provided with an introduction structure facing the groove. The above design only requires transferring the chip die to the groove of the packaging substrate, and there is no need to have too high requirements on the transfer position accuracy. During packaging, the packaging glue generates a lateral thrust on the chip die from one side of the introduction structure during the glue pressing, so that the chip die moves toward the side where the introduction structure is not provided. In this way, the chip die package can be fixed at a relatively fixed position in the groove, thereby improving the packaging position accuracy of the chip die, thereby achieving the purpose of improving the yield of embedded packaging.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a packaging substrate, a packaging chip, an electronic device, and a chip packaging method. Background Art

[0002] Chip packaging is a back-end processing technology for semiconductor chips, providing physical protection, signal interconnection, heat dissipation, and fixation for the chip core structure (chip die). As semiconductors enter the post-Moore era, advanced packaging technology is becoming increasingly important for chip dies. Embedded packaging, one of the many advanced chip packaging technologies, has attracted attention due to its excellent chip die protection and simple process. However, the yield rate of embedded packaging is not ideal, which has also limited the widespread promotion of embedded packaging technology. Improving the yield rate of embedded packaging has become a technical problem that technicians in this field urgently need to solve. Summary of the Invention

[0003] In order to overcome the technical problems mentioned in the above technical background, the embodiments of the present application provide a packaging substrate, a packaging chip, an electronic device and a chip packaging method.

[0004] In a first aspect of the present application, a packaging substrate is provided, wherein the packaging substrate is provided with a groove, wherein a bottom wall of the packaging substrate corresponding to the groove is formed as a substrate bottom layer, and a side wall of the packaging substrate corresponding to the groove is formed as a retaining wall;

[0005] Among the retaining walls located on opposite sides of the groove, only one retaining wall is provided with an introduction structure facing the groove.

[0006] In a possible embodiment of the present application, the orthographic projection of the groove on the bottom layer of the substrate is a rectangle, and at least one of the retaining walls located on two adjacent sides of the groove is provided with a guide structure facing the groove;

[0007] Preferably, the retaining walls located on both adjacent sides of the groove are provided with an introduction structure toward the groove;

[0008] Preferably, the introduction structures provided on the retaining walls on both sides of the groove are identical;

[0009] Preferably, the lead-in structure comprises a chamfer.

[0010] In a possible embodiment of the present application, there are multiple grooves;

[0011] The introduction structure is located on different sides of different grooves; or,

[0012] The introduction structure is located on the same side of different grooves;

[0013] Preferably, the introduction structures on the retaining walls of different grooves are the same.

[0014] In a possible embodiment of the present application, in a direction perpendicular to the bottom layer of the substrate, a size of the introduction structure is smaller than a depth of the groove;

[0015] Preferably, the size of the lead-in structure is between 30% and 70% of the depth of the groove.

[0016] In a possible embodiment of the present application, the introduction structure includes rounded corners and / or chamfered corners;

[0017] Preferably, the introduction structure is a chamfered angle;

[0018] Preferably, the sidewall of the groove is perpendicular to the bottom layer of the substrate;

[0019] Preferably, the bottom layer of the substrate and the retaining wall are an integrally formed structure.

[0020] In a second aspect of the present application, a packaged chip is further provided, the packaged chip comprising a packaging substrate, a chip die, and a packaging layer;

[0021] The packaging substrate is provided with a groove, the bottom wall of the packaging substrate corresponding to the groove is formed as a substrate bottom layer, and the side walls of the packaging substrate corresponding to the groove are formed as retaining walls;

[0022] Among the retaining walls located on opposite sides of the groove, only one retaining wall is provided with an introduction structure toward the groove;

[0023] The bare chip is arranged in the groove;

[0024] The packaging layer is located on the packaging substrate and fills a gap between the chip die and the groove, wherein the chip die is close to a retaining wall where the introduction structure is not provided.

[0025] In a possible embodiment of the present application, the orthographic projection of the groove on the bottom layer of the substrate is a rectangle, and at least one of the retaining walls located on two adjacent sides of the groove is provided with a guide structure facing the groove;

[0026] Preferably, the retaining walls located on both adjacent sides of the groove are provided with an introduction structure toward the groove;

[0027] Preferably, the introduction structures provided on the retaining walls on both sides of the groove are identical;

[0028] Preferably, the lead-in structure comprises a chamfer.

[0029] In a possible embodiment of the present application, in a direction perpendicular to the bottom layer of the substrate, the size of the introduction structure is smaller than the depth of the groove, and the height of the chip die is greater than the depth of the groove;

[0030] Preferably, the size of the lead-in structure is between 30% and 70% of the depth of the groove, and the depth of the groove is between 10% and 90% of the height of the chip die.

[0031] Preferably, the sidewall of the groove is perpendicular to the bottom layer of the substrate, and in the direction perpendicular to the sidewall of the groove, the width of the groove is greater than the width of the chip bare particle, the size of the introduction structure is greater than the difference between the width of the groove and the width of the chip bare particle, and the size of the introduction structure is less than five times the difference.

[0032] A third aspect of the present application provides an electronic device, comprising the packaged chip in any possible embodiment of the second aspect.

[0033] A fourth aspect of the present application provides a chip packaging method, the chip packaging method comprising:

[0034] Providing a packaging substrate in any possible embodiment of the first aspect;

[0035] Transferring the bare chip into the groove of the packaging substrate;

[0036] forming an encapsulation layer, wherein, during the process of forming the encapsulation layer, the encapsulation glue generates a lateral thrust on the chip die from one side of the lead-in structure during lamination, causing the chip die to move toward a side where the lead-in structure is not provided;

[0037] Preferably, the step of encapsulating the layer includes:

[0038] Applying packaging glue at a position close to the lead-in structure in the packaging substrate;

[0039] The packaging adhesive is subjected to a pressing process using a pressing plate to produce the packaging layer.

[0040] The embodiments of the present application provide a packaging substrate, a packaging chip, an electronic device, and a chip packaging method. In the packaging substrate, a groove is provided on the packaging substrate, the bottom wall of the packaging substrate corresponding to the groove forms a substrate bottom layer, the side walls of the packaging substrate corresponding to the groove form retaining walls, and only one retaining wall on the two opposite sides of the groove is provided with an introduction structure facing the groove. The above design only requires transferring the chip die to the groove of the packaging substrate, and there is no need to have excessively high requirements for the transfer position accuracy. During packaging, the packaging glue generates a lateral thrust on the chip die from one side of the introduction structure during the glue pressing, so that the chip die moves toward the side where the introduction structure is not provided. In this way, the chip die package can be fixed at a relatively fixed position in the groove, thereby improving the packaging position accuracy of the chip die, thereby achieving the purpose of improving the yield rate of embedded packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A schematic diagram of transferring a bare chip in an embedded package in the prior art;

[0043] Figure 2 A schematic diagram of the film layer structure of the packaging substrate provided in the first embodiment;

[0044] Figure 3 A top view of the package substrate provided in the first embodiment;

[0045] Figure 4 A second top view of the package substrate provided in the first embodiment;

[0046] Figure 5 A third top view of the package substrate provided in the first embodiment;

[0047] Figure 6 A fourth top view of the package substrate provided in the first embodiment;

[0048] Figure 7 A fifth top view of the package substrate provided in the first embodiment;

[0049] Figure 8 A sixth top view of the package substrate provided in the first embodiment;

[0050] Figure 9 for Figure 2 Dimensioning diagram of

[0051] Figure 10 A schematic diagram of the film layer structure of the packaged chip provided in the second embodiment;

[0052] Figure 11 for Figure 10 One of the dimensioning diagrams;

[0053] Figure 12 for Figure 10 Dimensioning diagram 2;

[0054] Figure 13 A schematic flow chart of the steps of the chip packaging method provided in the second embodiment;

[0055] Figure 14 for Figure 13 Corresponding process flow chart;

[0056] Figure 15 for Figure 13 A possible process flow chart corresponding to step S13.

[0057] Icon: 1-packaged chip; 10-packaged substrate; 110-substrate bottom layer; 120-retaining wall; 1201-introduction structure; 130-groove; 20-bare chip; 30-package layer; 40-bonding layer. DETAILED DESCRIPTION

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0059] In the description of this application, it should be noted that the terms "upper" and "lower" etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. These are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0060] After analyzing the technical problems mentioned in the background technology, the inventors found that the main reason for the poor embedded packaging is the uncertainty of the packaging fixed position of the chip die in the groove. The main reasons for the uncertainty of the packaging fixed position of the chip die in the groove are two aspects. The first is that there is a position deviation when the chip die is transferred to the groove of the packaging substrate. The other is that the packaging material acts on the chip die during the packaging process, which will cause the chip die to move to a certain extent.

[0061] In order to reduce the position movement of the chip during the subsequent packaging process, please refer to Figure 1 In the prior art, a die attach film (DAF) 40 can be added to one side of the die 20 to secure the die 20 in the groove 130 of the package substrate 10. However, this method places high demands on the alignment accuracy during the transfer of the die 20 to the package substrate 10, which can easily lead to transfer position errors, thereby still resulting in poor yield of the packaging process and poor heat dissipation of the final product.

[0062] In order to solve the above technical problems, the inventors have innovatively designed the following technical solutions, which will be described in detail below with reference to the accompanying drawings.

[0063] It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned technical problems and the solutions proposed in the embodiments of this application below for the above-mentioned problems should all be the contributions made by the inventor to this application in the process of invention and creation, and should not be understood as technical contents known to technical personnel in this field.

[0064] First embodiment

[0065] Please refer to Figure 2 , Figure 2 The following diagram illustrates the film layer structure of the package substrate provided in this embodiment. In this embodiment, the package substrate 10 includes a substrate bottom layer 110 and a retaining wall 120. The package substrate 10 defines a groove 130. The bottom wall of the package substrate 10 corresponding to the groove 130 forms the substrate bottom layer 110, and the sidewalls of the package substrate 10 corresponding to the groove 130 form the retaining wall 120. The retaining wall 120 is located on the substrate bottom layer 110 and protrudes relative to the substrate bottom layer 110.

[0066] In this embodiment, of the retaining walls 120 located on opposite sides of the groove 130, only one retaining wall 120 is provided with an introduction structure 1201 facing the groove 130. In other words, of the retaining walls 120 located on opposite sides of the groove 130, one retaining wall 120 is provided with an introduction structure 1201 facing the groove 130, while the other retaining wall 120 is not provided with an introduction structure 1201 facing the groove 130. The introduction structure 1201 facing the groove 130 means that the corresponding introduction structure surface of the introduction structure 1201 faces the groove 130.

[0067] In the above structure, the bare chip die only needs to be transferred into the groove 130 of the packaging substrate 10, without requiring high transfer position accuracy. Since the size of the bare chip die is only slightly smaller than that of the groove 130, during packaging, the encapsulant primarily fills the groove 130 through one side of the lead-in structure 1201. During the lamination process, the encapsulant generates a lateral thrust on the bare chip die from the side of the lead-in structure 1201, causing the bare chip die to move toward the side without the lead-in structure 1201. In this way, the bare chip die can be packaged and fixed in a relatively fixed position in the groove 130, improving the packaging position accuracy of the bare chip die and thus achieving the goal of improving the yield rate of embedded packaging.

[0068] Furthermore, in this embodiment, the orthographic projection of the groove 130 on the substrate bottom layer 110 is a rectangle, and at least one of the retaining walls 120 located on two adjacent sides of the groove 130 is provided with an introduction structure 1201 facing the groove 130 .

[0069] Please refer to Figure 3 The retaining walls 120 on both sides of the groove 130 can be provided with guide structures 1201 facing the groove. The guide structures 1201 provided on the retaining walls 120 on both sides of the groove 130 can be the same or different. Preferably, the guide structures 1201 provided on the retaining walls 120 on both sides of the groove 130 are the same. This design allows the die to be fixed near the corner formed by the two adjacent sides of the groove 130 without the guide structures 1201 during the packaging process, making the position of the die to be packaged and fixed more accurately.

[0070] The orthographic projection of the retaining wall 120 on the substrate bottom layer 110 may be in a grid shape. In other words, the retaining wall 120 may enclose a plurality of grooves 130 on the substrate bottom layer 110, wherein one grid opening corresponds to one groove 130. For example, Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 As shown, the introduction structure 1201 can be located on different sides of at least some of the different grooves 130; or Figure 3 and Figure 8As shown, the introduction structure 1201 may also be located on the same side of different grooves 130. In this embodiment, the introduction structures 1201 located on the retaining walls 120 of different grooves 130 may all be identical, wherein the identical introduction structures 1201 refer to identical shapes and sizes.

[0071] In this embodiment, when the lead-in structure 1201 is located at different sides of at least some of the different grooves 130, different glue coating methods can be selected according to the position of the lead-in structure 1201 in the groove 130 to facilitate packaging. Figure 4 and Figure 6 In the structure shown in FIG, a packaging glue can be applied near the position of the lead-in structure 1201, and a packaging layer for packaging the bare chip in the groove 130 can be obtained by a glue pressing process. Figure 4 Taking the structure shown as an example, since Figure 4 There are adjacent rows of grooves 130 with guide structures 1201 distributed on the adjacent sides between each other, so that the packaging glue can be applied between the adjacent rows of grooves 130. This can reduce the number of times the packaging glue is applied, and at the same time improve the control accuracy of the lateral thrust of the packaging glue on the chip die on the side of the guide structure 1201 during the subsequent glue pressing process, thereby making it easier to control the packaging position of the chip die in the groove 130. For example, in Figure 5 and Figure 7 In the structure shown in the figure, since the distribution position of the introduction structure 1201 is less regular, in order to reduce the number of times of gluing, the packaging glue can be applied on the entire surface, and then the packaging layer is obtained by gluing. In addition, since the distribution position of the above-mentioned introduction structure 1201 is irregular, the reverse force of the introduction structure 1201 on the gluing plate during the gluing process can be balanced.

[0072] In this embodiment, please combine Figure 3 and Figure 8 When the lead-in structure 1201 is located on the same side of different grooves 130 , a packaging glue layer can be produced by coating the position close to the lead-in structure 1201 and performing a pressing process to encapsulate the bare chip in the groove 130 .

[0073] Further, in this embodiment, please refer to Figure 9 In a direction perpendicular to the substrate bottom layer 110, the dimension h1 of the lead-in structure 1201 is smaller than the depth h2 of the groove 130. To improve the fluidity difference between the side with the lead-in structure 1201 and the side without the lead-in structure 1201, in this embodiment, the dimension h1 of the lead-in structure 1201 is set between 30% and 70% of the depth h2 of the groove 130.

[0074] In this embodiment, the introduction structure 1201 may include rounded corners and / or chamfered corners. In order to improve the fluidity of the packaging glue at the position of the introduction structure 1201, the introduction structure 1201 is preferably chamfered.

[0075] In this embodiment, the sidewalls of the retaining groove 130 are perpendicular to the substrate bottom layer 110. The substrate bottom layer 110 and the retaining wall 120 can be made of the same material. For example, the substrate bottom layer 110 and the retaining wall 120 can be an integrally formed structure manufactured simultaneously, or can be manufactured in sequence. Preferably, the substrate bottom layer 110 and the retaining wall 120 are an integrally formed structure.

[0076] In the packaging substrate 10 provided in the above-described embodiment, of the retaining walls 120 on opposite sides of the groove 130, only one retaining wall 120 is provided with a guide structure 1201 facing the groove 130. Due to the asymmetric design on the two opposing sides, during the adhesive lamination process, the encapsulation adhesive primarily fills the groove 130 through one side of the guide structure 1201. The encapsulation adhesive exerts a lateral thrust on the die from the guide structure 1201, moving the die toward the side without the guide structure 1201. This secures the die package at a relatively fixed position within the groove 130, improving the die package position accuracy, thereby increasing the yield rate of embedded packaging and reducing the requirements for transfer position accuracy. Furthermore, compared to the prior art, no adhesive layer is required, which can also reduce production costs.

[0077] Second embodiment

[0078] Based on the same invention concept, please refer to Figure 10 , Figure 10 The following is a schematic diagram of the structure of the packaged chip provided by this embodiment. In this embodiment, the packaged chip 1 includes a package substrate 10 , a chip die 20 and a package layer 30 .

[0079] The package substrate 10 includes a substrate bottom layer 110 and retaining walls 120. A recess 130 is defined in the package substrate 10. The bottom wall of the package substrate 10 corresponding to the recess 130 forms the substrate bottom layer 110, and the sidewalls of the package substrate 10 corresponding to the recess 130 form the retaining walls 120. The retaining walls 120 are located on the substrate bottom layer 110 and protrude relative to the substrate bottom layer 110. In this embodiment, of the retaining walls 120 located on opposite sides of the recess 130, only one retaining wall 120 is provided with a guide structure 1201 facing the recess 130. In other words, of the retaining walls 120 located on opposite sides of the recess 130, the retaining wall 120 on one side is provided with a guide structure 1201 facing the recess 130, while the retaining wall 120 on the other side is not provided with a guide structure 1201 facing the recess 130.

[0080] In this embodiment, the chip die 20 is placed in the groove 130 , the packaging layer 30 is located on the packaging substrate 10 and fills the gap between the chip die 20 and the groove 130 , and the chip die 20 is close to the retaining wall 120 without the introduction structure 1201 .

[0081] The packaged chip 1 provided above is obtained based on the characteristic that the fluidity of the packaging glue on the side with the introduction structure 1201 is greater than the fluidity on the side without the introduction structure 1201 during the packaging process. The chip bare die 20 can be placed close to the retaining wall 120 without the introduction structure 1201. The position of the chip bare die 20 in the groove 120 is determined, thereby ensuring that the packaged chip 1 has good packaging performance.

[0082] Furthermore, in this embodiment, the orthographic projection of the groove 130 on the substrate bottom layer 110 is a rectangle, and at least one of the retaining walls 120 located on two adjacent sides of the groove 130 is provided with an introduction structure 1201 facing the groove 130 .

[0083] Please refer again Figure 3 The retaining walls 120 on both sides of the groove 130 can be provided with a guide structure 1201 facing the groove. The guide structures 1201 provided on the retaining walls 120 on both sides of the groove 130 can be the same or different. Preferably, the guide structures 1201 provided on the retaining walls 120 on both sides of the groove 130 are the same, and the guide structures 1201 can include chamfers. This design allows the die to be fixed near the corner formed by the two adjacent sides of the groove 130 without the guide structure 1201 during the packaging process, and the position of the die can be fixed more accurately.

[0084] For further information, please refer to Figure 11 In a direction perpendicular to substrate bottom layer 110, dimension h1 of lead-in structure 1201 is smaller than depth h2 of recess 130, and height h3 of die 20 is greater than depth h2 of recess 130. To increase the difference in encapsulant fluidity between the side with lead-in structure 1201 and the side without lead-in structure 1201, in this embodiment, dimension h1 of lead-in structure 1201 is set between 30% and 70% of depth h2 of recess 130.

[0085] In this embodiment, preferably, the depth h2 of the groove 130 may be between 10% and 90% of the height h3 of the chip die 20 .

[0086] For further information, please refer to Figure 12The sidewalls of the groove 130 are perpendicular to the substrate bottom layer 110. In a direction perpendicular to the sidewalls forming the groove 130, the width d1 of the groove 130 is greater than the width d2 of the chip die. The dimension d3 of the lead-in structure 1201 is greater than the difference d1-d2 between the width d1 of the groove 130 and the width d2 of the chip die 20, and the dimension d3 of the lead-in structure 1201 is less than 5*(d1-d2).

[0087] Third embodiment

[0088] Based on the same inventive concept, this embodiment also provides a chip packaging method, please refer to Figure 13 and Figure 14 , Figure 13 The following is a flow chart illustrating the chip packaging method provided in this embodiment. Figure 14 Example Figure 13 The corresponding process diagram is combined with the following Figure 13 and Figure 14 Each step of the chip packaging method provided in this embodiment is described in detail.

[0089] Step S110 , providing a packaging substrate 10 .

[0090] The packaging substrate provided in this step is the packaging substrate 10 described in the first embodiment.

[0091] In step S120 , the bare chip 20 is transferred into the cavity 130 of the package substrate 10 .

[0092] In this step, it is only necessary to transfer the chip die 20 into the groove 130 , and there is no need to place too high a requirement on the transfer accuracy of the chip die 20 .

[0093] Step S130 , forming an encapsulation layer 30 .

[0094] In this step, since the size of the chip die 20 is only slightly smaller than the size of the groove 130, during packaging, the encapsulation glue mainly fills the groove 130 through one side of the lead-in structure 1201. During the lamination process, the encapsulation glue generates a lateral thrust on the chip die 20 from the side of the lead-in structure 1201, causing the chip die 20 to move toward the side where the lead-in structure 1201 is not provided.

[0095] For example, please refer to Figure 15 , step S130 can be implemented in the following manner.

[0096] First, packaging glue is applied at a position close to the lead-in structure 1201 in the packaging substrate 10 , wherein the packaging glue can be in a strip shape, and the strip-shaped packaging glue can be formed by spraying along a set direction using a glue spray nozzle.

[0097] Next, the packaging adhesive is laminated using a laminating plate 2 to produce a packaging layer 30 .

[0098] During this process, the adhesive laminating plate 2 presses down vertically from above the packaging substrate 10. After the adhesive laminating plate 2 acts on the encapsulating adhesive, the encapsulating adhesive expands in all directions. During this expansion process, the encapsulating adhesive primarily enters the groove 130 through the guide structure 1201. The encapsulating adhesive entering the groove 130 exerts a lateral thrust on the chip die 20, pushing the chip die 20 toward the side where the guide structure 1201 is not provided. This secures the chip die 20 at a predetermined position within the groove 130.

[0099] Based on the same inventive concept, this embodiment further provides an electronic device that may include the packaged chip described in the second embodiment. Because the position of the die in the packaged chip is relatively fixed, the packaged chip can be ensured to have good packaging performance, thereby ensuring the performance stability of the electronic device using the packaged chip.

[0100] The embodiments of the present application provide a packaging substrate, a packaging chip, an electronic device, and a chip packaging method. In the packaging substrate, a groove is provided on the packaging substrate, the bottom wall of the packaging substrate corresponding to the groove forms a substrate bottom layer, the side walls of the packaging substrate corresponding to the groove form retaining walls, and one retaining wall on one side of the retaining walls on opposite sides of the groove is provided with an introduction structure facing the groove. The above design only requires transferring the chip die to the groove of the packaging substrate, and there is no need to have excessively high requirements for the transfer position accuracy. During packaging, the packaging glue generates a lateral thrust on the chip die from one side of the introduction structure during the glue pressing, so that the chip die moves toward the side where the introduction structure is not provided. In this way, the chip die package can be fixed at a relatively fixed position in the groove, thereby improving the packaging position accuracy of the chip die, thereby achieving the purpose of improving the yield of embedded packaging.

[0101] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A packaging substrate, characterized in that: The packaging substrate is used for packaging bare chips, wherein the packaging substrate is provided with a groove for accommodating the bare chips, the bottom wall of the packaging substrate corresponding to the groove is formed as a substrate bottom layer, and the side walls of the packaging substrate corresponding to the groove are formed as retaining walls, wherein the bare chips and the bottom wall of the groove are not fixedly connected; Among the retaining walls located on opposite sides of the groove, only one retaining wall is provided with an introduction structure toward the groove; The orthographic projection of the groove on the bottom layer of the substrate is a rectangle, and the introduction structure is arranged on the retaining walls on two adjacent sides of the groove; Wherein, the introduction structures located on the retaining walls of different grooves are the same; The orthographic projection of the retaining wall on the bottom layer of the substrate is in a grid shape. The retaining wall encloses a plurality of grooves on the bottom layer of the substrate. The introduction structure is located on different sides of different grooves. The grooves located in adjacent columns are provided with introduction structures on adjacent sides thereof.

2. The packaging substrate according to claim 1, wherein The introduction structures provided on the retaining walls on both sides of the groove are identical; The lead-in structure includes a chamfer.

3. The packaging substrate according to any one of claims 1 to 2, wherein: In a direction perpendicular to the bottom layer of the substrate, the size of the introduction structure is smaller than the depth of the groove; The size of the lead-in structure is between 30% and 70% of the depth of the groove.

4. The packaging substrate according to claim 3, wherein: The introduction structure includes rounded corners and / or chamfered corners.

5. The packaging substrate according to claim 3, wherein: The introduction structure is a chamfered angle; The sidewall of the groove is perpendicular to the bottom layer of the substrate.

6. A packaged chip, characterized in that: The packaged chip includes a packaging substrate, a bare chip and a packaging layer; The packaging substrate is provided with a groove, the bottom wall of the packaging substrate corresponding to the groove is formed as a substrate bottom layer, and the side walls of the packaging substrate corresponding to the groove are formed as retaining walls; Among the retaining walls located on opposite sides of the groove, only one retaining wall is provided with an introduction structure facing the groove, the orthographic projection of the groove on the bottom layer of the substrate is a rectangle, and the introduction structure is provided on the retaining walls on two adjacent sides of the groove; The bare chip is disposed in the groove, and the bare chip is non-fixedly connected to the bottom wall of the groove; The packaging layer is located on the packaging substrate and fills the gap between the chip die and the groove, wherein the chip die is close to the retaining wall where the introduction structure is not provided; The orthographic projection of the retaining wall on the bottom layer of the substrate is in a grid shape. The retaining wall encloses a plurality of grooves on the bottom layer of the substrate. The introduction structure is located on different sides of different grooves. The grooves located in adjacent columns are provided with introduction structures on adjacent sides thereof.

7. The packaged chip according to claim 6, wherein: The introduction structures provided on the retaining walls on both sides of the groove are identical; The lead-in structure includes a chamfer.

8. The packaged chip according to claim 6, wherein: In a direction perpendicular to the bottom layer of the substrate, the size of the lead-in structure is smaller than the depth of the groove, and the height of the chip die is greater than the depth of the groove; The size of the lead-in structure is between 30% and 70% of the depth of the groove, and the depth of the groove is between 10% and 90% of the height of the chip die.

9. The packaged chip according to claim 6, wherein: The sidewall of the groove is perpendicular to the bottom layer of the substrate. In the direction perpendicular to the sidewall of the groove, the width of the groove is greater than the width of the chip die. The size of the introduction structure is greater than the difference between the width of the groove and the width of the chip die, and the size of the introduction structure is less than five times the difference.

10. An electronic device, characterized in that: The electronic device comprises the packaged chip according to any one of claims 6 to 9.

11. A chip packaging method, characterized in that: The chip packaging method comprises: Providing the packaging substrate according to any one of claims 1 to 5; Transferring the bare chip into the groove of the packaging substrate; A packaging layer is formed, wherein during the process of forming the packaging layer, the packaging glue generates a lateral thrust on the chip die from one side of the lead-in structure during the lamination process, so that the chip die moves toward the side where the lead-in structure is not provided.

12. The chip packaging method according to claim 11, wherein: The step of forming the encapsulation layer includes: Applying packaging glue at a position close to the lead-in structure in the packaging substrate; The packaging adhesive is subjected to a pressing process using a pressing plate to produce the packaging layer.

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