Semiconductor device and method for manufacturing the same

Abstract

Disclosed are a semiconductor device and a method for manufacturing the same. The method includes forming an active pattern on a substrate, the substrate including a first logic cell region and a second logic cell region adjacent to each other in a first direction; and forming a device isolation layer on the substrate that exposes an upper portion of the active pattern. Forming the active pattern includes forming a first line mask pattern that extends parallel to each other in the first direction and spans the first logic cell region and the second logic cell region; forming an upper separation mask pattern on the first line mask pattern, the upper separation mask pattern including a first opening that overlaps at least two of the first line mask patterns; forming a first hard mask pattern from the at least two first line mask patterns; and etching the substrate to form a trench that defines the active pattern.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 201710346560.6, whose application date is May 17, 2017 and whose invention name is “Semiconductor device and manufacturing method thereof”. Technical Field

[0002] The embodiments discussed herein relate generally to semiconductor devices and methods of manufacturing the same, and more particularly, to semiconductor devices including fin field-effect transistors and methods of manufacturing the same. Background Art

[0003] Semiconductor devices include integrated circuits composed of MOSFETs (metal oxide semiconductors). As the size and design rules of semiconductor devices decrease, the size of the MOSFETs in integrated circuits also decreases. As MOSFETs become smaller, short channel effects occur in the MOSFETs, and the operating characteristics of the semiconductor devices deteriorate. Summary of the Invention

[0004] Embodiments of the inventive concept provide a semiconductor device having improved reliability and a method of manufacturing the same.

[0005] According to some exemplary embodiments of the present inventive concepts, a method for manufacturing a semiconductor device may include: forming an active pattern on a substrate, the substrate including a first logic cell region and a second logic cell region adjacent to each other along a first direction; and forming a device isolation layer on the substrate that exposes an upper portion of the active pattern. The step of forming the active pattern may include: forming a first line mask pattern extending parallel to each other along the first direction and crossing the first logic cell region and the second logic cell region; forming an upper separation mask pattern on the first line mask pattern, wherein the upper separation mask pattern is located on a first cell boundary between the first logic cell region and the second logic cell region and includes a first opening overlapping at least two of the first line mask patterns; performing a first etching process using the upper separation mask pattern as an etching mask to form a first hard mask pattern from the at least two first line mask patterns; and etching the upper portion of the substrate through a second etching process using the first hard mask pattern as an etching mask to form a trench defining the active pattern.

[0006] According to some exemplary embodiments of the present inventive concepts, a semiconductor device may include: a substrate including a plurality of logic cells arranged along a first direction; an active pattern; and a device isolation layer on the substrate. The device isolation layer may include: a first double diffusion interrupt region having a first width measured along the first direction and arranged between a pair of adjacent logic cells; and a second double diffusion interrupt region having a second width measured along the first direction that is greater than the first width and arranged between another pair of adjacent logic cells. The active pattern may include: a plurality of pairs of first active patterns, the first active patterns in each pair being spaced apart from each other along the first direction with the first double diffusion interrupt region interposed therebetween; and a plurality of pairs of second active patterns, the second active patterns in each pair being spaced apart from each other along the first direction with the second double diffusion interrupt region interposed therebetween. The first active pattern may include a first end portion adjacent to one side of the first double diffusion interrupt region and aligned with each other along a second direction intersecting the first direction. The second active pattern may include a second end portion adjacent to one side of the second double diffusion interrupt region, and one of the second end portions may be offset from the other of the second end portions along the first direction.

[0007] According to some exemplary embodiments, a semiconductor device may include: a substrate including first and second cell regions adjacent to each other along a first direction, with a first cell boundary interposed therebetween and extending along a second direction intersecting the first direction; first active patterns arranged on the first and second cell regions along a second direction, each of the first active patterns extending along the first direction but not intersecting the first cell boundary; and a device isolation layer on the substrate exposing upper portions of the active patterns. The device isolation layer may include: a first double diffusion interruption region disposed on the first cell boundary and between at least two pairs of first active patterns located on different cell regions and adjacent to each other along the first direction; and a first single diffusion interruption region disposed on at least one selected from the group consisting of the first and second cell regions and between the pairs of first active patterns located on the same cell region and adjacent to each other along the first direction. The semiconductor device may further include a gate pattern intersecting the first active patterns.

[0008] According to some exemplary embodiments, a semiconductor device may include: a substrate including a first cell region and a second cell region adjacent to each other along a first direction, a cell boundary interposed between the first cell region and the second cell region and extending along a second direction intersecting the first direction; active patterns arranged on the first cell region and the second cell region along a second direction, each of the active patterns extending along the first direction but not intersecting the cell boundary; a device isolation layer on the substrate and exposing portions of the active patterns, wherein the exposed portions of the active patterns include active fins, and wherein the device isolation layer includes a double diffusion break region disposed on the cell boundary and between pairs of active patterns located on the first cell region and the second cell region and adjacent to each other along the first direction, the active patterns being at least two pairs; gate patterns arranged along the first direction and intersecting the active fins along the second direction; and first source / drain regions arranged in upper portions of the active patterns between adjacent ones of the gate patterns, wherein at least one of the first source / drain regions includes an epitaxial layer and has a top surface parallel to a top surface of at least one of the active patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 are top views illustrating semiconductor devices according to some exemplary embodiments of the inventive concept.

[0010] Figure 2A is a diagram for explaining the configuration of active patterns in a semiconductor device according to some exemplary embodiments of the present inventive concept, and more particularly, Figure 1 A top view of an example of a boundary portion between a first logic unit and a second logic unit.

[0011] Figure 2B It is shown by way of example that Figure 2A A top view of a portion of a semiconductor device with an active pattern.

[0012] Figure 3A is a diagram for explaining the configuration of active patterns in a semiconductor device according to some exemplary embodiments of the present inventive concept, and more particularly, Figure 1 A top view of an example of a boundary portion between a first logic unit and a second logic unit.

[0013] Figure 3B It is shown by way of example that Figure 3A A top view of a portion of a semiconductor device with an active pattern.

[0014] Figure 4 is a top view illustrating an example of arrangement of double diffusion break regions in a semiconductor device according to some example embodiments of the inventive concept.

[0015] Figures 5A to 15A are top plan views illustrating a method for fabricating a semiconductor device including an active pattern according to some exemplary embodiments of the inventive concept.

[0016] Figures 5B to 15B are respectively along Figures 5A to 15A Cross-sectional views taken along lines II' and II-II'.

[0017] Figures 5C to 15C are respectively along Figures 5A to 15A Cross-sectional views taken along lines III-III' and IV-IV'. DETAILED DESCRIPTION

[0018] Figure 1 are top views illustrating semiconductor devices according to some exemplary embodiments of the inventive concept.

[0019] Reference Figure 1 , a plurality of logic cells C1, C2, C3, and C4 may be provided on a substrate of a semiconductor device according to an exemplary embodiment of the inventive concept. Each of the logic cells C1, C2, C3, and C4 may include a plurality of transistors (not shown). For example, the logic cells C1, C2, C3, and C4 may include: a first logic cell C1; a second logic cell C2 spaced apart from the first logic cell C1 in a first direction D1; a third logic cell C3 spaced apart from the first logic cell C1 in a second direction D2 intersecting (e.g., perpendicular to) the first direction D1; and a fourth logic cell C4 spaced apart from the second logic cell C2 in the second direction D2. The fourth logic cell C4 may be spaced apart from the third logic cell C3 in the first direction D1. A cell boundary CB may be defined between adjacent logic cells among the logic cells C1, C2, C3, and C4.

[0020] Each of the logic cells C1, C2, C3, and C4 may include a PMOSFET active region PR and an NMOSFET active region NR, each separated from one another by a device isolation layer ST. For example, the PMOSFET active region PR and the NMOSFET active region NR of each of the logic cells C1, C2, C3, and C4 may be spaced apart from one another in the second direction D2. Logic cells C1, C2, C3, and C4 adjacent to one another in the second direction D2 may be arranged so that their active regions of the same conductivity type face one another. For example, the first logic cell C1 may be arranged so that its PMOSFET active region PR is adjacent to the PMOSFET active region PR of the third logic cell C3. In this specification, any logic cell may be referred to herein as a cell for performing a Boolean logic function (e.g., INVERTER, AND, OR, NAND, etc.) or a memory function (e.g., a flip-flop). Although only four logic cells are shown, it should be appreciated that any number of logic cells may be provided.

[0021] In some embodiments, the transistors included in each of the logic cells C1, C2, C3, and C4 may be configured based on a FinFET structure. For example, the PMOSFET active region PR and the NMOSFET active region NR in each of the logic cells C1, C2, C3, and C4 may include an active pattern having a fin shape protruding from the substrate. The gate electrode constituting the transistor may straddle at least one of the active patterns.

[0022] Figure 2A is a diagram for explaining the configuration of active patterns in a semiconductor device according to some exemplary embodiments of the present inventive concept, and more particularly, Figure 1 A top view of an example of a boundary portion between a first logic unit and a second logic unit.

[0023] Reference Figure 1 and Figure 2A , a plurality of active patterns AP may be provided, the plurality of active patterns AP having a length measured along the first direction D1 and arranged along the first direction D1 and the second direction D2. The active pattern AP may have a fin shape protruding from the top surface of the substrate in a third direction D3 (e.g., perpendicular to the first direction D1 and the second direction D2). The active pattern AP of the first logic cell C1 may constitute the PMOSFET active region PR or the NMOSFET active region NR of the first logic cell C1, and the active pattern AP of the second logic cell C2 may constitute the PMOSFET active region PR or the NMOSFET active region NR of the second logic cell C2. The active pattern AP of the first logic cell C1 may have the same conductivity as the active pattern AP of the second logic cell C2.

[0024] The device isolation layer ST can separate the active patterns AP from each other. That is, the device isolation layer ST can be provided between adjacent active patterns in the active pattern AP. In some embodiments, the device isolation layer ST can include first isolation regions IR1n and IR1w extending in a first direction D1 and defining first (e.g., relatively long) sidewalls of the active pattern AP, and second isolation regions IR2s and IR2d extending in a second direction D2 and defining second (e.g., relatively short) sidewalls of the active pattern AP. In one embodiment, the first isolation regions IR1n and IR1w and the second isolation regions IR2s and IR2d can be part of a single, integrated insulating layer. In another embodiment, one or more of the first isolation regions IR1n and IR1w and the second isolation regions IR2s and IR2d can be part of a separately formed insulating layer.

[0025] The first separation regions IR1n and IR1w may be arranged along the second direction D2, and the width of the active pattern AP may correspond to the interval between the first separation regions IR1n and IR1w along the second direction D2. For example, the first separation regions IR1n and IR1w may be equally spaced apart from each other along the second direction D2, and thus the active pattern AP may have substantially the same width.

[0026] In one embodiment, the first isolation regions IR1n and IR1w may include a pair of wide first isolation regions IR1w positioned outermost along the second direction D2, and a narrow first isolation region IR1n positioned between the pair of wide first isolation regions IR1w. The width of the wide first isolation region IR1w may be greater than the width of the narrow first isolation region IR1n. For example, the wide first isolation region IR1w may be used to separate the PMOSFET active region PR and the NMOSFET active region NR from each other to define a region for transistors, to separate adjacent logic cells from each other in the second direction D2, etc. However, it should be understood that the wide first isolation region IR1w may be used for other purposes.

[0027] The narrow first isolation regions IR1n may have at least substantially the same width. The active patterns AP may be spaced apart from each other at equal intervals along the second direction D2, with one of the narrow first isolation regions IR1n interposed between a pair of adjacent active patterns AP. A single multi-fin transistor may be implemented by a single gate pattern spanning the active patterns AP equally spaced apart from each other along the second direction D2. Although only four active patterns AP are shown as constituting a single multi-fin transistor that can be implemented by a single gate pattern, it should be appreciated that any number of active patterns AP may be provided to constitute a single multi-fin transistor. In other words, although only three narrow first isolation regions IR1n are shown between a pair of wide first isolation regions IR1w, it should be appreciated that any number of narrow first isolation regions IR1n may be provided between a pair of wide first isolation regions IR1w.

[0028] The second isolation regions IR2s and IR2d may be defined to intersect the first isolation regions IR1n and IR1w. The second isolation regions IR2s and IR2d may therefore partially coextensive with the first isolation regions IR1n and IR2w. The second isolation regions IR2s and IR2d may be arranged along the first direction D1, and the length of the active pattern AP may correspond to the spacing between the second isolation regions IR2s and IR2d along the first direction D1. For example, the active pattern AP may have opposite ends in the length direction, adjacent to the second isolation regions IR2s and IR2d, respectively, with the second isolation regions IR2s and IR2d spaced apart from each other along the first direction D1. As shown in the figure, the active pattern AP may have various lengths.

[0029] In one embodiment, the second separation regions IR2s and IR2d may include: a single diffusion interrupt region IR2s, which is provided between a pair of active patterns AP spaced apart from each other along the first direction D1 in each of the logic cells C1 and C2; and a double diffusion interrupt region IR2d, which is provided between a pair of logic cells (e.g., the first logic cell C1 and the second logic cell C2) adjacent to each other along the first direction D1.

[0030] The single diffusion interrupt region IR2s may have a first width W1 measured along the first direction D1. The first width W1 may be defined by the spacing between a pair of active patterns AP that are adjacent to each other along the first direction D1 and have the single diffusion interrupt region IR2s interposed therebetween. In some embodiments, the active patterns AP may have substantially the same planar shape at their respective ends adjacent to the single diffusion interrupt region IR2s. The ends of the active patterns AP adjacent to the same side of the common single diffusion interrupt region IR2s may be aligned with each other along the second direction D2. Therefore, the active patterns AP within a pair of active patterns AP that are adjacent to each other along the first direction D1 across the common single diffusion interrupt region IR2s may be spaced apart from each other by the same spacing. That is, the first width W1 of the single diffusion interrupt region IR2s may be uniform (or at least substantially uniform) along the second direction D2.

[0031] The double diffusion interrupt region IR2d may have a second width W2 measured along the first direction D1. The second width W2 may be defined by the spacing between active patterns AP adjacent to each other along the first direction D1 and having the double diffusion interrupt region IR2d interposed therebetween. In this specification, the second width W2 may correspond to the minimum width of the double diffusion interrupt region IR2d provided between pairs of logic cells adjacent to each other in the first direction D1. The double diffusion interrupt region IR2d having the second width W2 may also be referred to herein as a narrow double diffusion interrupt region IR2dn.

[0032] In some embodiments, the active pattern AP may have substantially the same planar shape at respective end portions thereof adjacent to the narrow double diffusion interruption region IR2dn. In one embodiment, the end portion of the active pattern AP adjacent to the narrow double diffusion interruption region IR2dn may be the same as or similar to the end portion of the active pattern AP adjacent to the single diffusion interruption region IR2s.

[0033] When viewed in a top view, the end portions ed of the active pattern AP of the first logic cell C1 adjacent to the narrow double diffusion interrupt region IR2dn may be aligned with one another along the second direction D2. Similarly, when viewed in a top view, the end portions ed of the active pattern AP of the second logic cell C2 adjacent to the narrow double diffusion interrupt region IR2dn may be aligned with one another in the second direction D2. Thus, the same spacing may be provided between active patterns AP adjacent to one another in the first direction D1 with the narrow double diffusion interrupt region IR2dn interposed therebetween. That is, the second width W2 of the narrow double diffusion interrupt region IR2dn may be uniform (or at least substantially uniform) along the second direction D2. The second width W2 of the narrow double diffusion interrupt region IR2dn may be greater than the first width W1 of the single diffusion interrupt region IR2s.

[0034] In one embodiment, the active pattern AP can be formed by a process including patterning a substrate to form trenches, wherein the trenches define the active pattern AP. A single patterning process can be performed so that the trenches are formed simultaneously. An insulating layer can be provided to fill the lower portions of the trenches, thereby forming the first isolation regions IR1n and IR1w and the second isolation regions IR2s and IR2d. Therefore, in one embodiment, the active pattern AP and the device isolation layer ST can be formed by a single trenching process and a single filling process. A detailed description of the formation of the active pattern AP will be discussed later.

[0035] Figure 2B It is shown by way of example that Figure 2A A top view of a portion of a semiconductor device with an active pattern.

[0036] Reference Figure 2B , the gate pattern GP may be provided across the active pattern AP. For example, the gate pattern GP may have a line shape or a bar shape extending along the second direction D2 and arranged at regular intervals along the first direction D1. Although not shown, each gate pattern GP may include a gate electrode and a gate dielectric pattern.

[0037] One or more of the gate patterns GP may overlap the second isolation region IR2s or IR2d. The gate pattern GP overlapping the second isolation regions IR2s and IR2d may be referred to herein as a dummy gate pattern GP_DM. As not shown, the single diffusion interrupt region IR2s may be overlapped by a single dummy gate pattern GP_DM. The double diffusion interrupt region IR2d may be overlapped by at least two or more dummy gate patterns GP_DM. The narrow double diffusion interrupt region IR2dn may overlap two dummy gate patterns GP_DM. One of the two dummy gate patterns GP_DM may overlap the end of the active pattern AP of the first logic cell C1 adjacent to the narrow double diffusion interrupt region IR2dn, and the other of the two dummy gate patterns GP_DM may overlap the end of the active pattern AP of the second logic cell C2 adjacent to the narrow double diffusion interrupt region IR2dn. In some embodiments, the second width W2 of the narrow double diffusion interrupt region IR2dn can be substantially the same as or smaller than the pitch of the gate patterns GP (e.g., measured along the first direction D1) (i.e., such that the narrow double diffusion interrupt region IR2dn is still overlapped by the two dummy gate patterns GP_DM).

[0038] Figure 3A is a diagram for explaining the configuration of active patterns in a semiconductor device according to some exemplary embodiments of the present inventive concept, and more particularly, Figure 1A top view of an example of a boundary portion between a first logic unit and a second logic unit. Figure 3B It is shown by way of example that Figure 3A For the sake of brevity, repeated descriptions will be omitted.

[0039] Reference Figure 1 and Figure 3A , the double diffusion interrupt region IR2d may have a third width W3 measured along the first direction D1, which is defined by the interval between the active patterns AP adjacent to each other along the first direction D1 and having the double diffusion interrupt region IR2d interposed therebetween. The third width W3 may be greater than the second width W2 of the narrow double diffusion interrupt region IR2dn (e.g., as shown in FIG. Figure 2A and Figure 2B In other words, the double diffusion interrupt region IR2d may have a width greater than the second width W2, and the second width W2 may be considered as the minimum width of the double diffusion interrupt region IR2d. The double diffusion interrupt region IR2d having the third width W3 may also be referred to herein as a wide double diffusion interrupt region IR2dw.

[0040] In some embodiments, the third width W3 of the wide double diffusion interruption region IR2dw may vary depending on its position along the second direction D2. The end portion of the active pattern AP adjacent to the wide double diffusion interruption region IR2dw may have different shapes that vary depending on the corresponding position along the second direction D2. This will be referred to as Figure 3B Discussed in further detail.

[0041] Reference Figure 3BThe active pattern AP adjacent to the wide double diffusion break region IR2dw may include an outermost active pattern AP_O located on the outermost side along the second direction D2 and an inner active pattern AP_I located between the outermost active patterns AP_O. The outermost active pattern AP_O may have a first end ed1 adjacent to a side of the wide double diffusion break region IR2dw, and the inner active pattern AP_I may have a second end ed2 adjacent to the side of the wide double diffusion break region IR2dw. The first end ed1 and the second end ed2 may be offset from each other along the first direction D1. For example, a first logic cell C1 may have an inner active pattern AP_I and an outermost active pattern AP_O, each having a second end ed2 and a first end ed1 adjacent to the same side of the wide double diffusion break region IR2dw, and the second end ed2 may protrude deeper toward the cell boundary CB than the first end ed1. Similarly, the second logic cell C2 may include an inner active pattern AP_I and an outermost active pattern AP_O, each having a second end ed2 and a first end ed1 adjacent to the same side of the wide double diffusion break region IR2dw, and the second end ed2 may protrude deeper toward the cell boundary CB than the first end ed1. Thus, a relatively large gap may be provided between a pair of outermost active patterns AP_O adjacent to each other along the first direction D1 and spaced apart from each other by the wide double diffusion break region IR2dw, and a relatively small gap may be provided between a pair of inner active patterns AP_I adjacent to each other in the first direction D1 and spaced apart from each other by the wide double diffusion break region IR2dw. In other words, the third width W3 of a portion of the wide double diffusion break region IR2dw adjacent to the outermost active pattern AP_O may be greater than the third width W3 of a portion of the wide double diffusion break region IR2dw adjacent to the inner active pattern AP_I.

[0042] The outermost active pattern AP_O may have a first shape at the corresponding end ed1 adjacent to the wide double diffusion interruption region IR2dw, and the inner active pattern AP_I may have a second shape at the corresponding end ed2 adjacent to the wide double diffusion interruption region IR2dw. The first shape of the outermost active pattern AP_O may be different from the second shape of the inner active pattern AP_I. For example, the end ed1 of the outermost active pattern AP_O may have a rounded shape, while the end of the inner active pattern AP_I may have a flat shape, for example, with angled corners.

[0043] In some embodiments, the wide double diffusion interrupt region IR2dw may be overlapped by at least three or more dummy gate patterns GP_DM. Figure 3BAs shown, the wide double diffusion break region IR2dw may overlap three dummy gate patterns GP_DM. One of the three dummy gate patterns GP_DM overlapping the wide double diffusion break region IR2dw may collectively overlap end portions ed1 and ed2 of the active pattern AP of the first logic cell C1 adjacent to the wide double diffusion break region IR2dw, and another of the three dummy gate patterns GP_DM overlapping the wide double diffusion break region IR2dw may collectively overlap end portions ed1 and ed2 of the active pattern AP of the second logic cell C2 adjacent to the wide double diffusion break region IR2dw. Another of the three dummy gate patterns GP_DM may be disposed on the wide double diffusion break region IR2dw (e.g., so as to overlap with the cell boundary CB). The third width W3 of the wide double diffusion interrupt region IR2dw may be substantially the same as or less than twice the pitch of the gate pattern GP (i.e., so that the wide double diffusion interrupt region IR2dw is still overlapped by three dummy gate patterns GP_DM). Depending on the number of dummy gate patterns GP_DM that overlap the wide double diffusion interrupt region IR2dw, the third width W3 of the wide double diffusion interrupt region IR2dw may increase.

[0044] As discussed above, the shape and configuration of the end portion of the active pattern AP adjacent to the wide double diffusion interruption region IR2dw may be different from the shape and configuration of the end portion of the active pattern AP adjacent to the narrow double diffusion interruption region IR2dn. This difference may be due to differences in their manufacturing methods, which will be discussed in further detail later.

[0045] Figure 4 is a top view illustrating an example of arrangement of double diffusion break regions in a semiconductor device according to some example embodiments of the inventive concept.

[0046] As needed, various sizes and widths may be implemented on the double diffusion interrupt region IR2d between logic cells adjacent to each other in the first direction D1. For example, a narrow double diffusion interrupt region IR2dn may be provided to have a second width W2 between a pair of logic cells adjacent to each other along the first direction D1, and a wide double diffusion interrupt region IR2dw may be provided to have a third width W3 greater than the second width W2 between another pair of logic cells adjacent to each other along the first direction D1. Figure 4 The arrangement of the double diffusion interrupt region IR2d is discussed in more detail.

[0047] Reference Figure 4, a semiconductor device according to some exemplary embodiments of the present inventive concept may include a first logic cell C1, a second logic cell C2, and a fifth logic cell C5, respectively provided on a substrate. The first logic cell C1, the second logic cell C2, and the fifth logic cell C5 may be arranged along a first direction D1. For example, the first logic cell C1 and the fifth logic cell C5 may be spaced apart from each other along the first direction D1, with the second logic cell C2 interposed therebetween. The first logic cell C1 and the second logic cell C2 may share a first cell boundary CB1, and the second logic cell C2 and the fifth logic cell C5 may share a second cell boundary CB2.

[0048] In one embodiment and as exemplarily shown, a narrow double diffusion break region IR2dn may be provided between the first and second logic cells C1 and C2, and a wide double diffusion break region IR2dw may be provided between the second and fifth logic cells C5. However, in another embodiment, a narrow double diffusion break region IR2dn may be provided between the first and second logic cells C1 and C2 and between the second and fifth logic cells C5, or a wide double diffusion break region IR2dw may be provided between the first and second logic cells C1 and C2 and between the second and fifth logic cells C5. In another embodiment, a wide double diffusion break region IR2dw may be provided between the first and second logic cells C1 and C2, and a narrow double diffusion break region IR2dn may be provided between the second and fifth logic cells C5.

[0049] Figures 5A to 15A are top plan views illustrating a method for fabricating a semiconductor device including an active pattern according to some exemplary embodiments of the inventive concept. Figures 5B to 15B are respectively along Figures 5A to 15A Cross-sectional views taken along lines II' and II-II'. Figures 5C to 15C are respectively along Figures 5A to 15A Cross-sectional views taken along lines III-III' and IV-IV'.

[0050] Reference Figure 5A 、 Figure 5B and Figure 5C, the substrate 100 may be provided to include a first logic cell region CR1, a second logic cell region CR2, a third logic cell region CR3, and a fourth logic cell region CR4, respectively. For example, the first logic cell region CR1 and the second logic cell region CR2 may be regions in which a pair of logic cells adjacent to each other in the first direction D1 are formed, and the third logic cell region CR3 and the fourth logic cell region CR4 may be regions in which another pair of logic cells adjacent to each other in the first direction D1 are formed. The first logic cell region CR1 and the second logic cell region CR2 may share a first cell boundary CB1, and the third logic cell region CR3 and the fourth logic cell region CR4 may share a second cell boundary CB2. Alternatively, the first logic cell region CR1 may be a region in which Figure 4 The first logic cell C1 is formed in the region where the second logic cell region CR2 and the third logic cell region CR3 may be Figure 4 The region where the second logic cell C2 is formed, the fourth logic cell region CR4 may be Figure 4 In this case, Figure 5A The first cell boundary CB1 may correspond to Figure 4 The first cell boundary CB1, Figure 5A The second cell boundary CB2 may correspond to Figure 4 The substrate 100 may be a semiconductor substrate or a compound semiconductor substrate (eg, including silicon, germanium, silicon-germanium, etc. or any combination thereof).

[0051] Through subsequent processes, refer to Figure 2A and Figure 2B The discussed narrow double diffusion interruption region IR2dn can be formed in the substrate 100 between the first logic cell region CR1 and the second logic cell region CR2, and with reference to FIG. Figure 3A and Figure 3B The discussed wide double diffusion interrupt region IR2dw can be formed between the third and fourth logic cell regions CR3 and CR4 in the substrate 100. Embodiments based on the case where different logic cells are formed in the first to fourth logic cell regions CR1, CR2, CR3, and CR4 are also discussed below.

[0052] Reference Figure 5A, line mask patterns 110a and 110b may be formed on the substrate 100 and extend parallel to each other along the first direction D1. For example, the line mask patterns 110a and 110b may extend along the first direction D1 and be spaced apart from each other along the second direction D2. The line mask patterns 110a and 110b may be spaced apart from each other at substantially the same intervals along the second direction D2. The line mask patterns 110a and 110b may include a first line mask pattern 110a formed on the first and second logic cell regions CR1 and CR2, and a second line mask pattern 110b formed on the third and fourth logic cell regions CR3 and CR4. The first line mask pattern 110a may cross the first and second logic cell regions CR1 and CR2 along the first direction D1, and the second line mask pattern 110b may cross the third and fourth logic cell regions CR3 and CR4 along the first direction D1.

[0053] In one embodiment and with reference to Figure 5B and Figure 5C , each of the first and second line mask patterns 110a and 110b may include a lower line mask pattern 112 and an upper line mask pattern 114 having different etching selectivities from each other and sequentially stacked on the substrate 100. The lower line mask pattern 112 may be formed of a material having an etching selectivity relative to the substrate 100. For example, the lower line mask pattern 112 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The upper line mask pattern 114 may be formed of a material having an etching selectivity relative to the lower line mask pattern 112 (e.g., polysilicon). In this embodiment, each of the line mask patterns 110a and 110b is shown as having a double-layer stacked structure, but the present inventive concept is not limited thereto. In certain embodiments, each of the line mask patterns 110a and 110b may include a single-layer structure, a triple-layer stacked structure, etc. The line mask patterns 110a and 110b may be formed using, for example, a double patterning technique or a quadruple patterning technique.

[0054] Reference Figure 6A 、 Figure 6B and Figure 6C, lower separation mask patterns 122, 124, and 126 may be formed on the substrate 100. In one embodiment, the lower separation mask patterns 122, 124, and 126 may be formed by forming a lower separation mask layer covering the line mask patterns 110a and 110b on the entire surface of the substrate 100, and then patterning the lower separation mask layer. The lower separation mask layer may be patterned by, for example, forming a photoresist pattern on the lower separation mask layer to define the lower separation mask patterns 122, 124, and 126, and then etching the lower separation mask layer using the photoresist pattern as an etching mask. The lower separation mask layer may be formed of, for example, a SOH (spin-on hard mask) layer, but it should be appreciated that the lower separation mask layer may be formed of any other suitable material.

[0055] In some embodiments, the lower separation mask patterns 122, 124, and 126 may include: a first lower separation mask pattern 122 extending across the first and second logic cell regions CR1 and CR2 along the first direction D1; a second lower separation mask pattern 124 formed on the third logic cell region CR3; and a third lower separation mask pattern 126 formed on the fourth logic cell region CR4 and spaced apart from the second lower separation mask pattern 124 along the first direction D1. The second lower separation mask pattern 124 and the third lower separation mask pattern 126 may be formed on the third and fourth logic cell regions CR3 and CR4, respectively, while being spaced apart from each other with the second cell boundary CB2 interposed therebetween. However, the first lower separation mask pattern 122 may be formed as a single, integral body (e.g., including lower separation mask patterns formed on the first and second logic cell regions CR1 and CR2, which are integrally combined with each other).

[0056] The first lower separation mask pattern 122 may cover a plurality of first line mask patterns 110a (eg, four first line mask patterns 110a, as shown) arranged on the first and second logic cell regions CR1 and CR2 along the second direction D2. Figure 6A The second lower separation mask pattern 124 may cover a plurality of second line mask patterns 110b (eg, four second line mask patterns 110b, as shown) arranged along the second direction D2 on the third logic cell region CR3. Figure 6A The third lower separation mask pattern 126 may cover a plurality of second line mask patterns 110b (eg, four second line mask patterns 110b, as shown) arranged along the second direction D2 on the fourth logic cell region CR4. Figure 6AThus, different portions of the plurality of second line mask patterns 110b may be covered by the second lower separation mask patterns 124 and the third lower separation mask patterns 126. The second lower separation mask patterns 124 and the third lower separation mask patterns 126 may be spaced apart from each other at intervals that may correspond to a third width W3 of the wide double diffusion interrupt region IR2dw (e.g., as described above with reference to Figure 3A and Figure 3B In some embodiments, the second and third lower separation mask patterns 124 and 126 may have ends facing each other with the second cell boundary CB2 interposed therebetween, and the ends of the second and third lower separation mask patterns 124 and 126 may have rounded corners 124 c and 126 c, respectively. When a photoresist pattern is formed to define the second and third lower separation mask patterns 124 and 126, the rounded corners 124 c and 126 c are formed due to the characteristics of the photoresist process.

[0057] The first lower separation mask pattern 122 may expose the first line mask pattern 110a (also referred to herein as a dummy first line mask pattern 110a_DM) located on opposite sides of the first lower separation mask pattern 122 along the second direction D2. Similarly, the second lower separation mask pattern 124 and the third lower separation mask pattern 126 may expose the second line mask pattern 110b (also referred to herein as a dummy second line mask pattern 110b_DM) located on opposite sides of the second lower separation mask pattern 124 and the third lower separation mask pattern 126 along the second direction D2 and a portion of the second line mask pattern 110b between the second lower separation mask pattern 124 and the third lower separation mask pattern 126.

[0058] Reference Figure 7A 、 Figure 7B and Figure 7C , a first etching process may be performed to completely remove the dummy first line mask pattern 110a_DM and the dummy second line mask pattern 110b_DM using the lower separation mask patterns 122, 124, and 126 as etching masks. The first etching process may also remove the exposed portion of the second line mask pattern 110b from between the second lower separation mask pattern 124 and the third lower separation mask pattern 126, thereby forming an initial second hard mask pattern 110bp. Thus, the first etching process may divide each second line mask pattern 110b into initial second hard mask patterns 110bp, which are spaced apart from each other (e.g., so as to be adjacent to each other along the first direction D1) with the second cell boundary CB2 interposed therebetween. The first etching process may, for example, include an anisotropic dry etching process. The first etching process may also partially remove the upper portion of the substrate 100.

[0059] In some embodiments, a spacing may be provided between adjacent initial second hard mask patterns 110bp, and the spacing may vary along the second direction D2. For example, a spacing d1 may be provided between a pair of initial second hard mask patterns 110bp located on the outermost sides, and a spacing d2 smaller than the spacing d1 may be provided between another pair of initial second hard mask patterns 110bp. The initial second hard mask patterns 110bp may have respective ends adjacent to the second cell boundary CB2, and the ends of the initial second hard mask patterns 110bp may have shapes that conform to the shapes of the ends of the second lower separation mask pattern 124 and the third lower separation mask pattern 126. For example, the initial second hard mask patterns 110bp may have rounded ends adjacent to the corners 124c and 126c of the second lower separation mask pattern 124 and the third lower separation mask pattern 126.

[0060] Reference Figure 8A 、 Figure 8B and Figure 8C , an upper separation mask layer 130 may be formed on the entire surface of the substrate 100. The upper separation mask layer 130 may cover the first lower separation mask pattern 122, the second lower separation mask pattern 124, and the third lower separation mask pattern 126, and also fill the space therebetween. The upper separation mask layer 130 may be formed of the same material as the lower separation mask layer (e.g., an SOH layer).

[0061] Reference Figure 9A 、 Figure 9B and Figure 9C , the upper separation mask layer 130 may be patterned to form an upper separation mask pattern 132. The upper separation mask pattern 132 may include a plurality of openings exposing the lower separation mask patterns 122, 124, and 126. In one embodiment, the upper separation mask layer 130 may be patterned by a process including forming a photoresist pattern on the upper separation mask layer 130 that exposes regions where the openings OP1 and OP2 are to be formed, and then etching the upper separation mask layer 130 using the photoresist pattern as an etching mask.

[0062] In some embodiments, the openings may include a first opening OP1 that collectively exposes a portion of the first lower separation mask pattern 122 on the first and second logic cell regions CR1 and CR2, and a plurality of second openings OP2 that expose the first to third lower separation mask patterns 122, 124, and 126 on corresponding ones of the first to fourth logic cells CR1, CR2, CR3, and CR4. The first opening OP1 may be located on the first cell boundary CB1, and the second opening OP2 may be located to be spaced apart from the first and second cell boundaries CB1 and CB2.

[0063] The first opening OP1 may have a rectangular shape that crosses the first lower separation mask pattern 122 along the second direction D2. For example, the first opening OP1 may overlap four of the first line mask patterns 110a arranged along the second direction D2. A planar shape may be formed on the overlapping area between the first opening OP1 and each first line mask pattern 110a. When viewed in a top view, the first opening OP1 may have rounded corners due to the characteristics of the photolithography process. In some embodiments, the length of the first opening OP1 (e.g., measured along the second direction D2) may be adjusted to ensure that the rounded corners of the first opening OP1 do not overlap the first line mask pattern 110a. As a result, the boundary of the area where the first opening OP1 overlaps each first line mask pattern 110a may extend as a straight line. The first opening OP1 may have a width corresponding to the size of the second width W2 of the narrow double diffusion interrupt region IR2dn.

[0064] Although each of the second openings OP2 is shown as overlapping two of the first line mask patterns 110a or two of the initial second hard mask patterns 110bp, it should be appreciated that any second opening OP2 may overlap any number of first line mask patterns 110a or initial second hard mask patterns 110bp. The second openings OP2 may have various lengths. For example, each of the second openings OP2 may have a rectangular shape with rounded corners and have a major axis extending along the second direction D2. A planar shape may be formed in the first logic cell region CR1 and the second logic cell region CR2 where the first line mask pattern 110a is overlapped by the second openings OP2. Similarly, a planar shape may be formed in the third logic cell region CR3 and the fourth logic cell region CR4 where the initial second hard mask pattern 110bp is overlapped by the second openings OP2. Each of the second openings OP2 may have a width that is smaller than the width of the first opening OP1. For example, the second opening OP2 may have a size that is the same as the reference CR1. Figure 2A and Figure 2B The size of the first width W1 of the discussed single diffusion interrupt region IR2s corresponds to a width (eg, measured along the first direction D1). Alternatively, one or all of the second openings OP2 may not be provided on the logic cell regions CR1, CR2, CR3, and CR4.

[0065] Reference Figure 10A 、 Figure 10B and Figure 10C, a second etching process may be performed to remove portions of the lower separation mask patterns 122, 124, and 126 exposed by the openings OP1 and OP2 using the upper separation mask pattern 132 as an etching mask. The second etching process may be, for example, an anisotropic dry etching process. The second etching process may be performed until the top surface of the portion of the substrate 100 overlapped by the openings OP1 and OP2 is exposed. The second etching process may also remove the first line mask pattern 110a and the initial second hard mask pattern 110bp overlapped by the first opening OP1 and the second opening OP2.

[0066] The second etching process may separate the first lower separation mask pattern 122 into a first sub-separation mask pattern 122a and a second sub-separation mask pattern 122b spaced apart from each other along the first direction D1. Furthermore, each of the first line mask patterns 110a may be separated along the first direction D1, such that a first hard mask pattern 110h1 is formed over the first and second logic cell regions CR1 and CR2. As shown, the first hard mask pattern 110h1 may have various lengths. Furthermore, one or more of the initial second hard mask patterns 110bp may be separated along the first direction D1, such that a second hard mask pattern 110h2 is formed having various lengths over the third and fourth logic cell regions CR3 and CR4.

[0067] In some embodiments, when viewed in a top view, the first hard mask pattern 110h1 of the first logic cell region CR1 may have respective ends adjacent to the first cell boundary CB1 and aligned with each other along the second direction D2. Similarly, when viewed in a top view, the first hard mask pattern 110h1 of the second logic cell region CR2 may have respective ends adjacent to the first cell boundary CB1 and aligned with each other along the second direction D2. Thus, the same spacing may be provided between the first hard mask patterns 110h1 adjacent to each other along the first direction D1 with the first cell boundary CB1 interposed therebetween. When viewed in a top view, the second hard mask pattern 110h2 of the third logic cell region CR3 may have respective ends adjacent to the second cell boundary CB2, and one or more of the ends may be offset along the first direction D1. In other words, the third logic cell region CR3 may include a second hard mask pattern 110h2 located outermost and having an end relatively far from the second cell boundary CB2, and may further include an adjacent second hard mask pattern 110h2 positioned along the second direction D2 and having an end relatively close to the second cell boundary CB2. Similarly, when viewed in a top plan view, the second hard mask pattern 110h2 of the fourth logic cell region CR4 may have respective ends adjacent to the second cell boundary CB2, and one or more of the ends may be offset along the first direction D1. In other words, the fourth logic cell region CR4 may include a second hard mask pattern 110h2 located outermost and having an end relatively far from the second cell boundary CB2, and may further include an adjacent second hard mask pattern 110h2 positioned along the second direction D2 and having an end relatively close to the second cell boundary CB2. Therefore, a gap may be provided between second hard mask patterns 110h2 adjacent to each other along the first direction D1 with the second cell boundary CB2 interposed therebetween, and such a gap may vary depending on their positions along the second direction D2.

[0068] After the second etching process, the upper separation mask pattern 132 may remain in the space between the separation mask patterns 122a, 122b, 124, and 126. The depth of each of the openings OP1 and OP2 may extend (e.g., along the third direction D3) and be redefined to include a bottom surface corresponding to the top surface of the substrate 100.

[0069] Reference Figure 11A 、 Figure 11B and Figure 11C , the separation mask patterns 122a, 122b, 124, and 126 may be removed. For example, an ashing process may be performed to remove the separation mask patterns 122a, 122b, 124, and 126.

[0070] By performing a third etching process using the first and second hard mask patterns 110h1 and 110h2 as etching masks, trenches T1, T2, T3, and T4 may be formed to define the active pattern AP. The third etching process may be, for example, an anisotropic dry etching process. The trenches T1, T2, T3, and T4 may include first and second trenches T1 and T2 defining relatively long sidewalls of the active pattern AP, and third and fourth trenches T3 and T4 defining relatively short sidewalls of the active pattern AP.

[0071] As in Figure 11B and Figure 11C As best shown in FIG, when measured along the second direction D2, the first trench T1 may have a width substantially the same as or smaller than the width of the second trench T2. The second trench T2 may have various widths along the second direction D2. The third trench T3 may have a width substantially the same as or smaller than the width of the fourth trench T4, when measured along the first direction D1. The fourth trench T4 may have various widths along the first direction D1. For example, the fourth trench T4 between the first logic cell region CR1 and the second logic cell region CR2 may have a width smaller than the width of the fourth trench T4 between the third logic cell region CR3 and the fourth logic cell region CR4. In some embodiments, each of the trenches T1, T2, T3, and T4 may be formed to have a width that decreases as the distance from the top surface of the substrate 100 gradually increases downward. Each of the active patterns AP may be formed to have a shape whose width decreases as the distance toward the top surface of the substrate 100 gradually decreases. Each of the widths of the trenches T1 , T2 , T3 , and T4 discussed above may be considered to be a maximum width of the trenches T1 , T2 , T3 , and T4 .

[0072] The lower portions of the trenches T1, T2, T3, and T4 may be filled to form a device isolation layer, and the upper portion of the active pattern AP is exposed through the device isolation layer. The device isolation layer may include a narrow first separation region IR1n in the first trench T1, a wide first separation region IR1w in the second trench T2, a single diffusion interruption region IR2s in the third trench T3, and double diffusion interruption regions IR2dn and IR2dw in the fourth trench T4. Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3B The description discussed may be identically or similarly applicable to the widths of the separation regions IR1n and IR1w (i.e., the first separation regions) and the diffusion interruption regions IR2s, IR2dn, and IR2dw (i.e., the second separation regions), and may also be applicable to the shape and arrangement of the ends of the active pattern AP adjacent thereto, so repeated descriptions will be omitted for the sake of brevity.

[0073] In one embodiment, the device isolation layer may be formed by a process including forming an insulating layer to fill the trenches T1, T2, T3, and T4, and then planarizing and etching the insulating layer to expose the upper portion of the active pattern AP. The exposed upper portion of the active pattern AP may also be defined as an active fin AF hereinafter. The device isolation layer may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a low-k dielectric layer, and the like.

[0074] As discussed above, according to exemplary embodiments of the present inventive concept, an active pattern can be formed by a process including patterning a line mask pattern to form a hard mask pattern that defines the planar position and shape of the active pattern, and etching an upper portion of a substrate using the hard mask pattern as an etching mask to form a trench that defines the active pattern. Patterning of the line mask pattern may include a patterning process for removing the line mask pattern from a region where a double diffusion interruption region is to be formed (hereinafter referred to as a first patterning process) and another patterning process for removing the line mask pattern from a region where a single diffusion interruption region is to be formed (hereinafter referred to as a second patterning process).

[0075] The second patterning process can be performed using an upper separation mask pattern having an opening that overlaps the line mask pattern in the area where the single diffusion interrupt region will be formed. In this case, the length of the opening can be adjusted to form a planar shape in which the opening overlaps the line mask pattern. As a result, the active pattern can be formed with ends adjacent to the single diffusion interrupt region and aligned with each other along the width direction of the active pattern.

[0076] The first patterning process can be performed using lower separation mask patterns that are adjacent to each other and have cell boundaries interposed therebetween as etching masks. In this case, the lower separation mask patterns can be formed to have respective ends facing each other and having rounded corners (e.g., due to the characteristics of the photolithography process involved). As a result, the active pattern adjacent to the double diffusion interruption region can be formed to have respective ends adjacent to the double diffusion interruption region and offset along the length direction of the active pattern. Due to the above reasons, it will be difficult to subsequently form a gate pattern (i.e., a dummy gate pattern) that overlaps the end of the active pattern adjacent to one side of the double diffusion interruption region. Specifically, when the double diffusion interruption region is formed to have a minimum width, the above problem will be more serious due to insufficient process margin. In the subsequent process, the source / drain region can be formed to have a shape that depends on whether the dummy gate pattern overlaps the end of the active pattern adjacent to the side of the double diffusion interruption region. Therefore, if the dummy gate pattern does not overlap the end of the active pattern adjacent to the side of the double diffusion interruption region, the reliability of the semiconductor device will be reduced.

[0077] According to an exemplary embodiment of the present invention, when the double diffusion interrupt region is formed to have a minimum width (i.e., when a narrow double diffusion interrupt region is formed), a second patterning process can be performed so that the line mask pattern is removed from the region where the double diffusion interrupt region will be formed. In other words, the upper separation mask pattern can have an opening that overlaps the line mask pattern formed on the region where the double diffusion interrupt region will be formed. Therefore, the active pattern adjacent to the narrow double diffusion interrupt region can be formed to have respective ends aligned along the width direction of the active pattern. Then, a dummy gate pattern can be easily formed that overlaps the end of the active pattern adjacent to the side of the double diffusion interrupt region. As a result, the semiconductor device can have improved reliability due to the improved distribution of its electrical characteristics.

[0078] Methods for fabricating a semiconductor device including an active pattern according to some exemplary embodiments of the inventive concept will be further provided below.

[0079] Reference Figure 12A 、 Figure 12B and Figure 12C , the sacrificial structures 140 may be formed to cross the active pattern AP. The sacrificial structures 140 may extend in the second direction D2 and be equally spaced apart from each other in the first direction D1. Each of the sacrificial structures 140 may include a sacrificial pattern 142 and a gate mask pattern 144 sequentially stacked on the substrate 100.

[0080] In some embodiments, one or more of the sacrificial structures 140 may overlap the second separation regions IR2s, IR2dn, and IR2dw. For example, the single diffusion interrupt region IR2s may be overlapped by a single sacrificial structure 140 spaced apart from an adjacent end of the active pattern AP. The narrow double diffusion interrupt region IR2dn may be overlapped by two sacrificial structures 140. One of the two sacrificial structures 140 may jointly overlap an end of the active pattern AP of the first logic cell region CR1 adjacent to the narrow double diffusion interrupt region IR2dn. The other of the two sacrificial structures 140 may jointly overlap an end of the active pattern AP of the second logic cell region CR2 adjacent to the narrow double diffusion interrupt region IR2dn.

[0081] The wide double diffusion break region IR2dw may be overlapped by three sacrificial structures 140. One of the three sacrificial structures 140 may collectively overlap an end portion of the active pattern AP of the third logic cell region CR3 adjacent to the wide double diffusion break region IR2dw. Another of the three sacrificial structures 140 may collectively overlap an end portion of the active pattern AP of the fourth logic cell region CR4 adjacent to the wide double diffusion break region IR2dw. Yet another of the three sacrificial structures 140 may be disposed on the wide double diffusion break region IR2dw at a position overlapping the second cell boundary CB2.

[0082] The sacrificial structure 140 is formed by a process including forming a sacrificial layer (not shown) to cover the entire surface of the substrate 100, forming a gate mask pattern 144 on the sacrificial layer, and patterning the sacrificial layer using the gate mask pattern 144 as an etching mask to form a sacrificial pattern 142. The sacrificial layer may include, for example, polysilicon. The gate mask pattern 144 may include, for example, silicon nitride or silicon oxynitride.

[0083] Gate spacers SP may be formed on sidewalls of the sacrificial structure 140. The gate spacers SP may be formed by conformally forming a spacer layer to cover the sacrificial structure 140 and performing an overall anisotropic etching process on the substrate 100. The spacer layer may be formed using, for example, at least one of SiO2, SiCN, SiCON, SiN, etc. Alternatively, the spacer layer may be formed as a multilayer structure including, for example, at least one of SiO2, SiCN, SiCON, SiN, etc.

[0084] Reference Figure 13A 、 Figure 13B and Figure 13C , the recessed regions RS1 and RS2 may be formed on opposite sides of the sacrificial structure 140. In one embodiment, the recessed regions RS1 and RS2 may be formed by performing an isotropic and / or anisotropic etching process using the sacrificial structure 140 as an etching mask to etch the upper portion of the active fin AF. For example, the recessed regions RS1 and RS2 may include a first recessed region RS1 having a U-shaped cross-sectional shape between adjacent sacrificial structures 140 and a second recessed region RS2 adjacent to the single diffusion interruption region IR2s. During the formation of the recessed regions RS1 and RS2, the active fin AF may be etched to remove its end portion adjacent to the single diffusion interruption region IR2s. Therefore, the second recessed region RS2 may be formed without a U-shaped cross-sectional shape.

[0085] Reference Figure 14A 、 Figure 14B and Figure 14CSource / drain regions SD1 and SD2 may be formed on opposite sides of the active pattern AP. In one embodiment, the source / drain regions SD1 and SD2 may be formed by performing a selective epitaxial growth process, wherein the active fins AF defining the recessed regions RS1 and RS2 and any portions of the active pattern AP exposed by the recessed regions RS1 and RS2 serve as a seed layer. That is, the source / drain regions SD1 and SD2 may include an epitaxial layer. For example, each of the source / drain regions SD1 and SD2 may include at least one material, such as silicon germanium (SiGe), silicon (Si), silicon carbide (SiC), etc., epitaxially grown from the active fins AF and / or the active pattern AP exposed by the recessed regions RS1 and RS2. Therefore, the source / drain regions SD1 and SD2 may apply compressive strain or tensile strain (also generally referred to herein as "epitaxial strain" or "mismatch strain," as known in the art) to the portion of the active fins AF underlying the sacrificial structure 140 (such portion also referred to herein as the channel region). Simultaneously with the epitaxial growth process or after the epitaxial growth process, the source / drain regions SD1 and SD2 may be doped with impurities. For example, the source / drain regions SD1 and SD2 may be doped with p-type or n-type impurities.

[0086] The source / drain regions SD1 and SD2 may include a first source / drain region SD1 located within the first recessed region RS1 and a second source / drain region SD2 located within the second recessed region RS2. In some embodiments, the first source / drain region SD1 may have an uppermost surface higher than an uppermost surface of the active fin AF, and the second source / drain region SD2 may have an uppermost surface lower than an uppermost surface of the active fin AF. Each of the second source / drain regions SD2 may have an inclined surface SD2_S that slopes downward toward the adjacent single diffusion interrupt region IR2s. For example, the inclined surface SD2_S may have a (111) crystal plane.

[0087] In the case where the end portion of the active pattern AP is adjacent to the narrow double-diffusion interrupt region IR2dn but is not overlapped by the sacrificial structure 140, the first recessed region RS1 (also referred to herein as the third recessed region) adjacent to such an end portion can be formed to have the same shape as the second recessed region RS2. A source / drain region (hereinafter referred to as the third source / drain region) can then be formed within the third recessed region, which has the same shape as the source / drain region SD2. In this embodiment, the third source / drain region can have a shape different from that of the adjacent source / drain region (i.e., the first source / drain region SD1), resulting in a degradation in the characteristic profile of the semiconductor device. For example, the electrical characteristics of the semiconductor device can be degraded due to the reduced strain applied to the channel region from the third source / drain region and / or contact failure between the source / drain region and the source / drain contact formed in a subsequent process. However, these problems can be avoided by ensuring that the ends of the active pattern AP adjacent to the narrow double diffusion interrupt region IR2dn are overlapped by the sacrificial structure 140 (eg, in the manner discussed in the above embodiments), and the reliability of the semiconductor device can be improved.

[0088] The first interlayer dielectric layer 150 may be formed to cover the sacrificial structure 140 and the source / drain regions SD1 and SD2. For example, the first interlayer dielectric layer 150 may include a silicon oxide layer and may be formed by a flowable chemical vapor deposition (FCVD) process.

[0089] The first interlayer dielectric layer 150 may be planarized until the top surface of the sacrificial pattern 142 is exposed. The planarization of the first interlayer dielectric layer 150 may be performed using an etch-back process or a chemical mechanical polishing process. Through the planarization process, the gate mask pattern 144 may be removed to expose the top surface of the sacrificial pattern 142. The planarization process may also remove the upper portion of the gate spacer SP.

[0090] Once exposed, the sacrificial pattern 142 can be replaced with a gate pattern GP, ​​each including a gate dielectric pattern GD and a gate electrode GE. Replacing the sacrificial pattern 142 with the gate pattern GP can include selectively removing the sacrificial pattern 142 to form a gate region that exposes the active pattern AP between the gate spacers SP, and then sequentially forming a gate dielectric layer and a gate electrode layer in the gate region. For example, the gate dielectric layer can include at least one of hafnium oxide, hafnium silicate, zirconium oxide, zirconium silicate, etc., or any combination thereof. The gate electrode layer can include a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.), a metal (e.g., aluminum, tungsten, etc.), etc., or any combination thereof. The gate pattern GP overlapping the second separation regions IR2s, IR2dn, and IR2dw can be referred to herein as a dummy gate pattern GP_DM.

[0091] Alternatively, the gate electrode GE may be recessed at its upper portion, and a capping pattern (not shown) may be further formed on the recessed gate electrode GE. That is, each of the gate patterns GP may include a gate dielectric pattern GD, a gate electrode GE, and a capping pattern (not shown). For example, the capping pattern (not shown) may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), etc., or any combination thereof.

[0092] Reference Figure 15A 、 Figure 15B and Figure 15C A second interlayer dielectric layer 160 may be formed to cover the first interlayer dielectric layer 150 and the gate pattern GP. The second interlayer dielectric layer 160 may include, for example, at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a low dielectric layer, and the like.

[0093] Source / drain contacts 170a and 170b may be formed through the first and second interlayer dielectric layers 150 and 160 and connected to the source / drain regions SD1 and SD2. Each of the source / drain contacts 170a and 170b may extend in the second direction D2 across at least two active patterns AP. The source / drain contacts 170a and 170b may include a first source / drain contact 170a commonly connected to a plurality of first source / drain regions SD1 disposed on one side of the gate pattern GP, ​​and a second source / drain contact 170b commonly connected to a plurality of second source / drain regions SD2 disposed on the opposite side of the gate pattern GP. The source / drain regions commonly connected to a single source / drain contact may constitute a single multi-fin transistor. To facilitate connection to the second source / drain regions SD2, the second source / drain contact 170b may have a bottom surface that is lower than the bottom surface of the first source / drain contact 170a. The source / drain contacts 170a and 170b may include at least one of an impurity-doped polysilicon layer, a metal layer (eg, tungsten, titanium, tantalum, etc.), a metal silicide layer (eg, titanium silicide, tungsten silicide, etc.), or any combination thereof.

[0094] Although not shown in the drawings, interconnection lines may be formed on the second interlayer dielectric layer 160 and electrically connected to the source / drain contacts 170 a and 170 b .

[0095] According to exemplary embodiments of the present inventive concept, the active pattern can be formed with respective ends adjacent to a narrow double-diffused interrupt region having a minimum width and aligned in the width direction of the active pattern. The dummy gate pattern can collectively overlap the ends of the active pattern adjacent to the narrow double-diffused interrupt region. As a result, substantially identical shapes can be achieved on the source / drain regions formed between the dummy gate pattern and its adjacent gate pattern. Consequently, the distribution of electrical characteristics can be improved, thereby enhancing the reliability of the semiconductor device.

[0096] Although the present disclosure has been described in conjunction with the embodiments shown in the accompanying drawings, it is not limited thereto and it will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the invention as described in the claims.

[0097] This application claims priority from Korean Patent Application No. 10-2016-0060334, filed on May 17, 2016, which is hereby incorporated by reference herein in its entirety.

Claims

1. A semiconductor device comprising: a substrate including a first cell region and a second cell region adjacent to each other along a first direction with a first cell boundary interposed therebetween and extending along a second direction crossing the first direction; first active patterns arranged on the first cell region and the second cell region along the second direction, each of the first active patterns extending along the first direction but not crossing the first cell boundary; a device isolation layer on the substrate and exposing an upper portion of the first active pattern, the device isolation layer comprising: a first double diffusion interruption region disposed on the first cell boundary and between pairs of first active patterns located on different cell regions and adjacent to each other along the first direction, the first active patterns being at least two pairs; and a first single diffusion interruption region provided on at least one selected from the group consisting of the first unit region and the second unit region and between a pair of first active patterns located on the same unit region and adjacent to each other along the first direction; and a first gate pattern crossing the first active pattern; and a first source / drain region in an upper portion of the first active pattern between the first gate pattern and the first single diffusion interruption region, wherein the first source / drain region includes an epitaxial layer and has an inclined surface extending downward from the first gate pattern to the first single diffusion interruption region. 2 . The semiconductor device according to claim 1 , wherein the first double diffusion interrupt region extends along the second direction, and wherein a width of the first double diffusion interrupt region measured along the first direction is constant along the second direction. 3 . The semiconductor device according to claim 1 , wherein two of the first gate patterns overlap the first double diffusion interruption region and end portions of the at least two pairs of first active patterns located on different cell regions. 4 . The semiconductor device according to claim 1 , wherein one of the first gate patterns overlaps the first single diffusion interruption region and is spaced apart from ends of the pair of first active patterns on the same cell region.

5. The semiconductor device according to claim 1 , wherein the substrate further comprises a third cell region and a fourth cell region adjacent to each other along the first direction with the second cell boundary interposed therebetween; second active patterns arranged on the third cell region and the fourth cell region along the second direction, each of the second active patterns extending along the first direction but not crossing the second cell boundary; and A second gate pattern intersects the second active pattern.

6. The semiconductor device according to claim 5, wherein the device isolation layer further comprises: a second double diffusion interruption region disposed on the second cell boundary and between pairs of second active patterns located on different cell regions and adjacent to each other along the first direction, the second active patterns being at least two pairs; The second double diffusion interrupt region extends along the second direction, and the width of the second double diffusion interrupt region measured along the first direction varies along the second direction. 7 . The semiconductor device according to claim 6 , wherein a maximum width of the second double diffusion interrupt region is greater than a width of the first double diffusion interrupt region. 8 . The semiconductor device according to claim 7 , wherein a minimum width of the second double diffusion interrupt region is greater than the width of the first double diffusion interrupt region.

9. The semiconductor device according to claim 6, wherein the second active pattern comprises outermost active patterns and at least one inner active pattern interposed between the outermost active patterns along the second direction, An end portion of the at least one inner active pattern is closer to the second cell boundary than an end portion of the outermost active pattern.

10. A semiconductor device comprising: a substrate including a first cell region and a second cell region adjacent to each other along a first direction, a cell boundary interposed between the first cell region and the second cell region and extending along a second direction crossing the first direction; active patterns arranged on the first cell region and the second cell region along the second direction, each of the active patterns extending along the first direction but not crossing the cell boundary; a device isolation layer on the substrate and exposing a portion of the active pattern, wherein the exposed portion of the active pattern includes an active fin, and wherein the device isolation layer includes a double diffusion interruption region and a single diffusion interruption region, the double diffusion interruption region being disposed on the cell boundary and between pairs of active patterns located on the first cell region and the second cell region and adjacent to each other along the first direction, and the single diffusion interruption region being disposed on the first cell region and between at least two pairs of active patterns located on the first cell region and adjacent to each other along the first direction, the active patterns being at least two pairs; a gate pattern arranged along the first direction and crossing the active fin along the second direction; as well as a first source / drain region in an upper portion of the active pattern between the gate pattern and the single diffusion interruption region, wherein the first source / drain region includes an epitaxial layer and has an inclined surface extending downward from the gate pattern to the single diffusion interruption region.

11. The semiconductor device according to claim 10, further comprising: Second source / drain regions are arranged in upper portions of the active patterns between adjacent ones of the gate patterns, wherein at least one of the second source / drain regions includes the epitaxial layer and has a top surface parallel to a top surface of at least one of the active patterns.

Images