Semiconductor structure and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a substrate and a gate stack structure on the substrate; wherein the gate stack structure comprises: a high-K dielectric layer; a first barrier layer in contact with the high-K dielectric layer; a work function layer on a side of the high-K dielectric layer away from the substrate; and a gate electrode layer on a side of the work function layer away from the substrate; wherein the first barrier layer comprises the same metal element as the high-K dielectric layer.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the field of Dynamic Random Access Memory (DRAM) manufacturing, as the size continues to shrink, the silicon dioxide (SiO2) dielectric layer is continuously thinned, resulting in non-negligible gate leakage. Therefore, a high-k dielectric layer is introduced during the fabrication of the device dielectric layer. Summary of the Invention

[0003] This application provides a semiconductor structure and a method for forming the same.

[0004] In a first aspect, embodiments of this application provide a semiconductor structure, including: a substrate and a gate stack structure located on the substrate; wherein the gate stack structure includes: a high-k dielectric layer; a first barrier layer in contact with the high-k dielectric layer; a work function layer located on the side of the high-k dielectric layer away from the substrate; and a gate electrode layer located on the side of the work function layer away from the substrate; wherein the first barrier layer contains the same metal element as the high-k dielectric layer.

[0005] In some embodiments, the first barrier layer is located on the side of the high-k dielectric layer closer to the substrate.

[0006] Thus, by setting a first barrier layer between the high-k dielectric layer and the substrate, the transport of O to the substrate can be blocked, thereby preventing the reaction between the high-k dielectric layer and the substrate to generate oxygen vacancies and silicon dioxide, thereby reducing the threshold voltage drift and improving the stability of the device; at the same time, it can also reduce the growth of the insulating layer.

[0007] In some embodiments, the system further includes a second barrier layer located on the side of the high-k dielectric layer away from the substrate and in contact with the high-k dielectric layer.

[0008] Thus, by setting a first barrier layer and a second barrier layer in contact with the high-k dielectric layer, not only can the transport of O from the high-k dielectric layer to the substrate be blocked, reducing O transport, but it can also prevent oxygen in the air or oxygen brought in by subsequent manufacturing processes from entering the gate electrode layer, work function layer and high-k dielectric layer. This is more conducive to preventing the reaction between the high-k dielectric layer and the substrate to generate oxygen vacancies and silicon dioxide, further reducing threshold voltage drift and improving device stability; at the same time, it can also further reduce the growth of the insulating layer.

[0009] In some embodiments, the first barrier layer is located on the side of the high-k dielectric layer away from the substrate.

[0010] In some embodiments, the first barrier layer comprises a lanthanum hafnium oxide layer, and the second barrier layer comprises a lanthanum hafnium oxide layer.

[0011] In some embodiments, the high-K dielectric layer includes at least one of a silicon hafnium oxide layer, a silicon oxynitride hafnium layer, a tantalum hafnium oxide layer, a titanium hafnium oxide layer, and a zirconium hafnium oxide layer.

[0012] In some embodiments, the gate electrode layer includes a titanium nitride layer.

[0013] In some embodiments, the gate stack structure further includes an insulating layer formed on the substrate, wherein the insulating layer includes at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0014] Thus, on the one hand, the stacked structure formed by the insulating layer and the subsequently formed high-k gate dielectric layer serves as the gate dielectric layer; on the other hand, the insulating layer provides a good interface foundation for the subsequent formation of the high-k gate dielectric layer, thereby improving the quality of the formed high-k gate dielectric layer, reducing the interface state density between the high-k gate dielectric layer and the substrate, and avoiding the adverse effects caused by direct contact between the high-k gate dielectric layer and the substrate.

[0015] In some embodiments, the system further includes: sidewall structures located on both sides of the gate stack structure; wherein the sidewall structures include nitrided layers.

[0016] In some embodiments, the thickness of the high-k dielectric layer is 20 to The thickness of the first barrier layer is 2 to The thickness of the gate electrode layer is 2 to

[0017] In some embodiments, the thickness of the insulating layer is 10 to

[0018] In a second aspect, embodiments of this application provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a high-k dielectric layer and a first barrier layer in contact with the high-k dielectric layer on the substrate; forming a work function layer on the side of the high-k dielectric layer away from the substrate; forming a gate electrode layer on the work function layer to form a gate stack structure on the substrate; wherein the first barrier layer comprises the same metal element as the high-k dielectric layer.

[0019] In some embodiments, forming a high-k dielectric layer on the substrate and a first barrier layer in contact with the high-k dielectric layer includes: forming a first barrier layer in contact with the substrate on the substrate; forming the high-k dielectric layer in contact with the first barrier layer on the first barrier layer; forming a work function layer on the side of the high-k dielectric layer away from the substrate includes: forming the work function layer in contact with the high-k dielectric layer on the high-k dielectric layer.

[0020] In some embodiments, the method further includes: forming a second barrier layer on the high-K dielectric layer in contact with the high-K dielectric layer; forming a work function layer on the side of the high-K dielectric layer away from the substrate includes: forming the work function layer on the second barrier layer in contact with the second barrier layer.

[0021] In some embodiments, forming a high-K dielectric layer on the substrate and a first barrier layer in contact with the high-K dielectric layer includes: forming a high-K dielectric layer in contact with the substrate on the substrate; forming a first barrier layer in contact with the high-K dielectric layer on the high-K dielectric layer; forming a work function layer on the side of the high-K dielectric layer away from the substrate includes: forming the work function layer in contact with the first barrier layer on the first barrier layer.

[0022] In some embodiments, the first barrier layer includes a lanthanum hafnium oxide layer, and the second barrier layer includes a lanthanum hafnium oxide layer; the method of forming the lanthanum hafnium oxide layer includes: forming a lanthanum oxide layer on the substrate or the high-k dielectric layer; forming a hafnium dioxide layer on the lanthanum oxide layer; and annealing to form the lanthanum hafnium oxide layer.

[0023] In some embodiments, the high-K dielectric layer includes at least one of a silicon hafnium oxide layer, a silicon oxynitride hafnium layer, a tantalum hafnium oxide layer, a titanium hafnium oxide layer, and a zirconium hafnium oxide layer.

[0024] In some embodiments, the gate electrode layer includes a titanium nitride layer.

[0025] In some embodiments, the thickness of the high-k dielectric layer is 20 to The thickness of the first barrier layer is 2 to The thickness of the gate electrode layer is 2 to

[0026] In some embodiments, the method further includes forming an insulating layer on the substrate, wherein the insulating layer comprises at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0027] In some embodiments, the thickness of the insulating layer is 10 to

[0028] In some embodiments, the method further includes: forming sidewall structures on both sides of the gate stack structure; wherein the sidewall structures include nitrided layers.

[0029] The semiconductor structure provided in this application includes: a substrate and a gate stack structure located on the substrate; wherein the gate stack structure includes: a high-k dielectric layer; a first barrier layer in contact with the high-k dielectric layer; a work function layer located on the side of the high-k dielectric layer away from the substrate; and a gate electrode layer located on the side of the work function layer away from the substrate; wherein the first barrier layer contains the same metal element as the high-k dielectric layer. In this way, firstly, in the gate stack structure, the high-k dielectric layer and the barrier layer are in contact, which on the one hand reduces the formation of oxygen vacancies in the high-k dielectric layer, thereby reducing threshold voltage drift and improving device stability; on the other hand, it also reduces the growth of the insulating layer. Secondly, the barrier layer in the gate stack structure also plays a certain role in regulating the metal work function, thereby reducing the threshold voltage of the device and reducing the power consumption of the device. Furthermore, the semiconductor structure of this application only adds a barrier layer, making the structure relatively simple and adaptable to current process designs; at the same time, the first barrier layer contains the same metal element as the high-k dielectric layer, which can effectively reduce the fabrication process and improve efficiency. Attached Figure Description

[0030] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0031] Figure 1a This is a schematic diagram of the composition of an HKMG structure;

[0032] Figure 1b This is a schematic diagram of the composition structure of a semiconductor structure based on the HKMG structure.

[0033] Figure 1c This is a schematic diagram of the oxygen transport direction between HKMG dielectric layers.

[0034] Figure 1d A schematic diagram of the reaction that occurs when oxygen enters the HKMG;

[0035] Figure 2a and Figure 2b This is a schematic diagram of a method for forming a semiconductor structure provided in an embodiment of this application;

[0036] Figures 2c to 2e This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of this application;

[0037] Figure 3a This is a schematic diagram of a method for forming a semiconductor structure provided in an embodiment of this application;

[0038] Figures 3b to 3cThis is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of this application;

[0039] Figure 4a This is a schematic diagram of a method for forming a semiconductor structure provided in an embodiment of this application;

[0040] Figures 4b to 4d This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of this application;

[0041] Figure 5a This is a schematic diagram of a method for forming a semiconductor structure provided in an embodiment of this application;

[0042] Figure 5b This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of this application. Detailed Implementation

[0043] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0045] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] The high-k dielectric layer in a high-k metal gate (HKMG) contains a large number of oxygen vacancies, which affect the electrical parameters and / or electrical performance of the HK device. At the same time, the presence of oxygen vacancies further enhances the growth of the surface silicon dioxide layer.

[0049] To better understand the semiconductor structures provided in the embodiments of this application, the HKMG structure and the semiconductor structure formed based on the HKMG structure are explained and described. For example... Figure 1a and Figure 1b As shown, the semiconductor structure includes a high-k metal gate structure 100, a substrate 105, a lightly doped drain (LDD) structure 106, a halo ring 107, and source / drain regions 108.

[0050] The high-K metal gate structure 100 includes an insulating layer 101, a high-K dielectric layer 102, a work function layer 103, and a gate electrode layer 104. The insulating layer 101 includes a SiO2 layer, the high-K dielectric layer 102 includes a hafnium dioxide (HfO2) layer, the work function layer 103 includes a lanthanum oxide (La2O3) layer, and the gate electrode layer 104 includes a titanium nitride (TiN) layer.

[0051] from Figure 1a and Figure 1b It can be seen that the substrate 105 is in contact with the insulating layer 101, and the insulating layer 101 is in contact with the high-K dielectric layer 102. Therefore, the reaction process described in formula (1) may occur in the high-K dielectric layer of HKMG.

[0052] HfO2 + 1 / 2Si → V O 2+ +2e-+1 / 2SiO2 (1);

[0053] like Figure 1c As shown, substrate 105 can be a silicon substrate, and substrate 105 is in contact with high-k dielectric layer 102. Metal gate 109 (including work function layer and gate electrode layer) is in contact with high-k dielectric layer 102. Here, A represents the oxygen transport direction, and B represents the electron transport direction.

[0054] The reaction according to formula (1) occurs in the high-k dielectric layer 102, resulting in the transport of electrons and O. O in the high-k dielectric layer 102 is transported to the substrate 105, leaving many oxygen vacancies (Vo) in the high-k dielectric layer 102. 2+ Most electrons will be transported to the metal gate 109, and only a small number of electrons will be transported to the substrate 105. This will reduce the carrier concentration on the channel surface and reduce the effective work function, thereby reducing the electrical characteristics of the circuit.

[0055] In addition, see Figure 1d In subsequent processes, oxygen from the air will enter the metal grid and undergo a reaction as shown in formula (2) to generate O. M Vo in high-k dielectric layer X (Oxygen vacancies) will combine with oxygen O2 that has entered the metal gate. M The reaction shown in equation (3) occurs, generating interstitial oxygen O. O X Oxygen filling the gap O X The reaction shown in equation (4) will continue to occur, generating oxygen vacancies and silicon dioxide (SiO2). X This forms a SiO2 layer on the surface of the silicon substrate.

[0056] 1 / 2O2(g)=O M (2);

[0057] V O X +O M =O O X (3);

[0058] O O X =V O X +SiO x (4).

[0059] Among them, O M This represents oxygen entering the metal grid; O O X Vo represents interstitial oxygen; X This indicates an oxygen vacancy.

[0060] The presence of numerous oxygen vacancies in the high-k dielectric layer is detrimental to the threshold voltage and stability of HK devices. Excessive oxygen vacancies lead to Fermi pinning at the interface, which increases the threshold voltage and reduces the switching speed. Simultaneously, the presence of oxygen vacancies acts as a medium for oxygen transport, further enhancing the growth of the surface SiO2 layer and affecting its thickness. This impacts the equivalent oxide thickness (EOT), increasing the threshold voltage and power consumption, and ultimately making the overall device performance uncontrollable. These are all problems that need to be addressed in HKMG device development.

[0061] Based on an understanding of the HK oxygen transport path, this application provides a method for forming a semiconductor structure. (See also...) Figure 2a The method includes steps S201 to S204, wherein:

[0062] Step S201, provide a substrate;

[0063] Step S202: A high-k dielectric layer and a first barrier layer in contact with the high-k dielectric layer are formed on the substrate; wherein the first barrier layer contains the same metal element as the high-k dielectric layer.

[0064] Here, step S202 can include the following three cases:

[0065] Scenario 1: A high-k dielectric layer is formed on the substrate, and a first barrier layer is formed on the high-k dielectric layer; therefore, the first barrier layer that is finally formed is in contact with the upper surface of the high-k dielectric layer.

[0066] Scenario 2: A first barrier layer is formed on the substrate, and a high-k dielectric layer is formed on the first barrier layer; therefore, the first barrier layer that is finally formed is in contact with the lower surface of the high-k dielectric layer.

[0067] Scenario 3: A first barrier layer is formed on the substrate, a high-k dielectric layer is formed on the first barrier layer, and a first barrier layer is formed on the high-k dielectric layer; therefore, the first barrier layer that is finally formed is in contact with both the upper and lower surfaces of the high-k dielectric layer.

[0068] Step S203: A function layer is formed on the side of the high-k dielectric layer away from the substrate;

[0069] Step S204: A gate electrode layer is formed on the work function layer to form a gate stack structure on the substrate.

[0070] Here, the gate stack structure can be an HKMG structure.

[0071] The semiconductor structure formation method provided in this application includes a substrate; a high-k dielectric layer and a first barrier layer in contact with the high-k dielectric layer are formed on the substrate; a work function layer is formed on the side of the high-k dielectric layer away from the substrate; and a gate electrode layer is formed on the work function layer to form a gate stack structure on the substrate. The first barrier layer contains the same metal element as the high-k dielectric layer. In this way, firstly, by using the barrier layer to block oxygen transport, on the one hand, the formation of oxygen vacancies in the high-k dielectric layer can be reduced, thereby reducing threshold voltage drift and improving device stability; on the other hand, the growth of the insulating layer can also be reduced. Secondly, the first barrier layer also plays a certain role in regulating the metal work function, thereby reducing the device threshold voltage, reducing device power consumption, and further optimizing device performance. Furthermore, the semiconductor structure of this application only adds a barrier layer, making the structure relatively simple and adaptable to current process designs. At the same time, the first barrier layer contains the same metal element as the high-k dielectric layer, which can effectively reduce the fabrication process and improve efficiency.

[0072] In this embodiment, the substrate may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0073] In some embodiments, the substrate may include a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer (such as a silicon layer on a silicon-germanium layer) situated on top of another different type of semiconductor layer. The substrate may include various doped regions doped with a P-type dopant such as boron or boron difluoride (BF2), an N-type dopant such as phosphorus or arsenic, or combinations thereof. The doped regions may be formed on the semiconductor substrate, in a P-well structure, in an N-well structure, in a double-well structure, or using a bump structure to form the doped regions.

[0074] Since HfO2 has a dielectric constant of approximately 25 and a band gap of 5.9 eV, and its conduction band offset from silicon is 1.5 eV, the charge carriers are insufficient to overcome the 1.5 eV barrier height to form a gate leakage current. Due to its wide band gap, high dielectric constant, and high stability at the Si interface, HfO2 is typically chosen as the high-k dielectric layer. In this embodiment, the high-k dielectric layer may include at least one hafnium-based material layer, such as an HfO2 layer, a HfSiO layer, a HfSiON layer, a HfTaO layer, a HfTiO layer, or a HfZrO layer.

[0075] Deposition methods for high-k dielectric layers can include chemical vapor deposition (CVD), such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), and plasma-enhanced chemical vapor deposition (PECVD).

[0076] The method of forming the work function layer may include at least one of the following: including ALD, PEALD, CVD, PECVD, PVD and / or combinations thereof, which can deposit to form a single work function layer or deposit to form a multi-layer work function layer.

[0077] The method for forming the gate electrode layer may include at least one of the following: physical vapor deposition (PVD), CVD, atomic layer deposition (ALD), PECVD, remote plasma chemical vapor deposition (RPCVD), metal-organic chemical vapor deposition (MOCVD), sputtering, plating, or other suitable methods.

[0078] The first barrier layer may include a lanthanum hafnium oxide layer, for example, it may contain LaHfO. x Material layer.

[0079] The work function layer can be made of N-type and / or P-type work function materials based on the device type corresponding to the gate stack structure. P-type work function materials include TiN, tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), nickel silicide (NiSi2), other suitable P-type work function materials, and / or combinations thereof. Exemplary N-type work function materials include La2O3, titanium (Ti), silver (Ag), tantalum aluminum nitride (TaAl), aluminum tantalum carbide (TaAlC), aluminum tantalum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), other suitable N-type work function materials, and / or combinations thereof. N-type work function materials can be configured to have the desired work function value of the gate electrode of an N-channel field-effect transistor (NFET); P-type work function materials can be configured to have the desired work function value of the gate electrode of a P-channel field-effect transistor (PFET).

[0080] The gate electrode layer may include copper, tungsten, metal alloys, metal silicides, other conductive materials, or combinations thereof.

[0081] In some embodiments, the high-K dielectric layer may include at least one of a silicon hafnium oxide layer, a silicon oxynitride hafnium layer, a tantalum hafnium oxide layer, a titanium hafnium oxide layer, and a zirconium hafnium oxide layer.

[0082] In some embodiments, for case one above, see Figure 2b Step S202 may include steps S21 and S22, wherein:

[0083] Step S21: A high-k dielectric layer in contact with the substrate is formed on the substrate;

[0084] Step S22: A first barrier layer is formed on the high-K dielectric layer to contact the high-K dielectric layer; wherein the first barrier layer contains the same metal element as the high-K dielectric layer;

[0085] Step S203 may include step S23, forming a work function layer that contacts the first barrier layer on the first barrier layer.

[0086] The following is combined Figure 2c Steps S201 to S204 will be further explained. Figure 2c Taking the formation of a high-k dielectric layer on a substrate, and then forming a first barrier layer on the high-k dielectric layer, as an example, specifically using the above-described case one, this will be explained. See [link to relevant documentation]. Figure 2c A high-K dielectric layer 203 in contact with the substrate 201 is formed on the substrate 201. A first barrier layer 204 in contact with the high-K dielectric layer 203 is formed on the high-K dielectric layer 203. A work function layer 205 in contact with the first barrier layer 204 is formed on the first barrier layer 204. A gate electrode layer 206 in contact with the work function layer 205 is formed on the work function layer 205.

[0087] Based on the semiconductor structure formation method provided in steps S201 to S204, this application embodiment provides a semiconductor structure, including: a substrate and a gate stack structure located on the substrate; wherein, the gate stack structure includes: a high-k dielectric layer; a first barrier layer in contact with the high-k dielectric layer; a work function layer located on the side of the high-k dielectric layer away from the substrate; and a gate electrode layer located on the side of the work function layer away from the substrate; wherein, the first barrier layer contains the same metal element as the high-k dielectric layer.

[0088] The work function layer located on the side of the high-k dielectric layer away from the substrate includes the following two cases: 1) the high-k dielectric layer is in contact with the work function layer; 2) the high-k dielectric layer is not in contact with the work function layer. For example, when the first barrier layer is in contact with the lower surface of the high-k dielectric layer, the work function layer is in contact with the high-k dielectric layer and is located above the high-k dielectric layer; when the first barrier layer is in contact with the upper surface of the high-k dielectric layer, the work function layer is not in contact with the high-k dielectric layer, but is located on the upper surface of the first barrier layer and is in contact with the first barrier layer; when the first barrier layer is in contact with both the upper and lower surfaces of the high-k dielectric layer, the work function layer is in contact with the first barrier layer located on the upper surface of the high-k dielectric layer, rather than with the first barrier layer located on the lower surface of the high-k dielectric layer.

[0089] The semiconductor structure provided in this application embodiment may be included in the formation process of an integrated circuit or a part thereof, and may include static random-access memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors and inductors, and active components such as PFETs, NFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, combinations thereof and / or other semiconductor devices.

[0090] In some embodiments, the first barrier layer is located on the side of the high-k dielectric layer away from the substrate. This application embodiment corresponds to the first scenario described above.

[0091] The following is combined Figure 2c The semiconductor structure provided in this embodiment will be further described in detail. Among other things, Figure 2c This is a schematic diagram of a semiconductor structure provided for scenario one described above. See also... Figure 2c The semiconductor structure includes a substrate 201 and a gate stack structure 202 located on the substrate 201; wherein the gate stack structure 202 includes a high-k dielectric layer 203; a first barrier layer 204 in contact with the high-k dielectric layer 203; a work function layer 205 located on the high-k dielectric layer 203; and a gate electrode layer 206 located on the work function layer 205; in this embodiment, the substrate 201 is a silicon substrate, the high-k dielectric layer 203 is an HfO2 layer, and the first barrier layer 204 is LaHfO2. x The work function layer 205 is a La2O3 layer, and the gate electrode layer 206 is a TiN layer. The first barrier layer 204 contains the same Hf element as the high-k dielectric layer 203.

[0092] In some embodiments, the high-K dielectric layer may include at least one of a silicon hafnium oxide layer, a silicon oxynitride hafnium layer, a tantalum hafnium oxide layer, a titanium hafnium oxide layer, and a zirconium hafnium oxide layer.

[0093] In some embodiments, the method further includes step S205, forming an insulating layer on the substrate, wherein the insulating layer comprises at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Here, S205 can be performed after step S201.

[0094] Based on the semiconductor structure formation method provided in steps S201 to S205, the gate stack structure in some embodiments further includes: an insulating layer formed on the substrate, wherein the insulating layer includes at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0095] See Figure 2d The gate stack structure 202 also includes an insulating layer 208 located on the substrate 201. In this embodiment, the insulating layer may be a silicon oxide layer.

[0096] In some embodiments, the method further includes step S206, forming sidewall structures on both sides of the gate stack structure; wherein the sidewall structures include nitride layers. Here, step S206 can be performed after S204.

[0097] Based on step S206, in some embodiments the structure further includes: sidewall structures located on both sides of the gate stack structure; wherein the sidewall structure includes a nitrided layer.

[0098] See Figure 2e The semiconductor structure also includes sidewall structures 209 located on both sides of the gate stack structure 202. In this embodiment, the sidewall structure 209 may include a silicon nitride (Si3N4) layer.

[0099] In some embodiments, the thickness of the high-k dielectric layer is 20 to 40 angstroms. In this way, the threshold voltage of the device can be effectively controlled, and the actual physical thickness can be increased as much as possible while ensuring the equivalent electrical thickness, so as to reduce the leakage current of the device and make the device more stable.

[0100] In some embodiments, the thickness of the first barrier layer is 2 to 100 mm. In this way, the impact of an excessively thick barrier layer on the regulation of the metal's work function can be reduced, while the problem of an excessively thin barrier layer failing to prevent oxygen from diffusing to the bottom can be solved.

[0101] In some embodiments, the thickness of the gate electrode layer is 2 to In this way, the influence of the gate electrode thickness on the work function difference of the device's metal-semiconductor contact can be reduced, the connection resistance of the device can be decreased, and thus the device performance can be improved.

[0102] In some embodiments, the gate electrode layer comprises a TiN layer. In other embodiments, the gate electrode layer may further comprise a TaN layer.

[0103] This application provides a method for forming a semiconductor structure in accordance with the second scenario described above. See [link to relevant documentation]. Figure 3a The method includes steps S301 to S305, wherein:

[0104] Step S301, provide a substrate;

[0105] Step S302: A first barrier layer in contact with the substrate is formed on the substrate;

[0106] Step S303: Form the high-k dielectric layer on the first barrier layer, which is in contact with the first barrier layer; wherein the first barrier layer contains the same metal element as the high-k dielectric layer;

[0107] Step S304: A work function layer in contact with the high-k dielectric layer is formed on the high-k dielectric layer;

[0108] Step S305: A gate electrode layer is formed on the work function layer to form a gate stack structure on the substrate.

[0109] The following is combined Figure 3b Steps S301 to S305 are further explained below. See [link / reference] Figure 3b A first barrier layer 204 in contact with the substrate 201 is formed on the substrate 201, a high-K dielectric layer 203 in contact with the first barrier layer 204 is formed on the first barrier layer 204, a work function layer 205 in contact with the high-K dielectric layer 203 is formed on the high-K dielectric layer 203, and a gate electrode layer 206 in contact with the work function layer 205 is formed on the work function layer 205.

[0110] This application provides a semiconductor structure for the second scenario described above, wherein the first barrier layer can contact the lower surface of the high-k dielectric layer; the structure includes: a substrate and a gate stack structure located on the substrate; wherein the gate stack structure includes: a high-k dielectric layer; a first barrier layer in contact with the high-k dielectric layer; a work function layer located on the side of the high-k dielectric layer away from the substrate; and a gate electrode layer located on the side of the work function layer away from the substrate; wherein the first barrier layer contains the same metal element as the high-k dielectric layer; and the first barrier layer is located on the side of the high-k dielectric layer closer to the substrate.

[0111] The following is combined Figure 3b The semiconductor structure provided in this embodiment will be described in further detail.

[0112] See Figure 3bThe semiconductor structure includes a substrate 201 and a gate stack structure 202 located on the substrate 201; wherein the gate stack structure 202 includes: a first barrier layer 204 in contact with the substrate 201, a high-k dielectric layer 203 in contact with the upper surface of the first barrier layer 204; a work function layer 205 located on the upper surface of the high-k dielectric layer 203; and a gate electrode layer 206 located on the work function layer 205; in this embodiment, the substrate 201 is a silicon substrate, the high-k dielectric layer 203 is an HfSiON layer, and the first barrier layer 204 is LaHfO. x The work function layer 205 is a La2O3 layer, and the gate electrode layer 206 is a TaN layer. The first barrier layer 204 contains the same Hf element as the high-k dielectric layer 203.

[0113] In this embodiment, by providing a first barrier layer between the high-k dielectric layer and the substrate, the transport of O to the substrate can be blocked, thereby preventing the reaction between the high-k dielectric layer and the substrate to generate oxygen vacancies and silicon dioxide, which can reduce the drift of the threshold voltage and improve the stability of the device; at the same time, it can also reduce the growth of the insulating layer.

[0114] In some embodiments, the gate stack structure further includes an insulating layer formed on the substrate, wherein the insulating layer comprises at least one layer selected from a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. See also Figure 3c The gate stack structure 202 further includes an insulating layer 208 formed on the substrate 201, the upper surface of which is in contact with the first barrier layer 204. In this embodiment, the insulating layer 208 is a silicon oxide layer.

[0115] In some embodiments, the thickness of the insulating layer is 10 to

[0116] This application provides a method for forming a semiconductor structure in response to the above-described third situation. See [link to relevant documentation]. Figure 4a The method includes steps S401 to S406, wherein:

[0117] Step S401, provide a substrate;

[0118] Step S402: A first barrier layer in contact with the substrate is formed on the substrate;

[0119] Step S403: Form the high-k dielectric layer on the first barrier layer, which is in contact with the first barrier layer; wherein the first barrier layer contains the same metal element as the high-k dielectric layer;

[0120] Step S404: A second barrier layer in contact with the high-K dielectric layer is formed on the high-K dielectric layer;

[0121] Step S405: A work function layer in contact with the second barrier layer is formed on the second barrier layer;

[0122] Step S406: A gate electrode layer is formed on the work function layer to form a gate stack structure on the substrate.

[0123] The following is combined Figure 4b Steps S401 to S406 are further explained. Steps S401 and S402 are performed to form a first barrier layer 204 in contact with the substrate 201; step S403 is performed to form a high-k dielectric layer 203 in contact with the first barrier layer 204; step S404 is performed to form a second barrier layer 207 in contact with the high-k dielectric layer 203; step S405 is performed to form a work function layer 205 in contact with the second barrier layer 207; and step S406 is performed to form a gate electrode layer 206 on the work function layer 205, thereby forming a gate stack structure 202 on the substrate 201.

[0124] Based on the semiconductor structure method provided in steps S401 to S406, this application embodiment provides a semiconductor structure for the above-mentioned third case, wherein the first barrier layer is in contact with both the upper and lower surfaces of the high-k dielectric layer. The structure includes: a substrate and a gate stack structure located on the substrate; wherein the gate stack structure includes: a high-k dielectric layer; a first barrier layer in contact with the high-k dielectric layer; a second barrier layer located on the side of the high-k dielectric layer away from the substrate and in contact with the high-k dielectric layer; a work function layer located on the side of the high-k dielectric layer away from the substrate; and a gate electrode layer located on the side of the work function layer away from the substrate; wherein the first barrier layer contains the same metal element as the high-k dielectric layer; and the first barrier layer is located on the side of the high-k dielectric layer closer to the substrate.

[0125] See Figure 4b The semiconductor structure includes a substrate 201 and a gate stack structure 202 located on the substrate 201; wherein the gate stack structure 202 includes: a first barrier layer 204 in contact with the substrate 201, a high-k dielectric layer 203 in contact with the upper surface of the first barrier layer 204; a second barrier layer 207 located on the upper surface of the high-k dielectric layer 203; a work function layer 205 located on the second barrier layer 207, i.e., the work function layer 205 is in contact with the upper surface of the second barrier layer 207; and a gate electrode layer 206 located on the work function layer 205.

[0126] In this embodiment, by providing a first barrier layer and a second barrier layer in contact with the high-k dielectric layer, not only can the transport of O from the high-k dielectric layer to the substrate be blocked, reducing O transport, but it can also prevent oxygen in the air or oxygen introduced in subsequent manufacturing processes from entering the gate electrode layer, work function layer, and high-k dielectric layer. This is more conducive to preventing the reaction between the high-k dielectric layer and the substrate to generate oxygen vacancies and silicon dioxide, further reducing threshold voltage drift and improving device stability; at the same time, it can also further reduce the growth of the insulating layer.

[0127] In some embodiments, the second barrier layer may be the same as the first barrier layer; for example, the first barrier layer may include a lanthanum hafnium oxide layer, and the second barrier layer may include a lanthanum hafnium oxide layer. In other embodiments, the second barrier layer may be different from the first barrier layer, and this application does not limit this.

[0128] In some embodiments, the thickness of the second barrier layer may be the same as or different from the thickness of the first barrier layer.

[0129] This application provides a semiconductor structure comprising: a substrate and a gate stack structure located on the substrate; wherein the gate stack structure comprises: an insulating layer formed on the substrate; a high-k dielectric layer; a first barrier layer in contact with the high-k dielectric layer; a work function layer located on the side of the high-k dielectric layer away from the substrate; and a gate electrode layer located on the side of the work function layer away from the substrate; wherein the first barrier layer contains the same metal element as the high-k dielectric layer; and the insulating layer comprises at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0130] In this embodiment, the gate stack structure includes: an insulating layer formed on a substrate; a high-k dielectric layer; a first barrier layer in contact with the high-k dielectric layer; a work function layer located on the side of the high-k dielectric layer away from the substrate; and a gate electrode layer located on the side of the work function layer away from the substrate. On one hand, the stack structure formed by the insulating layer and the subsequently formed high-k gate dielectric layer serves as the gate dielectric layer; on the other hand, the insulating layer provides a good interface foundation for the subsequent formation of the high-k gate dielectric layer, thereby improving the quality of the formed high-k gate dielectric layer, reducing the interface state density between the high-k gate dielectric layer and the substrate, and avoiding the adverse effects caused by direct contact between the high-k gate dielectric layer and the substrate.

[0131] The following is combined Figure 4c The semiconductor structure provided in this embodiment will be described in further detail.

[0132] The semiconductor structure includes a substrate 201 and a gate stack structure 202 located on the substrate 201; wherein the gate stack structure 202 includes: an insulating layer 208 formed on the substrate, the insulating layer 208 may be a silicon oxynitride layer; a high-k dielectric layer 203 located on the insulating layer 208; a first barrier layer 204 in contact with the high-k dielectric layer 203; a work function layer 205 located on the high-k dielectric layer 203; and a gate electrode layer 206 located on the work function layer 205; in this embodiment, the substrate 201 is a silicon substrate, the high-k dielectric layer 203 is an HfTaO layer, and the first barrier layer 204 is LaHfO. x The work function layer 205 is a La2O3 layer, and the gate electrode layer 206 is a TaN layer. The first barrier layer 204 contains the same Hf element as the high-k dielectric layer 203.

[0133] In some embodiments, the structure further includes sidewall structures located on both sides of the gate stack structure; wherein the sidewall structures include nitride layers. See also Figure 4d The semiconductor structure also includes sidewall structures 209 located on both sides of the gate stack structure 202. In this embodiment, the sidewall structure 209 can be a silicon dioxide-silicon nitride-silicon dioxide (SiO2-Si3N4-SiO2, ONO) multilayer structure.

[0134] In some embodiments, the structure further includes an LDD structure and a halo ring. Halo ring ion implantation is used in the LDD structure to increase the doping concentration at the substrate-source-drain interface, thereby reducing the width of the source-drain depletion region to suppress the drain-induced barrier reduction effect in short-channel devices.

[0135] This application provides a method for forming a semiconductor structure, such as... Figure 5a As shown, the first barrier layer includes a lanthanum hafnium oxide layer, the second barrier layer includes a lanthanum hafnium oxide layer, and the method includes steps S501 to S510, wherein:

[0136] Step S501, provide a substrate;

[0137] Step S502: A lanthanum oxide layer is formed on the substrate;

[0138] Here, the lanthanum oxide layer can be formed using methods such as molecular beam epitaxy (MBE), ALD, and CVD. In some embodiments, the thickness of the La2O3 layer can be 2 to...

[0139] Step S503: A hafnium dioxide layer is formed on the lanthanum oxide layer;

[0140] Hafnium dioxide can be formed here through methods such as ALD, CVD, and MBE.

[0141] Step S504: Annealing to form the first barrier layer;

[0142] Here, annealing can be rapid thermal annealing, flash annealing, peak annealing, or laser annealing. The annealing atmosphere can include O2, and also one or more of N2, Ar, or He; the annealing temperature can be 300 to 1000 degrees Celsius (°C), and the first barrier layer formed includes LaHfO. x In the first barrier layer after annealing, the oxygen vacancy density decreases, and due to the high formation energy of oxygen vacancies near La, it becomes difficult for external oxygen to be transported through the low-density oxygen vacancy dielectric layer to the high-density oxygen vacancy dielectric layer. This reduces or even eliminates interference from external oxygen, thereby improving device stability. Simultaneously, by forming the first barrier layer through annealing, it is made to contain the same metal elements as the high-k dielectric layer, effectively reducing fabrication steps and improving efficiency.

[0143] Step S505: A high-k dielectric layer is formed on the first barrier layer and in contact with the first barrier layer; wherein the first barrier layer contains the same metal element as the high-k dielectric layer;

[0144] Step S506: A lanthanum oxide layer is formed on the high-k dielectric layer;

[0145] Step S507: A hafnium dioxide layer is formed on the La2O3 layer;

[0146] Step S508: Annealing to form a second barrier layer;

[0147] Here, steps S506 to S508 can be implemented with reference to steps S502 to S504.

[0148] Step S509: A work function layer in contact with the second barrier layer is formed on the second barrier layer;

[0149] Step S510: A gate electrode layer is formed on the work function layer to form a gate stack structure on the substrate.

[0150] In this embodiment, a lanthanum oxide layer is formed on a substrate or a high-k dielectric layer; a hafnium dioxide layer is formed on the lanthanum oxide layer, and then annealed to form a lanthanum-hafnium oxide layer. In the first barrier layer after annealing, the oxygen vacancy density is reduced, and because the energy required to form oxygen vacancies near La is high, it is difficult for external oxygen to be transported through the low-density oxygen vacancy dielectric layer to the high-density oxygen vacancy dielectric layer, reducing or even eliminating interference from external oxygen, thereby improving device stability. Simultaneously, by annealing to form the first barrier layer, which contains the same metal element as the high-k dielectric layer, the fabrication process can be effectively reduced, improving efficiency.

[0151] In some embodiments, the gate electrode layer includes a TiN layer or a TaN layer.

[0152] In some embodiments, the thickness of the high-k dielectric layer is 20 to

[0153] In some embodiments, the thickness of the first barrier layer is 2 to 100 mm.

[0154] In some embodiments, the thickness of the gate electrode layer is 2 to

[0155] In some embodiments, the method further includes step S511, forming an insulating layer on the substrate, wherein the insulating layer comprises at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Here, step S511 is performed after step S501. See also... Figure 5b Steps S511, S502 to S511 are executed to form an insulating layer 208 on the substrate 201. Then, a lanthanum oxide layer and a hafnium dioxide layer are sequentially formed on the insulating layer 208, followed by annealing to form a first barrier layer 204. A high-k dielectric layer 203 is formed on the first barrier layer 204, and a lanthanum oxide layer is formed on the high-k dielectric layer 203. A hafnium dioxide layer is formed on the lanthanum oxide layer. Annealing forms a second barrier layer 207. A power function layer 205 is formed on the second barrier layer 207. A gate electrode layer 206 is formed on the work function layer 205, thereby forming a gate stack structure 202 on the substrate 201. Therefore, the gate stack structure 202 includes an insulating layer 208, a first barrier layer 204, a high-k dielectric layer 203, a second barrier layer 207, a work function layer 205, and a gate electrode layer 206.

[0156] In some embodiments, the thickness of the insulating layer is 10 to

[0157] The features disclosed in the methods or semiconductor structure embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or semiconductor structure embodiments.

[0158] The descriptions of the above semiconductor structure embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the semiconductor embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0159] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor structure, characterized in that, include: A substrate and a gate stack structure located on the substrate; wherein the gate stack structure includes: High-K dielectric layer; A first barrier layer located on the side of the high-k dielectric layer close to the substrate and in contact with the high-k dielectric layer; A second barrier layer located on the side of the high-k dielectric layer away from the substrate and in contact with the high-k dielectric layer; A work function layer located on the side of the high-k dielectric layer away from the substrate; The gate electrode layer is located on the side of the work function layer away from the substrate; The first barrier layer contains the same metal element as the high-K dielectric layer, and the first barrier layer includes a lanthanum hafnium oxide layer, and the second barrier layer includes a lanthanum hafnium oxide layer.

2. The structure according to claim 1, characterized in that, The high-K dielectric layer includes at least one of the following: silicon hafnium oxide layer, silicon oxynitride hafnium layer, tantalum hafnium oxide layer, titanium hafnium oxide layer, and zirconium hafnium oxide layer.

3. The structure according to claim 1, characterized in that, The gate electrode layer includes a titanium nitride layer.

4. The structure according to claim 1, characterized in that, The gate stack structure further includes an insulating layer formed on the substrate, wherein the insulating layer includes at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

5. The structure according to claim 1, characterized in that, Also includes: Sidewall structures located on both sides of the grid stack structure; wherein the sidewall structures include nitrided layers.

6. The structure according to claim 1, characterized in that, The thickness of the high-K dielectric layer is 20 to 40 Å; the thickness of the first barrier layer is 2 to 10 Å; and the thickness of the gate electrode layer is 2 to 10 Å.

7. The structure according to claim 4, characterized in that, The thickness of the insulating layer is 10 to 40 Å.

8. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first barrier layer in contact with the substrate is formed on the substrate; A high-k dielectric layer is formed on the first barrier layer and in contact with the first barrier layer; A second barrier layer is formed on the high-K dielectric layer and in contact with the high-K dielectric layer; A work function layer is formed on the second barrier layer and in contact with the second barrier layer; A gate electrode layer is formed on the work function layer to form a gate stack structure on the substrate; The first barrier layer contains the same metal element as the high-k dielectric layer, the first barrier layer includes a lanthanum hafnium oxide layer, and the second barrier layer includes a lanthanum hafnium oxide layer; the method for forming the lanthanum hafnium oxide layer includes: A lanthanum oxide layer is formed on the substrate or the high-k dielectric layer; A hafnium dioxide layer is formed on the lanthanum oxide layer; Annealing forms a lanthanum hafnium oxide layer.

9. The method according to claim 8, characterized in that, The high-K dielectric layer includes at least one of the following: silicon hafnium oxide layer, silicon oxynitride hafnium layer, tantalum hafnium oxide layer, titanium hafnium oxide layer, and zirconium hafnium oxide layer.

10. The method according to claim 8, characterized in that, The gate electrode layer includes a titanium nitride layer.

11. The method according to claim 8, characterized in that, The thickness of the high-K dielectric layer is 20 to 40 Å; the thickness of the first barrier layer is 2 to 10 Å; and the thickness of the gate electrode layer is 2 to 10 Å.

12. The method according to claim 8, characterized in that, Also includes: An insulating layer is formed on the substrate, wherein the insulating layer comprises at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

13. The method according to claim 12, characterized in that, The thickness of the insulating layer is 10 to 40 Å.

14. The method according to claim 8, characterized in that, Also includes: Sidewall structures are formed on both sides of the gate stack structure; wherein the sidewall structure includes a nitrided layer.

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