A modulation method for suppressing leakage current of H-bridge cascade inverter

Abstract

The present invention proposes a modulation method for suppressing leakage current of an H-bridge cascade inverter, which relates to the technical field of single-phase cascade H-bridge modulation, and comprises: S1, establishing a mathematical model of a photovoltaic array connected to an electrified railway traction network via a cascade inverter, and obtaining a leakage current excitation model through calculation of the mathematical model, and obtaining a total parasitic capacitance voltage and based on the leakage current excitation model; S2, screening out a switch sequence whose total parasitic capacitance voltage and of each output level are equal and constant in all switch combinations of all output levels; S3, optimizing the screened switch sequence with the minimum number of switching switches of adjacent levels of the output voltage as an optimization condition to obtain an optimal switch combination of a constant total parasitic capacitance voltage with the minimum number of overall switching times; S4, combining the optimal switch combination with an existing carrier stack to obtain a modulation result; the method provided by the present invention can achieve leakage current suppression and switching number optimization without increasing hardware costs.

Description

Technical Field

[0001] The invention relates to the technical field of single-phase cascade H-bridge modulation, and in particular to a modulation method for suppressing leakage current of an H-bridge cascade inverter. Background Art

[0002] Leakage current can cause electromagnetic radiation and interference to equipment, increase system harmonics and traction network losses, and seriously endanger equipment and personnel safety. Domestic and foreign scholars have conducted extensive research on the leakage current of non-isolated grid-connected inverters. The H5 topology proposed by SMA effectively suppresses the leakage current of single-phase H-bridges, and the derived H7 and H8 topologies solve the leakage current problem of three-phase inverters. However, this topology and its derivative systems are suitable for single inverter systems, and their main application scenarios are also low-power environments. With the further increase in photovoltaic capacity, more photovoltaic grid-connected scenarios require inverters with higher voltage and power levels, so multi-level inverters are gradually becoming a trend. Therefore, the cascaded H-bridge inverter is widely favored in the field of high-voltage and high-power single-phase grid-connected because of its modularity, easy expansion, and high power quality.

[0003] However, in the prior art, the modulation methods for cascaded H-bridge multi-level inverters are mainly carrier stacking and carrier phase shifting. Both modulation methods can effectively achieve multi-module cascade photovoltaic grid-connected performance, but have no obvious effect on leakage current suppression; other methods are only applicable to two-module cascades, cannot effectively expand multi-module cascade scenarios, and require additional passive circuits and equipment volume and cost, making it difficult to balance the additional hardware cost and modulation difficulty applied to multi-module cascade H-bridge leakage current suppression strategies.

[0004] Based on this, the present application specifically proposes a modulation method for suppressing leakage current of an H-bridge cascade inverter to solve the above problem. Summary of the invention

[0005] The object of the present invention is to provide a modulation method for suppressing leakage current of an H-bridge cascade inverter, which can achieve leakage current suppression and switching number optimization without increasing hardware cost.

[0006] The technical solution of the present invention is:

[0007] In a first aspect, the present application provides a modulation method for suppressing leakage current of an H-bridge cascade inverter, which comprises the following steps:

[0008] S1. Establish a mathematical model for connecting a photovoltaic array to an electrified railway traction network via a cascade inverter, and obtain a leakage current excitation model through the mathematical model calculation, and obtain the total parasitic capacitance voltage and based on the leakage current excitation model;

[0009] S2, selecting a switching sequence whose total parasitic capacitance voltage of each output level is equal and constant from all switch combinations of all output levels;

[0010] S3, taking the minimum number of switching times of adjacent level switching switches of the output voltage as the optimization condition, optimizing the selected switch sequence to obtain the optimal switch combination of the constant total parasitic capacitance voltage with the minimum number of overall switching times;

[0011] S4. Combine the optimal switch combination with the existing carrier stack to obtain a modulation result.

[0012] Furthermore, in step S1, the calculation steps of establishing the mathematical model of connecting the photovoltaic array to the electrified railway traction network via the cascade inverter include:

[0013] Define n cascaded modules to have equal PV port voltages:

[0014] U PV1 =U PV2 =…=U PVn =U PV , (1)

[0015] The bridge arm voltage is defined as:

[0016]

[0017] The common mode U of the i-th module cmi and differential mode U dmi The excitation signal is:

[0018]

[0019] According to the electrical quantity relationship of capacitor components, the leakage current expression can be obtained:

[0020]

[0021] Define the capacitor values ​​to be equal:

[0022]

[0023] According to Kirchhoff's voltage law, the mathematical model of photovoltaic array connected to the electrified railway traction network through cascade inverter is:

[0024]

[0025] Among them, U PV Indicates the PV port voltage of the cascaded module, U AiNi , U BiNi Respectively represent the A and B bridge arm voltages of the i-th module, S Ai , S BiRespectively represent the power switch conduction signal on the A and B bridge arms of the i-th module, U cmi represents the common mode excitation signal of the ith module, U dmi represents the differential mode excitation signal of the ith module, C PV Indicates the capacitance value, i SLg Indicates leakage current, U SCV represents the parasitic capacitance voltage and, U cn Represents the parasitic capacitance voltage matrix of each module, U Cm Indicates the common mode voltage, U dm represents the differential mode voltage, n represents the number of cascaded modules, U L Indicates the inductor voltage, U grid Indicates the grid voltage, U dmj Represents the differential mode voltage of the jth module.

[0026] Furthermore, in step S1, the above-mentioned step of calculating the leakage current excitation model by the mathematical model and obtaining the total parasitic capacitance voltage based on the leakage current excitation model includes:

[0027] According to formula (6), the parasitic capacitance voltage excitation model is expressed as:

[0028] A[U C ] T =B[U cm ] T +C[U dm ] T +D T U grid , (7)

[0029] Solving equation (7) yields the parasitic capacitance voltage of each module:

[0030]

[0031] According to equations (5) to (8), the total parasitic capacitance and leakage current excitation model of the system are obtained:

[0032]

[0033] Among them, A represents the parasitic capacitance voltage coefficient of each module, B represents the common mode voltage coefficient of each module, C represents the differential mode voltage coefficient of each module, D represents the grid voltage coefficient, and U SCV represents the parasitic capacitance voltage and, U Cm Indicates the common mode voltage, U dm Represents the differential mode voltage, C PV Indicates the capacitance value, i SLg Indicates leakage current, U dmj represents the differential voltage of the jth module, U grid Indicates the grid voltage, UCk represents the parasitic capacitance voltage of the kth module, U dmk represents the differential voltage of the kth module, U Cj represents the parasitic capacitance voltage of the jth module, and j and k both represent accumulated parameters.

[0034] Further, step S2 includes:

[0035] According to formula (9), the relationship between the total parasitic capacitance voltage of the system and the bridge arm voltage is obtained:

[0036] U SCV =[n / 2 -n / 2+0.5 … -n / 2+05. n / 2][U A1N1 U B1N1 … U AnNn U BnNn ] T (10)

[0037] Among them, [U A1N1 U B1N1 … U AnNn U BnNn ] represents the bridge arm voltage matrix, U AnNn , U BnNn Respectively represent the A and B bridge arm voltages of the nth module;

[0038] Equation (10) is solved to obtain the total parasitic capacitance voltage of the system corresponding to the highest positive level and the highest negative level, and based on this, a switching sequence with an equal and constant total parasitic capacitance voltage of each output level is selected from all switch combinations of all output levels.

[0039] Furthermore, in step S3, the calculation formula for the minimum number of switching times of the adjacent level switching switches of the output voltage is:

[0040]

[0041] Among them, F represents the minimum switching times of the adjacent two-level switch combination, S Ai Indicates the power switch conduction signal on the bridge arm of the i-th module, S A(i+1) Indicates the power switch conduction signal on the bridge arm of the i+1th module A, S Bi Indicates the power switch conduction signal on the bridge arm B of the i-th module, S B(i+1) Indicates the power switch conduction signal on the bridge arm B of the i+1th module.

[0042] In a second aspect, the present application provides an electronic device, characterized in that it includes:

[0043] A memory for storing one or more programs;

[0044] processor;

[0045] When the one or more programs are executed by the processor, a modulation method for suppressing leakage current of an H-bridge cascade inverter as described in any one of the first aspects is implemented.

[0046] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a modulation method for suppressing leakage current of an H-bridge cascade inverter as described in any one of the first aspects above.

[0047] Compared with the prior art, the present invention has at least the following advantages or beneficial effects:

[0048] The present invention provides a modulation method for suppressing leakage current of an H-bridge cascade inverter. By establishing a mathematical model of photovoltaic access to an electrified railway traction network, a switch sequence with equal total parasitic capacitance voltages of each level is screened out under the premise of ensuring that the output voltage level of the cascade inverter is not lost, and the switch sequence is optimized with the minimum number of switches of adjacent output voltage levels as the optimization condition, so as to obtain an optimal switch combination with a constant total parasitic capacitance voltage with the minimum overall switching number, and then the optimal switch combination is combined with an existing carrier stack to obtain a modulation result, which can effectively suppress leakage current and optimize the switching number, and at the same time achieve multi-module cascade photovoltaic grid-connected performance without increasing the volume and cost of additional passive circuits and hardware equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 A step diagram of a modulation method for suppressing leakage current of an H-bridge cascade inverter according to the present invention;

[0051] Figure 2 This is a schematic diagram of photovoltaic access to the railway traction network;

[0052] Figure 3 The schematic diagram of the modulation waveform is shown in FIG. 10 , taking 10 modules as an example;

[0053] Figure 4 This is a schematic diagram of the driving signal of the upper bridge arm power switch of each module, taking 10 modules as an example;

[0054] Figure 5 The voltage waveform of parasitic capacitance of 10 modules under traditional PD-PWM modulation;

[0055] Figure 6 This is the leakage current waveform of 10 modules under traditional PD-PWM modulation;

[0056] Figure 7 It is the waveform diagram of the output port voltage, grid voltage and grid-connected current of 10 modules;

[0057] Figure 8 This is the voltage waveform of parasitic capacitance of 10 modules;

[0058] Fig. 9 This is the leakage current waveform of 10 modules;

[0059] Fig.10 The figure is a schematic structural block diagram of an electronic device according to an embodiment of the present invention.

[0060] Icon: 101, memory; 102, processor; 103, communication interface. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0062] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0063] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0064] It should be noted that, in this article, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprises..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0065] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0066] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0067] Example 1

[0068] See also Figure 1 , Figure 1 The figure shows a step diagram of a modulation method for suppressing leakage current of an H-bridge cascade inverter provided in an embodiment of the present application.

[0069] In a first aspect, the present application provides a modulation method for suppressing leakage current of an H-bridge cascade inverter, which comprises the following steps:

[0070] S1. Establish a mathematical model for connecting a photovoltaic array to an electrified railway traction network via a cascade inverter, and obtain a leakage current excitation model through the mathematical model calculation, and obtain the total parasitic capacitance voltage and based on the leakage current excitation model;

[0071] S2, selecting a switching sequence whose total parasitic capacitance voltage of each output level is equal and constant from all switch combinations of all output levels;

[0072] S3, taking the minimum number of switching times of adjacent level switching switches of the output voltage as the optimization condition, optimizing the selected switch sequence to obtain the optimal switch combination of the constant total parasitic capacitance voltage with the minimum number of overall switching times;

[0073] S4. Combine the optimal switch combination with the existing carrier stack to obtain a modulation result.

[0074] See also Figure 2 , Figure 2 As a preferred embodiment, in step S1, the calculation steps of establishing a mathematical model of photovoltaic arrays connected to an electrified railway traction network via cascade inverters include:

[0075] Define n cascaded modules to have equal PV port voltages:

[0076] U PV1 =U PV2 =…=U PVn =UPV , (1)

[0077] Let n be a natural even number, and define the bridge arm voltage as:

[0078]

[0079] The common mode U of the i-th module cmi and differential mode U dmi The excitation signal is:

[0080]

[0081] According to the electrical quantity relationship of capacitor components, the leakage current expression can be obtained:

[0082]

[0083] Define the capacitor values ​​to be equal:

[0084]

[0085] According to Kirchhoff's voltage law, the mathematical model of photovoltaic array connected to the electrified railway traction network through cascade inverter is:

[0086]

[0087] Among them, U PV Indicates the PV port voltage of the cascaded module, U AiNi , U BiNi Respectively represent the A and B bridge arm voltages of the i-th module, S Ai , S Bi Respectively represent the power switch conduction signal on the A and B bridge arms of the i-th module, U cmi represents the common mode excitation signal of the ith module, U dmi represents the differential mode excitation signal of the ith module, C PV Indicates the capacitance value, i SLg Indicates leakage current, U SCV represents the parasitic capacitance voltage and, U cn Represents the parasitic capacitance voltage matrix of each module, U Cm Indicates the common mode voltage, U dm represents the differential mode voltage, n represents the number of cascaded modules, U L Indicates the inductor voltage, U grid Indicates the grid voltage, U dmj Represents the differential mode voltage of the jth module.

[0088] As a preferred implementation, in step S1, the leakage current excitation model is obtained by mathematical model calculation, and the calculation step of the total parasitic capacitance voltage and is obtained based on the leakage current excitation model includes:

[0089] According to formula (6), the parasitic capacitance voltage excitation model is expressed as:

[0090] A[U C ] T =B[U cm ] T +C[U dm ] T +D T U grid , (7)

[0091] Solving equation (7) yields the parasitic capacitance voltage of each module:

[0092]

[0093] According to equations (5) to (8), the total parasitic capacitance and leakage current excitation model of the system are obtained:

[0094]

[0095] Among them, A represents the parasitic capacitance voltage coefficient of each module, B represents the common mode voltage coefficient of each module, C represents the differential mode voltage coefficient of each module, D represents the grid voltage coefficient, and U SCV represents the parasitic capacitance voltage and, U Cm Indicates the common mode voltage, U dm Represents the differential mode voltage, C PV Indicates the capacitance value, i SLg Indicates leakage current, U dmj represents the differential voltage of the jth module, U grid Indicates the grid voltage, U Ck represents the parasitic capacitance voltage of the kth module, U dmk represents the differential voltage of the kth module, U Cj represents the parasitic capacitance voltage of the jth module, and j and k both represent accumulated parameters.

[0096] As a preferred implementation, step S2 includes:

[0097] According to formula (9), the relationship between the total parasitic capacitance voltage of the system and the bridge arm voltage is obtained:

[0098] U SCV =[n / 2 -n / 2+0.5 … -n / 2+05. n / 2][U A1N1 U B1N1 … U AnNn U BnNn ] T (10)

[0099] Among them, [U A1N1 U B1N1… U AnNn U BnNn ] represents the bridge arm voltage matrix, U AnNn , U BnNn Respectively represent the A and B bridge arm voltages of the nth module;

[0100] Equation (10) is solved to obtain the total parasitic capacitance voltage of the system corresponding to the highest positive level and the highest negative level, and based on this, a switching sequence with an equal and constant total parasitic capacitance voltage of each output level is selected from all switch combinations of all output levels.

[0101] The electrified railway traction network adopts a single-phase AC 27.5kV / 50Hz standard. In order to reduce the number of cascaded modules, an IGBT (Insulated Gate Bipolar Transistor) with a voltage level of 6.5kV is used. At the same time, a 1.5-fold margin is considered. Therefore, in this embodiment 1, 10 modules are connected in parallel as the research object, that is, n=10. Combined with formula (10), when the highest positive level is +10U PV The maximum negative level is -10U PV When the system total mode voltage is 5U PV .

[0102] The idea of ​​finding the switch sequence is to use the common-mode voltage values ​​corresponding to the highest positive and negative levels as a reference, screen the common-mode voltage values ​​of the switch combinations of all levels, and obtain a switch sequence in which the sum of the total parasitic capacitance voltage of each level is a constant;

[0103] Furthermore, the highest positive level of the 10-module cascade H-bridge is +10UPV, and the maximum negative level is -10 UPV, so the search direction is ①+10UPV→9UPV→…→0; ②-10UPV→-9UPV→…→0. The search starting point +10UPV switch combination is (10101010101010101010), and the -10UPV switch combination is (0101010101010101010101) to determine the switch combination of the next level with the least number of adjacent level switching in the switch sequence, thereby finally determining the switch combination of all levels.

[0104] As a preferred implementation, in step S3, the calculation formula for the minimum number of switching times of adjacent level switching switches of the output voltage is:

[0105]

[0106] Among them, F represents the minimum switching times of the adjacent two-level switch combination, S Ai Indicates the power switch conduction signal on the bridge arm of the i-th module, S A(i+1)Indicates the power switch conduction signal on the bridge arm of the i+1th module A, S Bi Indicates the power switch conduction signal on the bridge arm B of the i-th module, S B(i+1) Indicates the power switch conduction signal on the bridge arm B of the i+1th module.

[0107] It should be noted that, according to the switch sequence determined above, combined with the existing carrier stacking modulation, a new modulation method can be generated. Specifically, by performing an absolute value operation on the sine wave modulation signal, the number of carriers in the carrier stacking modulation can be reduced by half; the carriers are stacked in phase from 0 in the positive direction, and are named VC1, VC2, ..., VCn respectively; the state of each switch drive signal at different output levels is analyzed to determine its corresponding carrier number and logical operation relationship.

[0108] The final switch combination is shown in Table 1:

[0109] Table 1 Optimal switch combination

[0110]

[0111] See also Figure 3 , Figure 3 The modulation waveform diagram is shown in Figure 10, taking the modulation waveform V as an example. m =Msin(ωt), t represents time, M represents modulation degree∈(0,1), ω=2πf; V ref = abs(V m ), so that the switch signals are as follows:

[0112]

[0113]

[0114]

[0115]

[0116]

[0117]

[0118]

[0119]

[0120] See also Figure 4-6 , Figure 4 This is a schematic diagram of the driving signal of the upper bridge arm power switch of each module, taking 10 modules as an example; Figure 5 The voltage waveform of parasitic capacitance of 10 modules under traditional PD-PWM modulation; Figure 6 The leakage current waveform of 10 modules under traditional PD-PWM modulation.

[0121] The common-mode voltage and leakage current waveforms under PD-PWM modulation are as follows: Figure 5 , Figure 6 Observe the attached Figure 5 It can be seen that the total parasitic capacitance voltage and sinusoidal degree are low at this time, and its THD is about 13.8%, indicating that it contains a large number of harmonic components. According to formula (5), the leakage current value is large; Observation Figure 6 It can be seen that the effective value of the total leakage current is 35mA at this time, which does not meet the relevant requirements of NB / T 32004-2018.

[0122] like Figure 7 As shown, Figure 7 The waveform diagram of the output port voltage, grid voltage and grid-connected current of 10 modules; the port voltage presents a 21-level, the grid-connected current has a high sinusoidal degree and is consistent with the grid-connected voltage phase, and operates at a unity power factor. This shows that the modulation method of the present invention can realize the multi-module H-bridge cascade grid-connected function.

[0123] like Figure 8 As shown, Figure 8 The following is the voltage waveform of parasitic capacitance of 10 modules.

[0124] At this time, the total parasitic capacitance voltage and sinusoidal degree are high, and THD is about 0, indicating that it only contains a low-frequency component of 50 Hz. According to formula (5), the leakage current value is low;

[0125] like Fig. 9 As shown, Fig. 9 This is the leakage current waveform of 10 modules. Fig. 9 It can be seen that the total leakage current is only 10.4 mA at this time, which is 70.3% lower than the traditional PD-PWM debugging, verifying the effectiveness of the proposed leakage current suppression.

[0126] Example 2

[0127] See also Fig.10 , Fig.10 A schematic structural block diagram of an electronic device provided in an embodiment of the present application.

[0128] An electronic device includes a memory 101, a processor 102 and a communication interface 103, wherein the memory 101, the processor 102 and the communication interface 103 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The memory 101 can be used to store software programs and modules, and the processor 102 executes various functional applications and data processing by executing the software programs and modules stored in the memory 101. The communication interface 103 can be used to communicate signaling or data with other node devices.

[0129] Among them, the memory 101 can be but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0130] The processor 102 may be an integrated circuit chip with signal processing capability. The processor 102 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0131] It is understood that the structure shown in the figure is only for illustration, and a modulation method for suppressing leakage current of an H-bridge cascade inverter may also include more or fewer components than those shown in the figure, or have a different configuration than those shown in the figure. Each component shown in the figure may be implemented by hardware, software, or a combination thereof.

[0132] In the embodiments provided in the present application, it should be understood that the disclosed method can also be implemented in other ways. The embodiments described above are merely schematic, for example, the flowchart or block diagram in the accompanying drawings shows the possible implementation architecture, functions and operations of the method and computer program product according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of the boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0133] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0134] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0135] In summary, the embodiment of the present application provides a modulation method for suppressing the leakage current of the H-bridge cascade inverter, establishes a mathematical model of photovoltaic access to the electrified railway traction network, derives the relationship between the total parasitic capacitance voltage and the bridge arm voltage of the system, and screens out the switch sequence with equal total parasitic capacitance voltage and each level under the premise of ensuring that the output voltage level of the cascade inverter is not lost, and optimizes the switch sequence with the minimum number of switches between adjacent levels of the output voltage as the optimization condition, thereby obtaining the optimal switch combination of the constant total parasitic capacitance voltage and with the minimum number of overall switching times, and combining the optimal switch combination with the existing carrier stacking to generate a PWM signal that drives the power switch to operate. The modulation proposed by the present invention can achieve leakage current suppression and optimization of switching times without increasing hardware costs.

[0136] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0137] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A modulation method for suppressing leakage current of H-bridge cascade inverter, It is characterized in that The following steps are involved: S1. Establish a mathematical model for connecting a photovoltaic array to an electrified railway traction network via a cascade inverter, and obtain a leakage current excitation model through the mathematical model calculation, and obtain the total parasitic capacitance voltage and based on the leakage current excitation model; S2, selecting a switching sequence whose total parasitic capacitance voltage of each output level is equal and constant from all switch combinations of all output levels; S3, taking the minimum number of switching times of adjacent level switching switches of the output voltage as the optimization condition, optimizing the selected switch sequence to obtain the optimal switch combination of the constant total parasitic capacitance voltage with the minimum number of overall switching times; S4, combining the optimal switch combination with the existing carrier stack to obtain a modulation result; In step S1, the calculation steps of establishing a mathematical model of connecting a photovoltaic array to an electrified railway traction network via a cascade inverter include: Define n cascaded modules to have equal PV port voltages: ， （1） The bridge arm voltage is defined as: ， （2） The common mode U of the i-th module cmi and differential mode U dmi The excitation signal is: ， （3） According to the electrical quantity relationship of capacitor components, the leakage current expression can be obtained: ， （4） Define the capacitor values ​​to be equal: ， （5） According to Kirchhoff's voltage law, the mathematical model of photovoltaic array connected to the electrified railway traction network through cascade inverter is: ， （6） in, U PV Indicates the PV port voltage of the cascaded module, U AiNi , U BiNi Respectively represent the A and B bridge arm voltages of the i-th module, S Ai , S Bi Respectively represent the power switch conduction signal on the A and B bridge arms of the i-th module, U cmi represents the common mode excitation signal of the ith module, U dmi represents the differential mode excitation signal of the ith module, C PV Indicates the capacitance value, i SLg Indicates leakage current, U SCV represents the parasitic capacitance voltage and, U cn Represents the parasitic capacitance voltage matrix of each module, U cm represents the common mode voltage, U dm represents the differential mode voltage, n represents the number of cascaded modules, U L represents the inductor voltage, U grid Indicates the grid voltage, U dmj represents the differential mode voltage of the jth module; In step S1, the step of obtaining the leakage current excitation model by calculating the mathematical model and obtaining the total parasitic capacitance voltage based on the leakage current excitation model comprises: According to formula (6), the parasitic capacitance voltage excitation model is expressed as: ， （7） Solving equation (7) yields the parasitic capacitance voltage of each module: ， （8） According to equations (5) to (8), the total parasitic capacitance and leakage current excitation model of the system are obtained: ， （9） Among them, A represents the parasitic capacitance voltage coefficient of each module, B represents the common mode voltage coefficient of each module, C represents the differential mode voltage coefficient of each module, D represents the grid voltage coefficient, and U SCV represents the parasitic capacitance voltage and, U Cm represents the common mode voltage, U dm Represents the differential mode voltage, C PV Indicates the capacitance value, i SLg Represents the leakage current, U dmj represents the differential voltage of the jth module, U grid Indicates the grid voltage, U Ck represents the parasitic capacitance voltage of the kth module, U dmk represents the differential mode voltage of the kth module, U Cj represents the parasitic capacitance voltage of the jth module, and j and k both represent accumulated parameters.

2. A modulation method for suppressing leakage current of an H-bridge cascade inverter as claimed in claim 1, It is characterized in that Step S2 includes: According to formula (9), the relationship between the total parasitic capacitance voltage of the system and the bridge arm voltage is obtained: （10） in, represents the bridge arm voltage matrix, U AnNn , U BnNn Respectively represent the A and B bridge arm voltages of the nth module; Equation (10) is solved to obtain the total parasitic capacitance voltage of the system corresponding to the highest positive level and the highest negative level, and based on this, a switching sequence with an equal and constant total parasitic capacitance voltage of each output level is selected from all switch combinations of all output levels.

3. A modulation method for suppressing leakage current of an H-bridge cascade inverter as claimed in claim 2, It is characterized in that In step S3, the calculation formula for the minimum switching times of the adjacent level switching switches of the output voltage is: ， （11） Among them, F represents the minimum switching times of the adjacent two-level switch combination, S Ai Indicates the power switch conduction signal on the bridge arm of the i-th module, S A(i+1) Indicates the power switch conduction signal on the bridge arm of the i+1th module A, S Bi Indicates the power switch conduction signal on the bridge arm B of the i-th module, S B(i+1) Indicates the power switch conduction signal on the bridge arm B of the i+1th module.

4. An electronic device, It is characterized in that include: A memory for storing one or more programs; processor; When the one or more programs are executed by the processor, a modulation method for suppressing leakage current of an H-bridge cascade inverter as described in any one of claims 1 to 3 is implemented.

5. A computer-readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, a modulation method for suppressing leakage current of an H-bridge cascade inverter as claimed in any one of claims 1 to 3 is implemented.

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