A ring oscillator applied to an anti-radiation phase-locked loop

Abstract

The application discloses a voltage-controlled oscillator applied to an anti-radiation phase-locked loop, comprising a three-stage delay unit and a waveform shaping circuit. When a sensitive node of the delay unit is bombarded by high-energy particles, a single event transient current is generated at the node, which changes the phase and frequency of the VCO. The three-stage delay unit utilizes a positive feedback loop formed by an inverting cross circuit, and based on the SET effect transient current characteristics, accelerates the recovery process of the delay circuit to the SET effect, thereby having certain anti-SET capability. In addition, the application does not introduce a bias node sensitive to SET, although the tail current source drain node still exists, but the SET effect generated at the node is consumed by the delay unit, so the circuit is not sensitive to SET. The application effectively alleviates the irradiation influence on the voltage-controlled oscillator in the phase-locked loop, and has strong anti-single particle bombardment capability, and has little influence on the normal working state of the phase-locked loop.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor integrated circuits, and particularly relates to a ring oscillator applied to an anti-radiation phase-locked loop. BACKGROUND

[0002] With the rapid development of aerospace technology, the demand for high-reliability integrated circuits applied to irradiation environments is increasing. A large number of high-energy particles in space are easy to hit semiconductor devices, causing adverse effects such as parameter drift and performance degradation of aerospace integrated circuits, which directly or indirectly adversely affect the space system. Therefore, higher challenges are put forward for the reliability requirements of integrated circuits applied to aerospace.

[0003] A phase-locked loop (PLL) can realize functions such as frequency synthesis, clock generation, and phase synchronization, and is a key component of an aerospace electronic system. However, the PLL is very sensitive to single event effects, and under the bombardment of high-energy particles, it is very easy to produce phase or frequency offset phenomena, causing distortion of the output clock signal, leading to data transmission errors, and in severe cases, even causing chaos in the entire communication system of the spacecraft, causing abnormal operation of the spacecraft.

[0004] With the continuous reduction of process, the influence of single event effects on space devices is increasing, and in particular, single event transient (SET) effects have become the most important radiation effect affecting the phase-locked loop. A voltage controlled oscillator (VCO) is a core circuit module in the phase-locked loop, and is the circuit with the highest frequency and the most sensitive to noise in the PLL, and is also the module most sensitive to SET in the PLL. The response of SET effects in the VCO is relatively complex, and after the traditional VCO is affected by single event effects, the amplitude, frequency or phase of the output signal will change. Therefore, it is of great engineering value and practical significance to effectively anti-radiate the ring oscillator. SUMMARY

[0005] The purpose of the present application is to solve the problem of the traditional phase-locked loop ring oscillator being severely affected by single event effects, and to propose a ring oscillator applied to an anti-radiation phase-locked loop, to reduce or suppress the level transient caused by single particle bombardment, thereby solving the problem of the traditional ring oscillator being severely affected by single event effects. The technical scheme of the present application is as follows:

[0006] The present application provides a ring oscillator applied to an anti-radiation phase-locked loop, which comprises three delay units and a waveform shaping circuit, each delay unit adopts a wide tuning delay unit structure, and the three delay units are delay unit CELL1, CELL2 and CELL3, respectively.

[0007] Wherein, the delay unit CELL1, CELL2 and CELL3 are connected in a loop, the positive output of the delay unit CELL1 is connected to the negative input of the delay unit CELL2, the negative output of the delay unit CELL1 is connected to the positive input of the delay unit CELL2, the positive output of the delay unit CELL2 is connected to the negative input of the delay unit CELL3, the negative output of the delay unit CELL2 is connected to the positive input of the delay unit CELL3, the positive output of the delay unit CELL3 is connected to the negative input of the delay unit CELL1 and the positive input of the waveform shaping circuit, and the negative output of the delay unit CELL3 is connected to the positive input of the delay unit CELL1 and the negative input of the waveform shaping circuit; the waveform shaping circuit outputs as the output of the ring oscillator VCO.

[0008] Optionally, the delay unit of each stage comprises a positive input inverter module 1, a negative input inverter module 2, a PMOS differential cascade voltage switch logic 3, a NOMS differential cascade voltage switch logic 4 and a tail current tube module 5.

[0009] Wherein, the PMOS differential cascade voltage switch logic 3 and the NOMS differential cascade voltage switch logic 4 are both formed by a positive feedback loop using a back-to-back connected inverter structure, and under the action of the positive feedback, the recovery process of the circuit to the single event transient SET effect can be accelerated when a high-energy particle strikes the output node, so that the circuit has the ability to resist the single event transient SET.

[0010] The positive input inverter module 1 and the negative input inverter module 2 are oscillation period delay generation circuits, which realize frequency control by changing their own working current.

[0011] The tail current tube module 5 is directly controlled by the control voltage input by the oscillator, and the frequency is changed by changing the tail current size, which can reduce the single event sensitive node, thereby realizing the SET single event effect hardening.

[0012] Optionally, the positive input inverter module 1 is composed of an NMOS transistor M1 and a PMOS transistor M3, the gate terminals of M1 and M3 are connected and serve as the positive input port of the delay unit, the drain terminals of M1 and M3 are connected and serve as the negative output port of the delay unit, the source terminal of M3 is connected to the power supply, and the source terminal of M1 serves as a node P connected to the tail current tube module 5; the positive input inverter module 1 helps the three-stage delay unit oscillator output waveform to realize faster rising and falling.

[0013] Optionally, the negative input end inverter module 2 is composed of NMOS transistor M2 and PMOS transistor M4, the gate end of M2 and M4 is connected and used as the negative input port of the delay unit, the drain end of M2 and M4 is connected and used as the positive output port of the delay unit, the source of M4 is connected to the power supply, and the source of M2 is connected to node P and connected to the source of transistor M1 in the positive input end inverter module 1; the negative input end inverter module 2 helps the three-stage delay unit oscillator output waveform to realize faster rising and falling.

[0014] Optionally, the PMOS differential cascade voltage switch logic 3 is composed of two PMOS transistors M8 and M9, the gate of M8 is connected to the drain of M9 and the positive output port of the delay unit, the gate of M9 is connected to the drain of M8 and the negative output port of the delay unit, forming a negative resistance circuit connection, and the sources of M8 and M9 are connected to the power supply.

[0015] Optionally, the NMOS differential cascade voltage switch logic 4 is composed of two NMOS transistors M6 and M7, the gate of M6 is connected to the drain of M7 and the positive output port of the delay unit, the gate of M7 is connected to the drain of M6 and the negative output port of the delay unit, forming a negative resistance circuit connection, and the sources of M6 and M7 are connected to the ground.

[0016] Optionally, the tail current tube module 5 is composed of a current tube M5, the input control signal Vctrl of the VCO is connected to the gate of the transistor M5, the drain of M5 is connected to node P, node P is connected to the sources of transistors M1 and M2 in the positive input end inverter module 1 and the negative input end inverter module 2, and the source of M5 is connected to the ground.

[0017] The input control voltage Vctrl directly acts on the ring oscillator, the delay time of the delay unit is changed by changing the tail current value of the delay unit, so as to generate a clock signal of a corresponding frequency, with the increase of the control voltage Vctrl, the tail current source current of the delay unit gradually increases, so that the delay time of the delay unit continuously decreases, thereby linearly increasing the oscillation frequency of the VCO.

[0018] The beneficial effects of the present application are as follows:

[0019] Firstly, the input control voltage of the ring oscillator directly acts on the delay unit without additional bias circuit, thereby reducing the sensitive node of the oscillator, reducing the SET sensitivity, and reducing the circuit area consumption.

[0020] Secondly, the power supply of the double differential cascade voltage switch logic directly comes from the power supply voltage and the ground, and is not controlled by the tail current tube current, so that the elimination effect on SET is more stable.

[0021] The application will be described in further detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a schematic diagram of a ring oscillator applied to an anti-radiation phase-locked loop provided by the application;

[0023] Figure 2 is a circuit structure diagram of an anti-radiation wide-tuning delay unit provided by the application. DETAILED DESCRIPTION

[0024] The application will be described in further detail below with reference to the drawings and embodiments. However, the embodiments of the application are not limited thereto.

[0025] As shown in Figure 1 , the application provides a ring oscillator applied to an anti-radiation phase-locked loop, which comprises three-stage delay units and a waveform shaping circuit Buffer, each stage of the delay units adopts a wide-tuning delay unit structure, and the three-stage delay units are delay unit CELL1, CELL2 and CELL3 respectively.

[0026] Among them, the delay units CELL1, CELL2 and CELL3 are connected in a loop, the positive output end of the delay unit CELL1 is connected to the negative input end of the delay unit CELL2, the negative output end of the delay unit CELL1 is connected to the positive input end of the delay unit CELL2, the positive output end of the delay unit CELL2 is connected to the negative input end of the delay unit CELL3, the negative output end of the delay unit CELL2 is connected to the positive input end of the delay unit CELL3, the positive output end of the delay unit CELL3 is connected to the negative input end of the delay unit CELL1 and the positive input end of the waveform shaping circuit, and the negative output end of the delay unit CELL3 is connected to the positive input end of the delay unit CELL1 and the negative input end of the waveform shaping circuit; the output of the waveform shaping circuit is taken as the output of the ring oscillator VCO.

[0027] Since a typical ring oscillator generally comprises a bias circuit and a delay unit, the bias node in the bias circuit and the output node in the delay unit are sensitive nodes, the ring oscillator provided by the application only comprises the delay unit, and the bias circuit is not needed to provide a bias voltage for the delay unit, which is equivalent to reducing the sensitive nodes introduced in the bias circuit, so that reinforcement is realized.

[0028] Referring to Figure 2 , each stage of the delay unit comprises a positive input end inverter module 1, a negative input end inverter module 2, a PMOS differential cascade voltage switch logic 3, a NOMS differential cascade voltage switch logic 4 and a tail current tube module 5.

[0029] The PMOS differential cascade voltage switch logic 3 and the NMOS differential cascade voltage switch logic 4 are both formed by using the inverter structure connected back to back to form a positive feedback loop, and when high-energy particles bombard the output node, the recovery process of the circuit to the single event transient SET effect can be accelerated under the action of the positive feedback, so that the circuit has the single event transient SET resistance.

[0030] The positive input end inverter module 1 and the negative input end inverter module 2 are oscillation period delay generation circuits, which realize the frequency control by changing the working current.

[0031] The tail current tube module 5 is directly controlled by the control voltage input by the oscillator, the frequency is changed by changing the tail current, the single event sensitive node can be reduced, and the SET single event effect is reinforced.

[0032] It is worth noting that: the PMOS differential cascade voltage switch logic mainly uses the positive feedback formed by the circuit to accelerate the recovery process of the circuit to the SET effect, and reduces the influence caused by the particle bombardment. The NMOS differential cascade voltage switch mainly uses the positive feedback formed by the circuit to accelerate the recovery process of the circuit to the SET effect, and reduces the influence caused by the particle bombardment. The tail current tube module directly controls the transistor current by using the control voltage input by the ring oscillator, so as to control the delay time of the delay unit, thereby generating a clock signal with a corresponding frequency.

[0033] Reference Figure 2 As shown in the figure, the positive input end inverter module 1 is composed of NMOS transistor M1 and PMOS transistor M3, the gate ends of M1 and M3 are connected and serve as the positive input port of the delay unit, the drain ends of M1 and M3 are connected and serve as the negative output port of the delay unit, the source of M3 is connected to the power supply, and the source of M1 is connected to node P and connected to the tail current tube module 5; the positive input end inverter module 1 helps the three-stage delay unit oscillator output waveform to realize faster rising and falling.

[0034] The negative input end inverter module 2 is composed of NMOS transistor M2 and PMOS transistor M4, the gate ends of M2 and M4 are connected and serve as the negative input port of the delay unit, the drain ends of M2 and M4 are connected and serve as the positive output port of the delay unit, the source of M4 is connected to the power supply, and the source of M2 is connected to node P and connected to the source of transistor M1 in the positive input end inverter module 1; the negative input end inverter module 2 helps the three-stage delay unit oscillator output waveform to realize faster rising and falling.

[0035] The PMOS differential cascade voltage switch logic 3 is composed of two PMOS transistors M8 and M9, the gate of M8 is connected to the drain of M9 and the positive output port of the delay unit, the gate of M9 is connected to the drain of M8 and the negative output port of the delay unit, forming a negative resistance circuit connection, and the sources of M8 and M9 are both connected to the power supply.

[0036] The NMOS differential cascade voltage switch logic 4 is composed of two NMOS transistors M6 and M7, the gate of M6 is connected to the drain of M7 and the positive output port of the delay unit, the gate of M7 is connected to the drain of M6 and the negative output port of the delay unit, forming a negative resistance circuit connection, and the sources of M6 and M7 are both connected to the ground.

[0037] The tail current tube module 5 is composed of a current tube M5, the input control signal Vctrl of the VCO is connected to the gate of the transistor M5, the drain of M5 is connected to node P, node P is connected to the sources of transistors M1 and M2 in the positive input end inverter module 1 and the negative input end inverter module 2, and the source of M5 is connected to the ground.

[0038] The input control voltage Vctrl directly acts on the ring oscillator, the delay time of the delay unit is changed by changing the tail current value of the delay unit, so as to generate a clock signal of a corresponding frequency, with the increase of the control voltage Vctrl, the tail current source current of the delay unit gradually increases, so that the delay time of the delay unit continuously decreases, thereby linearly increasing the oscillation frequency of the VCO.

[0039] The application is applied to the working principle of the ring oscillator of the anti-radiation phase-locked loop as follows:

[0040] For the three-stage oscillator, the loop gain must meet the Barkhausen criterion, first, the three-stage ring oscillator needs to make the direct current phase shift 540°, that is, 180°, and the frequency-dependent phase shift 180°, that is, each stage can provide a phase shift of 60°, so the low-frequency gain of each delay unit needs to be greater than or equal to 2 to oscillate, considering the deviation of temperature and process, the low-frequency gain of the delay unit is usually designed to be twice or three times of the required value. Second, the starting loop gain needs to be greater than 1, and the stable loop gain is equal to 1, because it is difficult to start, the starting loop gain is generally 2-3 times of the stable loop gain. Because the input differential pair works in the linear region for most of the time during oscillation, the oscillator output is a sine wave rather than a square wave, and the output node voltage waveform is almost similar to a sine waveform, the waveform is regular, and has a large transition period.

[0041] For the irradiation effect of voltage controlled oscillator, the response of SET effect in VCO is relatively complex. After the VCO is affected by single event effect, the amplitude, frequency or phase of the output signal will change. Since the phase error caused by SET effect is the most concerned point in analyzing the whole PLL system, only the changes of phase and frequency are considered, and the difference in amplitude is ignored.

[0042] The sensitive nodes of delay cell are generally bias node and output node. When the sensitive node in delay cell is bombarded by SET, the charge will be deposited or stored on the node, and the voltage on the node remains disturbed, affecting the amplitude and phase of the output signal, and finally leading to oscillation failure until the charge dissipates and the disturbance is eliminated. Therefore, the sensitive nodes need to be reduced, or the size of single event transient current caused by particle bombardment at the sensitive node, so as to reduce the phase and frequency changes of VCO. Since the delay cell of VCO in PLL is always in oscillation state, the oscillation waveform has periodicity in 2π, therefore the response of differential ring oscillator to SET pulse also changes with the period 2π, and the SET effect generated at different times is different, that is, the SET response of VCO has time-varying characteristics. The main reason is that the phase deviation value is directly related to the voltage gain at the time of bombardment, and is also affected by the amplitude and pulse width of the injected current, the internal structure of the circuit, the signal change trend, the SET transient direction and other factors. Therefore, the structure of the circuit itself and the parameters of the related transistors will affect the SET response of VCO.

[0043] The working principles of PMOS differential cascade voltage switch logic 3 and NMOS differential cascade voltage switch logic 4 are described in detail below.

[0044] The transistors in reverse cross connection form two back-to-back connected inverter structures, and the two inverter structures that bite each other form a positive feedback loop. When high-energy particles bombard the output node, the recovery process of the circuit to SET effect can be accelerated under the action of positive feedback, so that the circuit has a certain anti-SET ability, and no other bias node sensitive to SET is introduced. Although the drain node of the tail current source still exists, the SET effect generated at this node will be consumed by the delay cell, and it is not sensitive to SET. The main idea is to accelerate the influence of SET, reduce the SET sensitive nodes, and use the positive feedback of the loop to reduce and accelerate the recovery process of SET effect, so as to reduce the SET sensitivity of the circuit. Compared with related works, the VCO has better reinforcement effect, fewer sensitive nodes, smaller area and lower power consumption.

[0045] The application provides a voltage-controlled oscillator applied to an anti-radiation phase-locked loop, comprising a three-stage delay unit and a waveform shaping circuit. When the sensitive node of the delay unit is bombarded by high-energy particles, a single event transient current is generated at the node, which changes the phase and frequency of the VCO. The three-stage delay unit utilizes the positive feedback loop formed by the reverse cross circuit, and based on the single event effect transient current characteristics, accelerates the recovery process of the bombarded node of the delay circuit to the SET effect, so that the circuit recovers the irradiation effect faster, and has a certain anti-SET capability. In addition, the application does not introduce a SET-sensitive bias node, although the tail current source drain node still exists, but the SET effect generated at the node will be consumed by the delay unit, which is not sensitive to SET. The application can effectively alleviate the irradiation effect on the voltage-controlled oscillator in the phase-locked loop, and has strong anti-single particle bombardment capability, and has little effect on the normal working state of the phase-locked loop.

[0046] In addition, the terms "first", "second", "third", etc. are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0047] Although the application is described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art by viewing the drawings, disclosure and appended claims in the implementation of the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude a plurality.

[0048] The above is a further detailed description of the application in conjunction with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the application to these descriptions. For those skilled in the art, without departing from the concept of the application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the application.

Claims

1. A ring oscillator applied to a radiation-resistant phase-locked loop, characterized in that, It includes three-stage delay units and waveform shaping circuits. Each stage of the delay unit adopts a wide-tuning delay unit structure. The three-stage delay units are delay units CELL1, CELL2 and CELL3. In this circuit, delay units CELL1, CELL2, and CELL3 are connected in a loop. The positive output of delay unit CELL1 is connected to the negative input of delay unit CELL2, the negative output of delay unit CELL1 is connected to the positive input of delay unit CELL2, the positive output of delay unit CELL2 is connected to the negative input of delay unit CELL3, the negative output of delay unit CELL2 is connected to the positive input of delay unit CELL3, the positive output of delay unit CELL3 is connected to the negative input of delay unit CELL1 and the positive input of waveform shaping circuit, and the negative output of delay unit CELL3 is connected to the positive input of delay unit CELL1 and the negative input of waveform shaping circuit. The output of the waveform shaping circuit serves as the output of the ring oscillator VCO. Each delay unit includes a positive input inverter module (1), a negative input inverter module (2), a PMOS differential cascade voltage switching logic (3), a NOMS differential cascade voltage switching logic (4), and a tail current transistor module (5). The positive input inverter module (1) consists of NMOS transistor M1 and PMOS transistor M3. The gates of M1 and M3 are connected and serve as the positive input port of the delay unit. The drains of M1 and M3 are connected and serve as the negative output port of the delay unit. The source of M3 is connected to the power supply. The source of M1 is connected as node P and connected to the tail current transistor module (5). The negative input inverter module (2) consists of NMOS transistor M2 and PMOS transistor M4. The gates of M2 and M4 are connected and serve as the negative input port of the delay unit. The drains of M2 and M4 are connected and serve as the positive output port of the delay unit. The source of M4 is connected to the power supply. The source of M2 is connected to node P and connected to the source of transistor M1 in the positive input inverter module (1). The PMOS differential cascaded voltage switch logic (3) is composed of two PMOS transistors M8 and M9. The gate of M8 is connected to the drain of M9 and the positive output port of the delay unit, and the gate of M9 is connected to the drain of M8 and the negative output port of the delay unit, forming a negative resistance circuit connection. The sources of M8 and M9 are both connected to the power supply. The NMOS differential cascaded voltage switching logic (4) is composed of two NMOS transistors M6 and M7. The gate of M6 is connected to the drain of M7 and the positive output port of the delay unit, and the gate of M7 is connected to the drain of M6 and the negative output port of the delay unit, forming a negative resistance circuit connection. The sources of M6 and M7 are both connected to ground. The tail current transistor module (5) is composed of a current transistor M5. The input control signal Vctrl of VCO is connected to the gate of transistor M5. The drain of M5 is connected to node P. Node P is connected to the source of transistors M1 and M2 in the positive input inverter module (1) and the negative input inverter module (2). The source of M5 is connected to ground.

2. The ring oscillator applied to a radiation-resistant phase-locked loop according to claim 1, characterized in that, The PMOS differential cascaded voltage switch logic (3) and NOMS differential cascaded voltage switch logic (4) both utilize a back-to-back connected inverter structure to form a positive feedback loop. When high-energy particles bombard the output node, the positive feedback can accelerate the circuit's recovery process from the single-event transient (SET) effect, enabling the circuit to resist SET. The positive input inverter module (1) and the negative input inverter module (2) are circuits for generating oscillation period delay. The frequency is controlled by changing its own operating current. The tail current tube module (5) is directly controlled by the control voltage input from the oscillator. By changing the magnitude of its tail current, the frequency can be changed, which can reduce the number of single-event sensitive nodes and thus achieve SET single-event hardening.

3. The ring oscillator applied to a radiation-resistant phase-locked loop according to claim 1, characterized in that, The positive input inverter module (1) helps the output waveform of the three-stage delay unit oscillator achieve a faster rise and fall transition.

4. The ring oscillator applied to a radiation-resistant phase-locked loop according to claim 1, characterized in that, The negative input inverter module (2) helps the output waveform of the three-stage delay unit oscillator achieve a faster rise and fall transition.

5. The ring oscillator applied to a radiation-resistant phase-locked loop according to claim 1, characterized in that, The input control signal Vctrl acts directly on the ring oscillator, changing the delay time of the delay unit by altering the tail current value, thereby generating a clock signal of the corresponding frequency. As the control voltage Vctrl increases, the tail current source current of the delay unit gradually increases, causing the delay time of the delay unit to continuously decrease, thus linearly increasing the oscillation frequency of the VCO.

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