Low-clock spread spectrum chip synchronization system and method based on parallel PMF-FFT

Abstract

The present invention discloses a low-clock spread spectrum code chip synchronization system and method based on parallel PMF-FFT. The system of the present invention includes a parallel AD sampling module, a parallel code chip phase modulation module, a parallel PMF-FFT module and an FFT peak decision module. The present invention adopts a parallel code chip phase shifting method, so that the system increases the number of sampling points involved in the code chip synchronization calculation without increasing the clock frequency, thereby improving the calculation accuracy of the code chip synchronization. The parallel code chip phase modulation method is adopted, so that the present invention improves the phase resolution of the spread spectrum code chip synchronization without increasing the clock rate, thereby improving the phase accuracy of the spread spectrum code synchronization. The present invention enables the system to achieve spread spectrum code chip synchronization with high calculation accuracy and code chip phase accuracy at a low clock rate, thereby improving the performance of spread spectrum code chip synchronization in clock-constrained scenarios.

Description

Technical Field

[0001] The present invention belongs to the field of wireless communication technology, and further relates to a chip synchronization system and method based on parallel partial matched filter-fast Fourier transform (PMF-FFT) under limited system clock frequency in spread spectrum communication technology. The present invention fine-tunes the phase of parallel spread spectrum chips and combines the use of parallel PMF-FFT method to achieve chip synchronization, so that the system can achieve high-precision spread spectrum code chip synchronization at a low clock rate. Background Art

[0002] The transmitter of the spread spectrum communication system uses a spread spectrum sequence generator to process the narrowband signal through the spread spectrum. The receiver uses chip synchronization to align the chip of the local spread spectrum code sequence of the received signal with the phase of the local spread spectrum code sequence, and despreads the aligned chip to convert it into the initial narrowband signal to complete the transmission of information. Chip synchronization is divided into two steps: capture and tracking. Tracking requires the system to have a high chip synchronization accuracy. Due to the constraints of the system operating frequency, traditional spread spectrum systems usually use the signal extraction collected by the digital-to-analog converter ADC to convert it into a low-speed serial data stream to achieve signal despreading. However, in a large-bandwidth spread spectrum system, the accuracy of chip synchronization will be reduced, affecting the system's anti-noise performance.

[0003] Shanghai Jiao Tong University has published a method for parallel despreading of high-speed data using a parallel AD sampling module in its patent document "A chip synchronization method for parallel despreading of direct sequence spread spectrum" (application date: 2012.09.10, application number 201210332769.4, application publication number: CN 102857251A). This method extracts the local spread code sequence at a specified rate to obtain D groups of spread code sequences, correlates the parallel data of each channel received by the receiving end with the local spread code sequence, obtains D groups of independent data, compares the peak values ​​of the D groups of correlation results, and determines the position of the chip offset according to the maximum peak value. The disadvantage of this method is that this method correlates the parallel data of D channels with the local spread code sequence separately to obtain D groups of independent correlation results, and only selects the signal result of one channel with a correlation peak for judgment. The size of the correlation peak is ultimately determined by the channel with the largest peak value among the D channels. The calculation results of other channels will be ignored, which will cause certain performance loss to the system.

[0004] The Shanghai Institute of Aerospace Electronics and Communications Equipment has published a PMF-FFT measurement and control signal capture device and method in its patent application "PMF-FFT measurement and control signal capture device and method" (application date: 2021.01.25, application number 202110101490.4, application publication number: CN 112910498A). The device consists of a digital down-conversion module, a PMF module, an FFT module, a peak detection module, a code generation module, a code phase compensation module, a cyclic control module and a Tang detection module. The device adopts an extraction strategy for the AD sampling data, and the extracted signal frequency is the frequency f s , the code frequency is f c , the captured code phase resolution is f s / f c The code chip synchronization of the spread spectrum signal is realized by using the PMF module and the FFT module, and the same correlator structure is used to adjust the search range of the code phase by controlling the number of cycles, thereby achieving capture and tracking. However, the disadvantage of this device is that the code phase resolution is only related to the extracted signal frequency f s Sum code frequency f c The signal frequency f s Since the hardware limit is usually not too high, this will result in the system code frequency f c When it is higher, the code phase resolution of the system will be too low, which will seriously affect the accuracy of code chip synchronization and reduce system performance. Summary of the invention

[0005] The purpose of the present invention is to address the defects of the above-mentioned prior art and propose a low-clock spread spectrum code chip synchronization system and method based on parallel PMF-FFT, which is used to solve the problem of low pseudo-code synchronization accuracy in spread spectrum communication systems when the operating frequency of FPGA is limited.

[0006] The specific idea for achieving the purpose of the present invention is that the parallel code chip phase shifting method in the synchronization method of the present invention fine-tunes the phase of the parallel spread spectrum code chips at the same time, expands the phase information of the code chips from a single channel to multiple channels, and increases the phase resolution of the spread spectrum code chips exponentially. The parallel PMF-FFT method in the synchronization method of the present invention uses parallel PMF-FFT capture of parallel code chips, which increases the number of sampling points of the PMF-FFT algorithm, can increase the calculation accuracy of the system, and improve the performance of the system's code chip synchronization. The parallel code chip phase adjustment module in the system of the present invention adjusts the phase of multiple parallel data in real time according to the input code chip length, so that the system can use a low-speed clock to fine-tune the phase of the parallel code chips throughout the process, meeting the needs of high-precision spread spectrum code chip synchronization at a low clock rate.

[0007] The technical scheme for achieving the purpose of the present invention is as follows.

[0008] The system of the present invention comprises a parallel AD sampling module, a parallel chip phase modulation module, a multi-channel parallel PMF-FFT module, and an FFT peak value judgment module; wherein:

[0009] The parallel AD sampling module is used to sample the spread spectrum signal transmitted by the transmitting end of the spread spectrum system by means of interleaved sampling, obtain multi-channel parallel spread spectrum signals with different phases corresponding to the multi-phase output in the interleaved sampling, and input the multi-channel parallel spread spectrum signals into the parallel chip phase modulation module;

[0010] The parallel chip phase modulation module comprises a data cache unit, a parallel phase modulation unit, a channel switching unit and a ping-pong gating unit; the data cache unit in the parallel chip phase modulation module is used to cache the parallel spread spectrum signals at the same time, and address the data in the parallel shift register from 0 to obtain the multi-channel parallel cache to be phase-modulated; the parallel phase modulation unit in the parallel chip phase modulation module comprises a starting address register, which is used to output the data corresponding to the multi-channel parallel signals in the data cache unit starting from the starting address to obtain the parallel phase modulation data of different phases, and input the parallel phase modulation data into the channel switching unit; the channel switching unit comprises two output A channel and a code tail register are used to control the parallel phase modulation data to be output alternately in two output channels to obtain parallel code chips of two channels, and at the same time, the starting address register in the parallel phase modulation unit is updated to the remainder of the sum of the value of the address register and the previous code length divided by the phase number of the parallel signal, and the parallel code chips of the two channels are input into the ping-pong gating unit; the ping-pong gating unit is used to detect the channel where the effective signal changes from 0 to 1, output the parallel code chips of the output channel, obtain the parallel code chips after phase modulation, and input the parallel code chips after phase modulation into the multi-channel parallel PMF-FFT module, and at the same time generate a frame header pulse signal and input it into the parallel PMF-FFT module;

[0011] The parallel PMF-FFT module includes a parallel spread spectrum code sequence generation unit, a parallel partial matched filtering unit and a fast Fourier transform unit; the parallel spread spectrum code sequence generation unit includes three sets of parallel ROMs storing local parallel spread spectrum code sequences, which are used to read the local parallel spread spectrum code sequences from the ROMs, align the local parallel spread spectrum code sequences of the three branches with the parallel code chips after phase modulation with the position of the frame header pulse signal as the starting position, obtain the three sets of aligned local parallel spread spectrum code sequences, and input the three sets of aligned local parallel spread spectrum code sequences into the parallel partial matched filtering unit; the parallel partial matched filtering unit includes three sets of matched A matching filter is used to perform parallel correlation calculations on the three groups of aligned local parallel spread spectrum code sequences and the parallel code chips after phase modulation, add and merge the multi-channel calculation results of each group to obtain three groups of single-channel serial calculation results, divide the three groups of single-channel serial calculation results into segments at equal intervals according to the intervals of the matching filter order, sum the data of each segment, obtain the code chip PMF results of the three branches, and input the PMF results of the three branches into a fast Fourier transform unit; the fast Fourier transform unit is used to perform fast Fourier transform on the PMF results of the three branches to obtain the PMF spectrum of the three branches, and input the spectrum into an FFT peak decision module;

[0012] The FFT peak decision module includes a synchronization locking unit, a peak decision unit, a code length adjustment unit and a code length output unit; the synchronization locking unit is used to judge whether the maximum value of the spectrum in the three branches exceeds a preset threshold, obtain a synchronization locking signal, and input the synchronization locking signal into the peak decision unit and the code length adjustment unit; the peak decision unit is used to retrieve the branch with the largest PMF peak among the leading branch, the middle branch and the lagging branch, obtain a peak comparison result, and input the peak comparison result into the code length adjustment unit; the code length adjustment unit includes a phase shift period and an observation period, which are used to adjust the size of the code length signal in the phase shift period and the observer according to the comparison result between the synchronization locking signal and the peak value, and input the code length signal into the parallel code chip phase modulation module, so as to realize the system's spread spectrum code chip synchronization through continuous iteration.

[0013] The specific steps of the synchronization method of the present invention include the following:

[0014] Step 1: The parallel AD sampling module collects multiple parallel digital signals:

[0015] The parallel AD sampling module at the receiving end of the spread spectrum communication system samples the spread spectrum signal transmitted by the transmitting end of the spread spectrum system by means of interleaved sampling, obtains multi-channel parallel spread spectrum signals of different phases corresponding to the multi-phase output in the interleaved sampling, and inputs the multi-channel parallel spread spectrum signals into the parallel chip phase modulation module;

[0016] Step 2: Use the parallel chip phase modulation method to adjust the phase of the multi-channel parallel spread spectrum signal:

[0017] Step 2.1, a data cache unit uses a parallel shift register corresponding to the parallel spread spectrum signal to cache the parallel spread spectrum signal at the same time, and addresses the data in the parallel shift register starting from 0 to obtain a multi-channel parallel cache to be phase-modulated;

[0018] Step 2.2, the parallel phase modulation unit uses the starting address register to record the starting address of the current unit, starts from the starting address in the multi-channel parallel buffer, outputs the data corresponding to the multi-channel parallel signals, obtains parallel phase modulation data of different phases, and inputs the parallel phase modulation data into the channel switching unit;

[0019] Step 2.3, the current output channel of the channel switching unit outputs the parallel phase modulation data in parallel at the same time, and sets the effective signal of the channel to 1. After each output of the parallel phase modulation data, the value of the output counter is increased by the phase number corresponding to the parallel code chip. When the output counter is greater than the length of the current code chip, the effective signal of the current output channel is set to 0, and the output counter is cleared to obtain a group of parallel code chips.

[0020] Step 2.4, the code tail register of the channel switching unit takes the value of the last group of parallel data in the parallel code chip, reads the value of the start address register in the parallel phase modulation unit, adds the value of the code tail register to the value of the start address register, and if the result is less than the phase number of the parallel code chip, then while the current output channel outputs the last group of data of the parallel code chip, the other output channel directly outputs the first group of data of the next parallel code chip, and sets the valid signal of the other output channel to 1, otherwise, the other output channel outputs the next parallel code chip after the current output channel outputs the code chip, and obtains the parallel code chip to be selected;

[0021] Step 2.5, after the parallel code chips are output, the starting address register in the parallel phase modulation unit is updated to the remainder of the sum of the address register value and the previous code length divided by the phase number of the parallel signal;

[0022] Step 2.6, when the ping-pong gating unit detects that the valid signal of any output channel changes from 0 to 1, a frame header pulse signal is generated and input into the parallel PMF-FFT module, and the parallel code chips of the output channel are output to obtain the phase-modulated parallel code chips, and are input into the multi-channel parallel PMF-FFT module;

[0023] Step 3, use the multi-channel parallel PMF-FFT method to obtain the PMF spectrum of the parallel code chips after phase modulation:

[0024] Step 3.1, with a number of bits less than the number of phases of the parallel signal, the local parallel spread spectrum code sequence is moved in the leading direction and the lagging direction respectively to obtain the parallel spread spectrum codes of the leading branch and the lagging branch, and the parallel spread spectrum codes of the three branches are stored in the ROM of the parallel spread spectrum code sequence generation unit;

[0025] Step 3.2, the parallel spread spectrum code sequence generation unit reads the local parallel spread spectrum code sequence from the ROM, takes the position of the frame header pulse signal as the starting position, aligns the local parallel spread spectrum code sequences of the three branches with the parallel code chips after phase modulation, obtains three groups of aligned local parallel spread spectrum code sequences, and inputs the three groups of aligned local parallel spread spectrum code sequences into the parallel partial matched filtering unit;

[0026] Step 3.3, the parallel partial matched filter unit performs parallel correlation calculations on the three groups of aligned local parallel spread spectrum code sequences and the parallel code chips after phase modulation, adds and merges the multi-path calculation results of each group to obtain three groups of single-path serial calculation results, divides the three groups of single-path serial calculation results into segments at equal intervals according to the interval of the matched filter order, sums the data of each segment, obtains the code chip PMF results of the three branches, and inputs the PMF results of the three branches into the fast Fourier transform unit;

[0027] Step 3.4, the fast Fourier transform unit performs fast Fourier transform on the PMF results of the three branches to obtain the PMF spectrum of the three branches, and inputs the spectrum into the FFT peak decision module;

[0028] Step 4: Make decision phase shifts on the PMF spectra of the three branches:

[0029] Step 4.1, when the synchronization locking unit detects that the peak value of the PMF spectrum of any of the three branches exceeds the preset threshold, the synchronization locking signal is set to 1; otherwise, the synchronization locking signal is set to 0, and the obtained synchronization locking signal is input into the peak judgment unit and the code length adjustment unit;

[0030] Step 4.2, the peak decision unit compares the PMF peaks in the leading branch, the middle branch and the lagging branch to obtain a peak comparison result, and inputs the peak comparison result into the code length adjustment unit;

[0031] Step 4.3, when the code length adjustment unit detects that the synchronization lock signal is 0, the code length is set to a number less than the length of the local spread spectrum code sequence; if the synchronization lock signal is 1 and the peak value of the leading branch is the largest, the next code length is set to the length of the local spread spectrum code sequence during the observation period, and the next code length is set to the length of the local spread spectrum code sequence minus 1 during the phase shift period; if the synchronization lock signal is 1 and the peak value of the lagging branch is the largest, the next code length is set to the length of the local spread spectrum code sequence during the observation period, and the next code length is set to the length of the local spread spectrum code sequence plus 1 during the phase shift period; otherwise, the next code length is set to the length of the local spread spectrum code sequence during both the observation period and the phase shift period;

[0032] Step 5: The code length output unit inputs the next code length into the parallel chip phase modulation module.

[0033] Compared with the prior art, the present invention has the following advantages:

[0034] First, since the parallel code chip phase modulation module in the system of the present invention directly adjusts the phase of the parallel code chip, the code phase resolution of the spread spectrum code in the present invention is multiplied, which overcomes the disadvantage that the spread spectrum code phase resolution of the prior art is insufficient when the system operating frequency is limited, resulting in too low code chip synchronization accuracy. The parallel code chip phase modulation module in the system of the present invention performs phase modulation operations on parallel data with a fixed phase relationship at the receiving end in real time according to the size of the input code length, so that the system of the present invention can achieve high-precision spread spectrum code chip synchronization at a low clock rate, reduce the requirements for the hardware operating frequency, and improve the stability of the system.

[0035] Second, because the method of the present invention uses a parallel code chip phase modulation method to adjust the phase of multiple parallel digital signals, the spread spectrum code chips of the present invention have a higher phase resolution at the same clock rate, overcoming the defect in the prior art that when the working clock is limited, the spread spectrum code chip phase resolution in the demodulation process at the receiving end is too low, resulting in a large phase error of code chip synchronization. The present invention improves the code chip synchronization accuracy of the spread spectrum code at a low clock rate.

[0036] Third, because the method of the present invention uses a multi-path parallel PMF-FFT method to obtain the PMF spectrum of the parallel code bits after phase modulation, compared with the prior art, the present invention can multiply the number of sampling points participating in the PMF-FFT algorithm when the working clock frequency is the same, thereby overcoming the problem in the prior art that when the working clock is limited, the number of calculation points participating in the code bit synchronization is insufficient, resulting in excessive calculation errors, thereby improving the calculation accuracy of the PMF spectrum. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural schematic diagram of the system of the present invention;

[0038] Figure 2A schematic diagram of the working principle of the parallel PMF-FFT module in the system of the present invention;

[0039] Figure 3 is a flow chart of the synchronization method of the present invention;

[0040] Figure 4 It is a flow chart of the parallel chip phase modulation method in the synchronization method of the present invention;

[0041] Figure 5 It is a timing diagram of the data overlapping moment in the synchronization method of the present invention;

[0042] Figure 6 It is a flow chart of the parallel PMF-FFT method in the synchronization method of the present invention. DETAILED DESCRIPTION

[0043] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0044] Reference Figure 1 The system structure of the embodiment of the system of the present invention is further described.

[0045] The embodiment of the system of the present invention transmits a spread spectrum signal generated by spreading the spectrum of a spread spectrum code sequence of a CDMA terminal with a code length of 512 to a terminal device in the CDMA system through a base station in the CDMA system. The terminal device in the CDMA system uses the method of the present invention to synchronize the code chips in the spread spectrum signal transmitted by the base station in the CDMA system received by the receiving end of the terminal device with the code chips of the local spread spectrum code sequence of the terminal device.

[0046] The system of the embodiment of the present invention includes a parallel AD sampling module, a parallel chip phase modulation module, a parallel PMF-FFT module and an FFT peak decision module. The parallel PMF-FFT module is based on a local parallel pseudo-random sequence. Wherein:

[0047] The parallel AD sampling module is used to convert the spread spectrum signal transmitted by the base station in the CDMA system into four parallel digital signals with four different phases, and input the four parallel digital signals into the parallel block phase shifting module.

[0048] The parallel chip phase modulation module includes a data cache unit, a parallel phase modulation unit, a channel switching unit and a ping-pong gating unit. The parallel data cache unit is used to cache the four parallel digital signals input by the parallel AD sampling module through four two-stage shift registers at the same time, and address the data of the shift registers to obtain the four parallel caches to be phase-shifted. The parallel phase modulation unit is used to read the phase-modulated parallel data from the cache according to the current starting address. The channel switching unit includes a horsetail register and two output channels, channel A and channel B, which are used to control the parallel phase modulation data to be output alternately in the two output channels to obtain the parallel chips of the two channels, and input the parallel chips of the two channels into the ping-pong gating unit; the ping-pong gating unit is used to gate the parallel chips of different channels to output in the same output channel to obtain the parallel chips after phase modulation, and input the parallel chips after phase modulation into the parallel PMF-FFT module.

[0049] See attached Figure 2 The parallel PMF-FFT module of the embodiment of the present invention is further described.

[0050] The parallel PMF-FFT module includes a parallel spread spectrum code sequence generation unit, a parallel partial matched filter unit and a fast Fourier transform unit; the parallel spread spectrum code sequence generation unit includes three groups of parallel ROMs storing local parallel spread spectrum code sequences, which are used to read the local parallel spread spectrum code sequences from the ROMs, align the local parallel spread spectrum code sequences of the three branches with the parallel code chips after phase modulation with the position of the frame header pulse signal as the starting position, obtain the three groups of aligned local parallel spread spectrum code sequences, and input the three groups of aligned local parallel spread spectrum code sequences into the parallel partial matched filter unit; the parallel partial matched filter unit , used to perform parallel correlation calculations on the three groups of aligned local parallel spread spectrum code sequences and the parallel code chips after phase modulation, add and merge the four-way calculation results of each group to obtain three groups of single-way serial calculation results, divide the three groups of single-way serial calculation results into segments at intervals of 4, sum the data of each segment, obtain the code chip PMF results of the three branches, and input the PMF results of the three branches into a fast Fourier transform unit; the fast Fourier transform unit is used to perform a 128-point fast Fourier transform on the PMF results of the three branches to obtain the PMF spectrum of the three branches, and input the spectrum into an FFT peak decision module;

[0051] The FFT peak decision module includes a synchronization locking unit, a peak decision unit, a code length adjustment unit and a code length output unit. The synchronization locking unit is used to set the synchronization locking signal to 1 or 0 according to whether the peak value of the PMF spectrum of any branch in the three branches exceeds the preset threshold, and input the synchronization locking signal into the peak decision unit and the code length adjustment unit. The peak decision unit is used to retrieve the branch with the largest PMF peak value among the leading branch, the middle branch and the lagging branch, obtain the peak comparison result, and input the peak comparison result into the code length adjustment unit. The code length adjustment unit includes an observation period and a phase shift period. The observation period is used to obtain the peak comparison result, and the phase shift period is used to change the value of the code length signal according to the value of the synchronization locking signal and the peak comparison result, so that the chip phase moves in different directions. The code length output unit is used to input the lower code length signal into the parallel chip phase adjustment module, and through continuous feedback iteration, the phase of the receiving end spread spectrum code chip is aligned with the phase of the local spread spectrum sequence to achieve the system's spread spectrum code chip synchronization.

[0052] Reference Figure 3 The implementation steps of the embodiment of the method of the present invention are further described.

[0053] Step 1: The parallel AD sampling module collects four parallel digital signals.

[0054] The parallel AD sampling module in the terminal equipment of the CDMA system uses a sampling clock with 0, π and The four ADCs with phase relationship are interleaved for sampling, and the spread spectrum signal with a code rate of 40MHz transmitted by the base station in the CDMA system is converted into four parallel digital signals with four different phases. The sampling rate of each digital signal is 40MHz, and the four parallel digital signals are input into the parallel code chip phase modulation module.

[0055] Step 2: Use the parallel chip phase modulation method to adjust the phases of the four parallel digital signals.

[0056] Reference Figure 4 The parallel chip phase modulation method of the present invention is further described.

[0057] Step 2.1, the data cache unit caches the four parallel digital signals input by the parallel AD sampling module simultaneously through four two-stage shift registers, and addresses the data of the shift registers. The four registers of the first stage are in the order of the four channels, and the addresses are 4, 5, 6, and 7 respectively. The registers of the second stage refer to the order of the four channels, and the addresses are 0, 1, 2, and 3 respectively, to obtain the four-way parallel cache to be shifted.

[0058] Step 2.2, the parallel phase modulation unit uses the starting address register to record the starting address addr of the current unit and starts from the starting address data, and sequentially outputs the four data with addresses addr, addr+1, addr+2 and addr+3 from the four parallel caches to be phase-shifted at the same time in parallel to obtain four-way parallel phase modulation data, and inputs the parallel phase modulation data into the channel switching unit.

[0059] Step 2.3, the current output channel of the channel switching unit outputs the parallel phase-modulated data in parallel at the same time, and sets the effective signal of the channel to 1. After each output of the parallel phase-modulated data, the value of the output counter is increased by 4. When the output counter is greater than the length of the current code piece, the effective signal of the current output channel is set to 0, and the output counter is cleared to obtain a set of parallel codes.

[0060] Step 2.4, the code tail register of the channel switching unit takes the number of the last set of parallel data in the parallel code chip, reads the value of the start address register in the parallel phase modulation unit, adds the value of the code tail register to the value of the start address register, and if the addition result is less than 4, while the current output channel outputs the last set of data of the parallel code chip, the other output channel directly outputs the first set of data of the next parallel code chip. Otherwise, the other output channel outputs the next parallel code chip after the current output channel finishes outputting the code chip, and obtains the parallel code chip to be selected.

[0061] Reference Figure 5 The case where the sum in step 2.4 is less than 4 is further described. Figure 5 (a), the starting address is 1, and the number of the last set of parallel data is 2. At this time, the data in the cache needs to be output immediately, otherwise the data 16 in the cache will be lost at the next moment. Figure 5 (b) While channel A outputs the last set of data 14 and 15 of the current black code piece, channel B directly outputs the first set of data 16 to 19 of the next set of gray code pieces and sets the valid signal of channel B to 1.

[0062] Step 2.5, after the parallel code chips are output, the start address register in the parallel phase modulation unit is updated to the remainder of the sum of the address register value and the previous code length divided by 4.

[0063] Step 2.6, when the ping-pong gating unit detects that the valid signal of any output channel changes from 0 to 1, it generates a frame header pulse signal and inputs it into the parallel PMF-FFT module, outputs the parallel code chips of the output channel, obtains the phase-modulated parallel code chips, and inputs them into the multi-channel parallel PMF-FFT module.

[0064] Step 3, using a multi-channel parallel PMF-FFT method to obtain the PMF spectrum of the parallel code chips after phase modulation.

[0065] See attached Figure 6 The system parallel PMF-FFT acquisition method of the present invention is further described.

[0066] Step 3.1, oversample the standard serial spread spectrum code of length 512 by four times and store it in parallel to obtain a local parallel spread spectrum code sequence, shift the local parallel spread spectrum code sequence by 3 bits in the leading direction and the lagging direction respectively to obtain parallel spread spectrum codes of the leading branch and the lagging branch of length 2048, and store the parallel spread spectrum codes of the three branches in the ROM of the parallel spread spectrum code sequence generation unit.

[0067] Step 3.2, the parallel spread spectrum code sequence generation unit reads the local parallel spread spectrum code sequence from the ROM, takes the position of the frame header pulse signal as the starting position, aligns the local parallel spread spectrum code sequences of the three branches with the parallel code bits after phase modulation, and obtains three groups of aligned local parallel spread spectrum code sequences, and inputs the three groups of aligned local parallel spread spectrum code sequences into the parallel partial matching filter unit.

[0068] Step 3.3, the parallel partially matched filter unit performs parallel correlation calculations on the three groups of aligned local parallel spread spectrum code sequences and the four parallel code bits after phase modulation, adds and combines the four-way calculation results of each group to obtain three groups of single-way serial calculation results, divides the three groups of single-way serial calculation results into segments at equal intervals of 4 bits, sums the data of each segment, obtains the code bit PMF results of the three branches, and inputs the PMF results of the three branches into the fast Fourier transform unit.

[0069] Step 3.4, the fast Fourier transform unit performs a fast 128-point Fourier transform on the PMF results of the three branches to obtain the PMF spectra of the three branches, and inputs the spectra into the FFT peak decision module.

[0070] Step 4: Decision-making phase shifting is performed on the PMF spectra of the three branches.

[0071] Step 4.1, when the synchronization locking unit calculates the ratio of the maximum value to the average value of the PMF spectrum of any branch among the three branches, when the ratio exceeds the preset threshold value 16, the synchronization locking signal is set to 1; otherwise, the synchronization locking signal is set to 0 and the synchronization locking signal is input into the peak decision unit and the code length adjustment unit.

[0072] Step 4.2, the peak decision unit compares the maximum values ​​of the PMF spectra in the leading branch, the middle branch and the lagging branch to obtain a peak comparison result, and inputs the peak comparison result into the code length adjustment unit.

[0073] Step 4.3, when the code length adjustment unit detects that the synchronization lock signal is 0, the next code length is set to 2045. When the synchronization lock signal is 1 and the peak value of the leading branch is the largest, the next code length is set to 2048 during the observation period, and the next code length is set to 2047 during the phase shift period, so that the chip phase is fine-tuned in the leading direction; when the synchronization lock signal is 1 and the peak value of the lagging branch is the largest, the next code length is set to 2048 during the observation period, and the next code length is set to 2049 during the phase shift period, so that the chip phase is fine-tuned in the lagging direction; otherwise, the next code length is set to 2048 during both the observation period and the phase shift period, so that the chip phase remains unchanged.

[0074] Step 5: The code length output unit inputs the next code length into the parallel chip phase modulation module.

Claims

1. A low clock spread spectrum chip synchronization system based on parallel PMF-FFT, characterized in that: It includes parallel AD sampling module, parallel chip phase modulation module, parallel PMF-FFT module, and FFT peak decision module; among which: The parallel AD sampling module is used to sample the spread spectrum signal transmitted by the transmitting end of the spread spectrum system by means of interleaved sampling, obtain multi-channel parallel spread spectrum signals with different phases corresponding to the multi-phase output in the interleaved sampling, and input the multi-channel parallel spread spectrum signals into the parallel chip phase modulation module; The parallel chip phase modulation module comprises a data cache unit, a parallel phase modulation unit, a channel switching unit and a ping-pong gating unit; the data cache unit in the parallel chip phase modulation module is used to cache the parallel spread spectrum signals at the same time, and address the data in the parallel shift register from 0 to obtain the multi-channel parallel cache to be phase-modulated; the parallel phase modulation unit in the parallel chip phase modulation module comprises a starting address register, which is used to output the data corresponding to the multi-channel parallel signals in the data cache unit starting from the starting address to obtain the parallel phase modulation data of different phases, and input the parallel phase modulation data into the channel switching unit; the channel switching unit comprises two output A channel and a code tail register are used to control the parallel phase modulation data to be output alternately in two output channels to obtain parallel code chips of two channels, and at the same time, the starting address register in the parallel phase modulation unit is updated to the remainder of the sum of the value of the address register and the previous code length divided by the phase number of the parallel signal, and the parallel code chips of the two channels are input into the ping-pong gating unit; the ping-pong gating unit is used to detect the channel where the effective signal changes from 0 to 1, output the parallel code chips of the output channel, obtain the parallel code chips after phase modulation, and input the parallel code chips after phase modulation into the multi-channel parallel PMF-FFT module, and at the same time generate a frame header pulse signal and input it into the parallel PMF-FFT module; The parallel PMF-FFT module includes a parallel spread spectrum code sequence generation unit, a parallel partial matched filtering unit and a fast Fourier transform unit; the parallel spread spectrum code sequence generation unit includes three sets of parallel ROMs storing local parallel spread spectrum code sequences, which are used to read the local parallel spread spectrum code sequences from the ROMs, align the local parallel spread spectrum code sequences of the three branches with the parallel code chips after phase modulation with the position of the frame header pulse signal as the starting position, obtain the three sets of aligned local parallel spread spectrum code sequences, and input the three sets of aligned local parallel spread spectrum code sequences into the parallel partial matched filtering unit; the parallel partial matched filtering unit includes three sets of matched A matching filter is used to perform parallel correlation calculations on the three groups of aligned local parallel spread spectrum code sequences and the parallel code chips after phase modulation, add and merge the multi-channel calculation results of each group to obtain three groups of single-channel serial calculation results, divide the three groups of single-channel serial calculation results into segments at equal intervals according to the intervals of the matching filter order, sum the data of each segment, obtain the code chip PMF results of the three branches, and input the PMF results of the three branches into a fast Fourier transform unit; the fast Fourier transform unit is used to perform fast Fourier transform on the PMF results of the three branches to obtain the PMF spectrum of the three branches, and input the spectrum into an FFT peak decision module; The FFT peak decision module includes a synchronization locking unit, a peak decision unit, a code length adjustment unit and a code length output unit; the synchronization locking unit is used to judge whether the maximum value of the spectrum in the three branches exceeds a preset threshold, obtain a synchronization locking signal, and input the synchronization locking signal into the peak decision unit and the code length adjustment unit; the peak decision unit is used to retrieve the branch with the largest PMF peak among the leading branch, the middle branch and the lagging branch, obtain a peak comparison result, and input the peak comparison result into the code length adjustment unit; the code length adjustment unit includes a phase shift period and an observation period, which are used to adjust the size of the code length signal in the phase shift period and the observer according to the comparison result between the synchronization locking signal and the peak value, and input the code length signal into the parallel code chip phase modulation module, so as to realize the system's spread spectrum code chip synchronization through continuous iteration.

2. A low clock spread spectrum code chip synchronization method based on parallel PMF-FFT in the synchronization system according to claim 1, characterized in that: The receiving end of the spread spectrum system uses the parallel chip phase modulation method to adjust the phase of the multi-channel parallel digital signal, and uses the multi-channel parallel PMF-FFT method to obtain the PMF spectrum of the parallel chip after phase modulation; the specific steps of the synchronization method include the following: Step 1: The parallel AD sampling module collects multiple parallel digital signals: The parallel AD sampling module at the receiving end of the spread spectrum communication system samples the spread spectrum signal transmitted by the transmitting end of the spread spectrum system by means of interleaved sampling, obtains multi-channel parallel spread spectrum signals of different phases corresponding to the multi-phase output in the interleaved sampling, and inputs the multi-channel parallel spread spectrum signals into the parallel chip phase modulation module; Step 2: Use the parallel chip phase modulation method to adjust the phase of the multi-channel parallel spread spectrum signal: Step 2.1, a data cache unit uses a parallel shift register corresponding to the parallel spread spectrum signal to cache the parallel spread spectrum signal at the same time, and addresses the data in the parallel shift register starting from 0 to obtain a multi-channel parallel cache to be phase-modulated; Step 2.2, the parallel phase modulation unit uses the starting address register to record the starting address of the current unit, starts from the starting address in the multi-channel parallel buffer, outputs the data corresponding to the multi-channel parallel signals, obtains parallel phase modulation data of different phases, and inputs the parallel phase modulation data into the channel switching unit; Step 2.3, the current output channel of the channel switching unit outputs the parallel phase modulation data in parallel at the same time, and sets the effective signal of the channel to 1. After each output of the parallel phase modulation data, the value of the output counter is increased by the phase number corresponding to the parallel code chip. When the output counter is greater than the length of the current code chip, the effective signal of the current output channel is set to 0, and the output counter is cleared to obtain a group of parallel code chips. Step 2.4, the code tail register of the channel switching unit takes the value of the last group of parallel data in the parallel code chip, reads the value of the start address register in the parallel phase modulation unit, adds the value of the code tail register to the value of the start address register, and if the result is less than the phase number of the parallel code chip, then while the current output channel outputs the last group of data of the parallel code chip, the other output channel directly outputs the first group of data of the next parallel code chip, and sets the valid signal of the other output channel to 1, otherwise, the other output channel outputs the next parallel code chip after the current output channel outputs the code chip, and obtains the parallel code chip to be selected; Step 2.5, after the parallel code chips are output, the starting address register in the parallel phase modulation unit is updated to the remainder of the sum of the address register value and the previous code length divided by the phase number of the parallel signal; Step 2.6, when the ping-pong gating unit detects that the valid signal of any output channel changes from 0 to 1, a frame header pulse signal is generated and input into the parallel PMF-FFT module, and the parallel code chips of the output channel are output to obtain the phase-modulated parallel code chips, and are input into the multi-channel parallel PMF-FFT module; Step 3, use the multi-channel parallel PMF-FFT method to obtain the PMF spectrum of the parallel code chips after phase modulation: Step 3.1, with a number of bits less than the number of phases of the parallel signal, the local parallel spread spectrum code sequence is moved in the leading direction and the lagging direction respectively to obtain the parallel spread spectrum codes of the leading branch and the lagging branch, and the parallel spread spectrum codes of the three branches are stored in the ROM of the parallel spread spectrum code sequence generation unit; Step 3.2, the parallel spread spectrum code sequence generation unit reads the local parallel spread spectrum code sequence from the ROM, takes the position of the frame header pulse signal as the starting position, aligns the local parallel spread spectrum code sequences of the three branches with the parallel code chips after phase modulation, obtains three groups of aligned local parallel spread spectrum code sequences, and inputs the three groups of aligned local parallel spread spectrum code sequences into the parallel partial matched filtering unit; Step 3.3, the parallel partial matched filter unit performs parallel correlation calculations on the three groups of aligned local parallel spread spectrum code sequences and the parallel code chips after phase modulation, adds and merges the multi-path calculation results of each group to obtain three groups of single-path serial calculation results, divides the three groups of single-path serial calculation results into segments at equal intervals according to the interval of the matched filter order, sums the data of each segment, obtains the code chip PMF results of the three branches, and inputs the PMF results of the three branches into the fast Fourier transform unit; Step 3.4, the fast Fourier transform unit performs fast Fourier transform on the PMF results of the three branches to obtain the PMF spectrum of the three branches, and inputs the spectrum into the FFT peak decision module; Step 4: Make decision phase shifts on the PMF spectra of the three branches: Step 4.1, when the synchronization locking unit detects that the peak value of the PMF spectrum of any branch among the three branches exceeds a preset threshold, the synchronization locking signal is set to 1; Otherwise, the synchronization lock signal is set to 0, and the obtained synchronization lock signal is input into the peak value determination unit and the code length adjustment unit; Step 4.2, the peak decision unit compares the PMF peaks in the leading branch, the middle branch and the lagging branch to obtain a peak comparison result, and inputs the peak comparison result into the code length adjustment unit; Step 4.3, when the code length adjustment unit detects that the synchronization lock signal is 0, the code length is set to a number less than the length of the local spread spectrum code sequence; if the synchronization lock signal is 1 and the peak value of the leading branch is the largest, the next code length is set to the length of the local spread spectrum code sequence during the observation period, and the next code length is set to the length of the local spread spectrum code sequence minus 1 during the phase shift period; if the synchronization lock signal is 1 and the peak value of the lagging branch is the largest, the next code length is set to the length of the local spread spectrum code sequence during the observation period, and the next code length is set to the length of the local spread spectrum code sequence plus 1 during the phase shift period; otherwise, the next code length is set to the length of the local spread spectrum code sequence during both the observation period and the phase shift period; Step 5: The code length output unit inputs the next code length into the parallel chip phase modulation module.

3. The low clock spread spectrum code chip synchronization method based on parallel PMF-FFT according to claim 2 is characterized in that: The threshold in step 4.1 is a value greater than the maximum value of the PMF spectrum when the spreading code is not synchronized and less than the maximum value of the PMF spectrum when the spreading code is synchronized.

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