Method for pausing time accurately and application thereof
By configuring a configurable periodic timing pulse, the problem of accurate timing of Pause Quanta time under mixed port rates and SerDes overclocking is solved, enabling precise control of packet traffic at different rates and avoiding data overflow or loss.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU CENTEC COMM CO LTD
- Filing Date
- 2021-12-24
- Publication Date
- 2026-06-02
AI Technical Summary
With mixed port rates and overclocked SERDEs, existing technologies cannot accurately calculate the Pause Quanta time, resulting in an inability to precisely control packet traffic.
By configuring the actual timing pulse period of the preset timing pulse, the pause time of the port sender's message is calculated based on the Pause Quanta in the Pause frame, and the time is decremented on the pause time counter. Different timing pulse periods are selected according to the port rate range to ensure accurate timing at different rates.
It achieves precise calculation of Pause Quanta time under Serdes overclocking, enabling accurate control of packet traffic and preventing port data overflow or loss.
Smart Images
Figure CN116346732B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communications, and in particular to a method and application for accurately timing the pause time of a Pause frame. Background Technology
[0002] In IEEE 802.3, a type of MAC frame called the Pause frame is defined. This frame is a control frame used to control the data stream to stop sending. It is generated on the MAC sending side and parsed and responded to on the MAC receiving side. When the received packet traffic exceeds the maximum traffic that the local device can handle, it will trigger the local device to send a Pause frame to the port device in the sending direction, causing the port device to stop sending packets to the local device for a period of time. The duration of the stop sending is also defined in detail in the Pause frame.
[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of this invention is to provide a method and application for accurately timing the pause frame time, which solves the problem that the corresponding accurate pause time cannot be calculated separately under mixed port rates and SERDE overclocking, thus making it impossible to accurately control packet traffic.
[0005] To achieve the above objectives, embodiments of the present invention provide a method for accurately timing the pause time of a Pause frame.
[0006] In one or more embodiments of the present invention, the method includes: calculating the pause time of packet transmission at the port transmitter based on PauseQuanta in the Pause frame; and configuring the actual timing pulse period of a preset timing pulse based on the current rate of the port to time the pause time.
[0007] In one or more embodiments of the present invention, configuring the actual timing pulse period of the preset timing pulse according to the current rate of the port to time the pause time specifically includes: decrementing the pause time counter according to the period of the preset timing pulse; configuring the actual timing pulse period T of the preset timing pulse according to the current rate speed of the port when the rate of the port changes; and decrementing the remaining value of the pause time counter based on the actual timing pulse period.
[0008] In one or more embodiments of the present invention, the method further includes: determining a preset timing pulse for the port based on the rate range of the port.
[0009] In one or more embodiments of the present invention, a preset timing pulse for the port is determined according to the port's rate range, specifically including: when the port operates at 1Gbps to 25Gbps, a timing pulse with a pulse period of 1024ns is determined; and / or, when the port operates at 40Gbps to 100Gbps, a timing pulse with a pulse period of 256ns is determined; and / or, when the port operates at 200Gbps to 400Gbps, a timing pulse with a pulse period of 128ns is determined; and / or, when the port operates at 800Gbps to 1600Gbps, a timing pulse with a pulse period of 64ns is determined.
[0010] In one or more embodiments of the present invention, the step of calculating the pause time of port sender message transmission based on the Pause Quanta in the Pause frame specifically includes: the time unit of the Pause Quanta is the time required to transmit 512 bits at the port rate, and the pause time of port sender message transmission is the product of the Pause Quanta and the time unit of the Pause Quanta.
[0011] In one or more embodiments of the present invention, the step of decrementing the pause time counter specifically includes: the initial value of the pause time counter is the Pause Quanta, and the value of the pause time counter being decremented is speed*T / 512.
[0012] In one or more embodiments of the present invention, the method further includes: when the pause time counter decreases to 0 and no new Pause frame is received, ending the port transmitter from sending messages; or when the pause time counter does not decrease to 0 and a new Pause frame is received, re-timing according to the Pause Quanta of the new Pause frame.
[0013] In another aspect of the invention, an apparatus for accurately timing the pause time of a Pause frame is provided, comprising a calculation module and a timing module.
[0014] The calculation module is used to calculate the pause time of the port sender message based on the Pause Quanta in the Pause frame.
[0015] The timing module is used to configure the actual timing pulse period of the preset timing pulse according to the current rate of the port, so as to time the pause time.
[0016] In one or more embodiments of the present invention, the timing module is further configured to: decrement the pause time counter according to the period of a preset timing pulse; configure the actual timing pulse period T of the preset timing pulse according to the current speed of the port when the port speed changes; and decrement the remaining value of the pause time counter based on the actual timing pulse period.
[0017] In one or more embodiments of the present invention, the timing module is further configured to: determine a preset timing pulse for the port based on the rate range of the port.
[0018] In one or more embodiments of the present invention, the timing module is further configured to: determine a timing pulse with a pulse period of 1024 ns when the port operates at 1 Gbps to 25 Gbps; and / or, determine a timing pulse with a pulse period of 256 ns when the port operates at 40 Gbps to 100 Gbps; and / or, determine a timing pulse with a pulse period of 128 ns when the port operates at 200 Gbps to 400 Gbps; and / or, determine a timing pulse with a pulse period of 64 ns when the port operates at 800 Gbps to 1600 Gbps.
[0019] In one or more embodiments of the present invention, the timing module is further configured to: terminate the port transmitter from sending messages when the pause time counter decreases to 0 and no new Pause frame is received; or restart the timing based on the Pause Quanta of the new Pause frame when the pause time counter has not decreased to 0 and a new Pause frame is received.
[0020] In another aspect of the invention, an electronic device is provided, comprising: at least one processor; and a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform the method for precisely timing the pause time of a Pause frame as described above.
[0021] In another aspect of the invention, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the method for precisely timing the pause time of a Pause frame as described above.
[0022] Compared with existing technologies, the method and application for precise timing of Pause frame pause time according to embodiments of the present invention can achieve accurate timing of Pause Quanta through timing pulses with independently configurable periods. The configurability of the timing pulse period also enables precise calculation of Pause Quanta time under SerDes overclocking. Even in mixed port rate and SerDes overclocking scenarios, the duration of paused message transmission can be accurately timed based on Pause Quanta, thereby achieving precise control of message traffic. Attached Figure Description
[0023] Figure 1 This is a flowchart of a method for accurately timing the pause time of a Pause frame according to an embodiment of the present invention;
[0024] Figure 2 This is a Pause frame structure diagram of a method for accurately timing the pause time of a Pause frame according to an embodiment of the present invention;
[0025] Figure 3 This is a detailed flowchart of a method for accurately timing the pause time of a Pause frame according to an embodiment of the present invention;
[0026] Figure 4 This is a structural diagram of a device for accurately timing the pause time of a Pause frame according to an embodiment of the present invention;
[0027] Figure 5 This is a hardware structure diagram of a computing device for accurately timing the pause time of a Pause frame according to an embodiment of the present invention. Detailed Implementation
[0028] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.
[0029] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.
[0030] The technical solutions provided by the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0031] Example 1
[0032] like Figures 1 to 2 As shown, an embodiment of the present invention describes a method for accurately timing the pause time of a Pause frame, the method comprising the following steps.
[0033] In step S101, the pause time for the port sender to transmit messages is calculated based on the Pause Quanta in the Pause frame.
[0034] A Pause frame, described in the IEEE 802.3 protocol, is a message used to control MAC data traffic. When the port's data volume is too large to process in a timely manner, it sends a Pause frame to the upstream MAC, instructing the upstream MAC to stop sending data for a period of time. The stop time is recorded in the Pause Quanta field of the message. When the upstream MAC receives a valid Pause frame from the port, it starts timing and stops sending data to prevent the port from being unable to process data in time, which could lead to FIFO overflow or data loss. If the timer expires and no new Pause frame is received, the port will retransmit data. If the timer has not expired and the Pause Quanta field of a newly received Pause frame is all 0s, it indicates that data can be retransmitted, and the timer stops, and the port resumes sending data.
[0035] The specific frame structure of the Pause frame is as follows: Figure 2 As shown, the MAC address structure includes 6 bytes of DA (Destination MAC Address), 6 bytes of SA (Source MAC Address), 2 bytes of EtherType, 2 bytes of Opcode, 2 bytes of Pause Quanta (MAC Stop Transmission Time), 42 bytes of PAD (Padding Field), and 4 bytes of FCS (Frame Checksum, usually CRC). The 2-byte Pause Quanta defines the time it takes for the MAC to stop transmitting. The unit of Pause Quanta is 512 bits of time, which varies depending on the port speed (Gbps). Specifically, Pause Quanta represents the time required to transmit 512 bits at a given port speed. For example, at a 10Gbps port speed, the 512-bit time is 51.2ns; at a 100Gbps port speed, the 512-bit time is 5.12ns.
[0036] When the Pause Quanta field of the Pause frame is parsed in the receiving direction of the port, it indicates that the sending end needs to stop sending messages for a duration of Pause Quanta * 512 bits. Taking a port rate of 100Gbps as an example, the corresponding Pause Quanta time unit is 5.12ns. Therefore, when the port rate is 100Gbps, the duration for the MAC to stop sending messages is Pause Quanta * 5.12ns.
[0037] In step S102, the actual timing pulse period of the preset timing pulse is configured according to the current rate of the port to time the pause time.
[0038] Configure the timing pulse period T (ns), and assign the Pause Quanta to the pause time counter as its initial value upon receiving a Pause frame. With each timing pulse, the pause time counter decreases by speed*(T / 512). When the pause time counter reaches 0, the Pause Quanta timer has ended. If no new Pause frame is received within the Pause Quanta timer, message transmission stops, and the system waits for Pause Quanta*512 bits before resuming message transmission. If a new Pause frame is received before the Pause Quanta timer expires, the timing restarts based on the new Pause Quanta.
[0039] Taking a port rate of 100Gbps and a timing pulse period of 256ns as an example, if the port rate is increased to 105Gbps after overclocking the SerDes, the 512-bit time will be 512 / 105 = 4.876ns. Maintaining the 50-second pause timer decrement by 50 for each timing pulse, the timing pulse period can be configured to 243.8ns (256ns / 1.05).
[0040] Example 2
[0041] like Figure 3 As shown, an embodiment of the present invention describes a method for accurately timing the pause time of a Pause frame, the method comprising the following steps.
[0042] In step S201, the pause time for the port sender to transmit messages is calculated based on the Pause Quanta in the Pause frame.
[0043] Pause Quanta defines the time it takes for a MAC address to stop sending packets. The unit of Pause Quanta is 512-bit time, which varies depending on the port speed. Specifically, Pause Quanta represents the time required to send 512 bits at a given port speed. For example, at a 10Gbps port speed, the 512-bit time is 51.2ns; at a 100Gbps port speed, the 512-bit time is 5.12ns.
[0044] When the Pause Quanta field of the Pause frame is parsed in the receiving direction of the port, it indicates that the sending end needs to stop sending messages for a duration of Pause Quanta * 512 bits. Taking a port rate of 100Gbps as an example, the corresponding Pause Quanta time unit is 5.12ns. Therefore, when the port rate is 100Gbps, the MAC stops sending messages for a duration of Pause Quanta * 5.12ns.
[0045] In step S202, the preset timing pulse of the port is determined according to the port's rate range.
[0046] Configure the timing pulse period T, and when a Pause frame is received, assign the Pause Quanta to the pause time counter as the initial value of the pause time counter.
[0047] In this embodiment, the timing pulse period can be configured to 1024ns, 256ns, 128ns, and 64ns, corresponding to port rates of 1Gbps to 25Gbps, 40Gbps to 100Gbps, 200Gbps to 400Gbps, and 800Gbps to 1600Gbps, respectively.
[0048] Each port can independently select any one of the above four timing pulse periods as the timing pulse period for calculating the Pause Quanta time, which can meet the requirements for accurate calculation of Pause Quanta time under different mixed port rates.
[0049] In step S203, the pause time counter is decremented according to the preset timing pulse period.
[0050] When the port operates at 1Gbps to 25Gbps, a timing pulse with a period of 1024ns is selected. At each rate, the amount by which the pause time counter decreases with each timing pulse is shown below:
[0051] At 1Gbps, the pause time counter decreases by 2 for each timing pulse.
[0052] At 5Gbps, the pause time counter decreases by 10 with each timing pulse.
[0053] At 10Gbps, the pause time counter decreases by 20 for each timing pulse.
[0054] At 25Gbps, the pause time counter decreases by 50 with each timing pulse.
[0055] When the port operates between 40Gbps and 100Gbps, a timing pulse with a period of 256ns is selected. At each data rate, the pause time counter decreases by the following amount with each timing pulse:
[0056] At 40Gbps, the pause time counter decreases by 20 for each timing pulse.
[0057] At 50Gbps, the pause time counter decreases by 25 for each timing pulse.
[0058] At 100Gbps, the pause time counter decreases by 50 with each timing pulse.
[0059] When the port operates at 200Gbps to 400Gbps, a timing pulse with a period of 128ns is selected. At each data rate, the amount by which the pause time counter decreases with each timing pulse is shown below:
[0060] At 200Gbps, the pause time counter decreases by 50 for each timing pulse.
[0061] At 400Gbps, the pause time counter decreases by 100 with each timing pulse.
[0062] When the port operates at 800Gbps to 1600Gbps, a timing pulse with a period of 64ns is selected. At each data rate, the pause time counter decreases by the following amount with each timing pulse:
[0063] At 800Gbps, the pause time counter decreases by 100 with each timing pulse.
[0064] At 1600Gbps, the pause time counter decreases by 200 for each timing pulse.
[0065] like Figure 4 As shown, an apparatus for accurately timing the pause time of a Pause frame according to a specific embodiment of the present invention is described.
[0066] In an embodiment of the present invention, the device for accurately timing the pause time of the Pause frame includes a calculation module 401 and a timing module 402.
[0067] The calculation module 401 is used to calculate the pause time of the port sender message based on the Pause Quanta in the Pause frame.
[0068] The timing module 402 is used to configure the actual timing pulse period of the preset timing pulse according to the current rate of the port, so as to time the pause time.
[0069] The timing module 402 is also used to: decrement the pause time counter according to the period of the preset timing pulse; configure the actual timing pulse period T of the preset timing pulse according to the current speed of the port when the port speed changes; and decrement the remaining value of the pause time counter based on the actual timing pulse period.
[0070] The timing module 402 is also used to: determine the preset timing pulse of the port according to the port's rate range.
[0071] The timing module 402 is also used to: determine a timing pulse with a pulse period of 1024ns when the port operates at 1Gbps to 25Gbps; and / or, determine a timing pulse with a pulse period of 256ns when the port operates at 40Gbps to 100Gbps; and / or, determine a timing pulse with a pulse period of 128ns when the port operates at 200Gbps to 400Gbps; and / or, determine a timing pulse with a pulse period of 64ns when the port operates at 800Gbps to 1600Gbps.
[0072] The timing module 402 is also used to: stop sending messages at the end port when the pause time counter decreases to 0 and no new Pause frame is received; or restart the timing based on the Pause Quanta of the new Pause frame when the pause time counter has not decreased to 0 and a new Pause frame is received.
[0073] Figure 5 A hardware structure diagram of a computing device 50 for precise timing of pause frame pause times, according to an embodiment of this specification, is shown. Figure 5 As shown, the computing device 50 may include at least one processor 501, a memory 502 (e.g., non-volatile memory), a main memory 503, and a communication interface 504, and the at least one processor 501, memory 502, main memory 503, and communication interface 504 are connected together via a bus 505. The at least one processor 501 executes at least one computer-readable instruction stored or encoded in the memory 502.
[0074] It should be understood that the computer-executable instructions stored in memory 502, when executed, cause at least one processor 501 to perform the above-described combinations in the various embodiments of this specification. Figure 1-5 The description includes various operations and functions.
[0075] In the embodiments of this specification, computing device 50 may include, but is not limited to: personal computer, server computer, workstation, desktop computer, laptop computer, notebook computer, mobile computing device, smartphone, tablet computer, cellular phone, personal digital assistant (PDA), handheld device, messaging device, wearable computing device, consumer electronic device, etc.
[0076] According to one embodiment, a program product, such as a machine-readable medium, is provided. The machine-readable medium may have instructions (i.e., the elements implemented in software as described above), which, when executed by a machine, cause the machine to perform the above-described combinations of the various embodiments of this specification. Figure 1-5 The various operations and functions described. Specifically, a system or apparatus equipped with a readable storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer or processor of the system or apparatus to read and execute the instructions stored in the readable storage medium.
[0077] The method and application for precise timing of Pause frame pause time according to embodiments of the present invention can achieve accurate timing of Pause Quanta through timing pulses with independently configurable periods. The configurability of the timing pulse period also enables precise calculation of Pause Quanta time under SerDes overclocking. Even in mixed port rate and SerDes overclocking scenarios, the duration of paused message transmission can be accurately timed based on Pause Quanta, thereby achieving precise control of message traffic.
[0078] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0079] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0080] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0081] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0082] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.
Claims
1. A method for accurately timing the pause time of a Pause frame, characterized in that, The method includes: The pause time at the port transmitter is calculated based on the Pause Quanta in the Pause frame, where the pause time is the time during which message transmission is stopped; and Configure the actual timing pulse period of the preset timing pulse according to the current rate of the port to time the pause time, specifically including: Determine the preset timing pulse for the port based on the port's rate range; The pause time counter is decremented according to the preset timing pulse period; When the speed of the port changes, the actual timing pulse period T of the preset timing pulse is configured according to the current speed of the port. Based on the actual timing pulse period, the remaining value of the pause time counter is decremented. The initial value of the pause time counter is the Pause Quanta, and the decrement of the pause time counter is speed*T / 512.
2. The method for accurately timing the pause time of a Pause frame as described in claim 1, characterized in that, Based on the rate range of the port, a preset timing pulse for the port is determined, specifically including: When the port operates at 1Gbps~25Gbps, a timing pulse with a period of 1024ns is determined; and / or, When the port operates at 40Gbps~100Gbps, a timing pulse with a pulse period of 256ns is determined; and / or, When the port operates at 200Gbps~400Gbps, a timing pulse with a pulse period of 128ns is determined; and / or, When the port operates at 800Gbps~1600Gbps, a timing pulse with a pulse period of 64ns is determined.
3. The method for accurately timing the pause time of a Pause frame as described in claim 1, characterized in that, The calculation of the pause time for the port sender to transmit messages based on the Pause Quanta in the Pause frame specifically includes: The Pause Quanta time unit is the time required to send 512 bits at the port rate, and the pause time for the port sender to transmit a message is the product of the Pause Quanta and the Pause Quanta time unit.
4. The method for accurately timing the pause time of a Pause frame as described in claim 1, characterized in that, The method further includes: When the pause time counter decreases to 0 and no new Pause frame is received, the port transmitter stops sending messages; or If the pause time counter has not decreased to 0 and a new Pause frame is received, the timer is restarted based on the Pause Quanta of the new Pause frame.
5. A device for accurately timing the pause time of a pause frame, characterized in that, The device includes: The calculation module is used to calculate the pause time of the port transmitter based on the Pause Quanta in the Pause frame, wherein the pause time is the time during which message transmission is stopped; and A timing module, configured to set the actual timing pulse period of a preset timing pulse based on the current rate of the port, for timing the pause time, specifically includes: Determine the preset timing pulse for the port based on the port's rate range; The pause time counter is decremented according to the preset timing pulse period; When the speed of the port changes, the actual timing pulse period T of the preset timing pulse is configured according to the current speed of the port. Based on the actual timing pulse period, the remaining value of the pause time counter is decremented. The initial value of the pause time counter is the Pause Quanta, and the decrement of the pause time counter is speed*T / 512.
6. An electronic device, characterized in that, include: At least one processor; as well as A memory that stores instructions that, when executed by the at least one processor, cause the at least one processor to perform a method for precisely timing the pause time of a Pause frame as described in any one of claims 1 to 4.
7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for accurately timing the pause time of a Pause frame as described in any one of claims 1 to 4.