Sensing assembly with common node

Abstract

This application is directed to sensing components with a common node. A set of sensing circuits of a memory device can include a shared differential amplifier with a first branch for each sensing circuit and a shared second branch, and a shared common node. A respective latch of each sense amplifier can be initialized to a second logic state, and the common node can undergo a voltage ramp to determine a state stored in a memory cell. If the memory cell stores a first logic state, the sense amplifier can be coupled with the common node to sink current and switch the state of the latch to the first logic state. Alternatively, if the memory cell stores the second logic state, no current can be sunk and the state of the latch can not switch.

Description

[0001] CROSS-REFERENCE

[0002] The present patent application claims priority to U.S. Patent Application No. 17 / 646,261, filed December 28, 2021, entitled “SENSING COMPONENT WITH A COMMON NODE,” by DI VINCENZO et al., assigned to the present assignee and expressly incorporated herein by reference. TECHNICAL FIELD

[0003] TECHNICAL FIELD BACKGROUND

[0004] Memory devices are widely used in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device into various states. For example, binary memory cells can be programmed into one of two supported states, often represented by a logic 1 or a logic 0. In some examples, individual memory cells can support more than two states, any of which can be stored. To access stored information, a component of a device can read or sense at least one stored state in a memory device. To store information, a component of a device can write or program a state in a memory device.

[0005] There are a variety of types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and the like. Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain their stored logic state for a long period of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. FeRAM can be able to achieve densities similar to volatile memory, but can have non-volatile characteristics because ferroelectric capacitors are used as storage devices. SUMMARY

[0006] An apparatus is described. The apparatus can include a memory cell; a sense amplifier coupled with the memory cell via a digit line, the sense amplifier comprising: a latch; a first transistor having a gate coupled with the digit line, wherein a first state of the latch couples the first transistor with a first node and a second state of the latch decouples the first transistor from the first node; a second transistor having a gate coupled with a first bias voltage, a terminal of the second transistor coupled with a terminal of the first transistor, wherein the second transistor is configured to provide a first current; and a third transistor having a first terminal coupled with the first node, wherein the third transistor is configured to sink a second current from the first node; and a fourth transistor coupled with the sense amplifier and configured to provide a voltage ramp on the first node, wherein the first transistor is configured to switch the latch from the first state to the second state based at least in part on a voltage difference between the digit line and the first node satisfying a threshold.

[0007] An apparatus is described. The apparatus can include a plurality of memory cells; a plurality of sense amplifiers respectively coupled with the plurality of memory cells via a plurality of digit lines, wherein each sense amplifier of the plurality of sense amplifiers comprises: a latch; a first branch of a plurality of first branches of a differential amplifier, the first branch comprising a first transistor having a gate coupled with a digit line of the plurality of digit lines and a second transistor having a gate coupled with a first bias voltage, wherein the second transistor is configured to supply a first current to a terminal of the first transistor, and wherein a first state of the latch couples the first transistor with a first node and a second state of the latch decouples the first transistor from the first node; and a third transistor having a gate coupled with a second bias voltage and a terminal coupled with the first node, wherein the third transistor is configured to sink a second current from the first node; and a second branch of the differential amplifier comprising a fourth transistor having a gate coupled with the first bias voltage and a fifth transistor having a gate coupled with a reference voltage and a terminal coupled with the first node of the plurality of sense amplifiers, wherein for each sense amplifier, the first transistor is configured to switch the latch from the first state to the second state based at least in part on a voltage ramp on the first node causing a voltage difference between the digit line associated with the each sense amplifier and the first node to satisfy a threshold.

[0008] A method is described. The method can include coupling a first transistor with a first node of a sense amplifier based at least in part on activating a second transistor coupled with a latch of the sense amplifier, wherein activating the second transistor is based at least in part on a first state of the latch; supplying a first current to the first transistor based at least in part on activating a third transistor, wherein the third transistor is coupled with a first bias voltage and the first transistor; sinking a second current from the first node based at least in part on activating a fourth transistor, wherein a voltage ramp of the first node is based at least in part on the second current; and activating the first transistor based at least in part on a voltage difference between the first node and a digit line satisfying a threshold, the voltage difference based at least in part on the voltage ramp, wherein the first transistor causes the latch to switch from the first state to a second state based at least in part on the voltage difference between the first node and the digit line satisfying the threshold. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 An example of a system supporting sensing components with a common node is shown in accordance with the examples disclosed herein.

[0010] FIG. 2 An example of a memory die supporting sensing components with a common node is shown in accordance with the examples disclosed herein.

[0011] FIG. 3 An example of a sensing circuit supporting sensing components with a common node is shown in accordance with the examples disclosed herein.

[0012] FIG. 4 An example of a timing diagram supporting sensing components with a common node is shown in accordance with the examples disclosed herein.

[0013] FIG. 5 A block diagram of a memory device supporting sensing components with a common node is shown in accordance with the examples disclosed herein.

[0014] FIG. 6 A flow diagram showing one or more methods supporting sensing components with a common node is shown in accordance with the examples disclosed herein. DETAILED DESCRIPTION

[0015] Memory devices (e.g., FeRAM devices or NAND devices) can perform a sense operation to determine a set of logic states (e.g., a codeword) stored in a corresponding set of memory cells. For example, a sense operation can use a set of sense amplifiers coupled with a set of memory cells to determine each bit (e.g., a logic “1” or a logic “0”) of a codeword. In some cases, if a sense amplifier detects a logic state, the sense amplifier can sink current (e.g., a tail current) to store the first state in a temporary register, such as a latch. Thus, each sense amplifier can include a respective branch or circuitry to provide current to sense a logic state. However, if a codeword includes a large number of bits of a second logic state, the current provided to the sense amplifiers to detect the second logic state can be unused or can inefficiently increase current consumption, which can increase system latency and power consumption. Thus, methods to improve the efficiency of a sense operation can be desired.

[0016] As disclosed herein, a set of sense circuits of a memory device can share a portion of a differential amplifier to increase the reliability and efficiency of an access operation of a memory cell storing a first logic state (e.g., a logic “1”) or a second logic state (e.g., a logic “0”). For example, each sense circuit can include a respective first branch of a shared differential amplifier, and can share a common second branch of the shared differential amplifier. In some cases, the set of sense circuits can also include a shared common node that can be selectively coupled with the respective first branch of each sense circuit. Additionally, each sense circuit can include a transistor coupled with the common node to sink current (e.g., a tail current) as part of detecting the first logic state. For example, as part of an access operation, a respective latch of each sense circuit can be initialized to the second logic state, and the common node can undergo a voltage ramp to determine a state stored in a memory cell using a voltage of a digit line coupled with the memory cell and the sense circuit. If the memory cell stores the first logic state and the voltage of the common node drops below a threshold of a transistor positioned between the first branch and the common node, the first branch of the sense circuit can electrically couple with the common node and allow current to flow to the first branch, which can activate a gate of a set transistor for the latch. Thus, the set transistor can switch a state of the latch to the first logic state. Alternatively, if the memory cell stores the second logic state, the voltage of the common node can not drop below the voltage of the digit line, which can fail to activate the set transistor and the state of the latch can not switch. Thus, the second branch of the shared differential amplifier among the set of sense circuits can reduce current consumption and thus improve the efficiency of a sense operation.

[0017] The features of the present disclosure are first described in the context of a system and die as described with reference to FIG. 1 and 2 The features of the present disclosure are first described in the context of a system and die as described with reference toFIGS. 3-4 Features of the disclosure are described in the context of the described sensing circuit and timing diagrams. Further features are illustrated and described by the described device diagrams and flow diagrams of sensing components with common nodes. FIGS. 5-6 Features of the disclosure are described in the context of the described sensing circuit and timing diagrams. Further features are illustrated and described by the described device diagrams and flow diagrams of sensing components with common nodes.

[0018] FIG. 1 An example of a system 100 supporting sensing components with common nodes is shown in accordance with examples disclosed herein. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 can include one or more memory devices 110, but aspects of the one or more memory devices 110 can be described in the context of a single memory device (e.g., the memory device 110).

[0019] The system 100 can include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 can illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, etc. The memory device 110 can be a component of a system that can be used to store data for one or more other components of the system 100.

[0020] At least portions of the system 100 can be an example of the host device 105. The host device 105 can be an example of a processor or other circuitry within a device that uses memory to perform processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, the host device 105 can refer to hardware, firmware, software, or a combination thereof that implements the functionality of the external memory controller 120. In some examples, the external memory controller 120 can be referred to as a host or host device 105.

[0021] Memory device 110 can be a standalone device or component that is operable to provide physical memory addresses / space that can be used or referenced by system 100. In some examples, memory device 110 can be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 can be operable to support one or more of modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0022] Memory device 110 can be used to store data for components of host device 105. In some examples, memory device 110 can act as a slave or dependent device (e.g., responsive and performing commands provided by host device 105 through external memory controller 120) of host device 105. Such commands can include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0023] Host device 105 can include one or more of external memory controller 120, processor 125, basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. Components of host device 105 can be coupled with each other using bus 135.

[0024] Processor 125 can be operable to provide control or other functionality for at least portions of system 100 or at least portions of host device 105. Processor 125 can be a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, external memory controller 120 can be implemented by processor 125 or be a part of the processor.

[0025] BIOS component 130 can be a software component that includes a BIOS operated as firmware that can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 can also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 can include a program or software stored in one or more of read-only memory (ROM), flash memory, or other nonvolatile storage.

[0026] Memory device 110 can include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160a, memory die 160b, memory die 160N) can include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 can be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more sections) where each memory cell can be used to store at least one bit of data. A memory device 110 that includes two or more memory dies 160 can be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

[0027] Device memory controller 155 can include circuitry, logic, or components that can be used to control operations of memory device 110. Device memory controller 155 can include hardware, firmware, or instructions that enable memory device 110 to perform various operations, and can be used to receive, transmit, or execute commands, data, or control information related to components of memory device 110. Device memory controller 155 can be used to communicate with one or more of external memory controller 120, the one or more memory dies 160, or processor 125. In some examples, device memory controller 155 can control operations of memory device 110 described herein in conjunction with local memory controllers 165 of memory dies 160.

[0028] In some examples, memory device 110 can receive data or commands, or both, from host device 105. For example, memory device 110 can receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory dies 160 to host device 105.

[0029] The local memory controller 165 (e.g., local to the memory die 160) can include circuitry, logic, or components operable to control operations of the memory die 160. In some examples, the local memory controller 165 can be used to communicate (e.g., receive or transmit data or commands, or both) with the device memory controller 155. In some examples, the memory device 110 can not include the device memory controller 155, and the local memory controller 165 or the external memory controller 120 can perform various functions described herein. As such, the local memory controller 165 can be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that can be included in the device memory controller 155 or the local memory controller 165, or both, can include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support operations of the described device memory controller 155 or local memory controller 165, or both.

[0030] The external memory controller 120 can be used to enable the transfer of one or more of information, data, or commands between components of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 can translate or interpret communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105 or functions described herein can be implemented by the processor 125. For example, the external memory controller 120 can be hardware, firmware, or software or some combination thereof implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or functions described herein can be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0031] The components of the host device 105 can exchange information with the memory device 110 using one or more channels 115. The channels 115 can be operable to support communications between the external memory controller 120 and the memory device 110. Each channel 115 can be an example of a transmission medium that carries information between the host device 105 and a memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of the system 100. A signal path can be an example of an electrically conductive path operable to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin can be an example of an electrically conductive input or output point of a device of the system 100, and a pin can be operable to serve as part of a channel.

[0032] The channels 115 (and associated signal paths and terminals) can be dedicated to communicating one or more types of information. For example, the channels 115 can include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling can be communicated on the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., a signal level) of a signal can be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0033] In some cases, a set of sense amplifiers of memory array 170 can include respective first branches of a shared differential amplifier, and can share a common second branch of the shared differential amplifier. In some cases, the set of sense circuits can also include a shared common node that can be selectively coupled with a respective first branch of each sense circuit. Additionally, each sense circuit can include a transistor coupled with the common node to sink current (e.g., tail current) as part of detecting a first logic state. For example, as part of an access operation, a respective latch of each sense circuit can be initialized to a second logic state, and the common node can undergo a voltage ramp to determine a state stored in a memory cell using a voltage of a digit line coupled with the memory cell and the sense circuit. If the memory cell stores the first logic state and the voltage of the common node falls below a threshold of a transistor positioned between the first branch and the common node, the first branch of the sense circuit can electrically couple with the common node and allow current to flow to the first branch, which can activate a gate of a set transistor for the latch. Thus, the set transistor can switch a state of the latch to the first logic state. Alternatively, if the memory cell stores the second logic state, the voltage of the common node can not fall below the voltage of the digit line, which can fail to activate the set transistor and the state of the latch can not switch. Thus, the second branch of the differential amplifier shared among the set of sense circuits can reduce current consumption and thus improve efficiency of a sensing operation.

[0034] FIG. 2 An example of a memory die 200 that supports a sense component with a common node is shown in accordance with examples disclosed herein. Memory die 200 can be an example of the memory die 160 described with reference to FIG. 1 In some examples, memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory apparatus. Memory die 200 can include one or more memory cells 205, which can each be programmable to store a different logic state (e.g., programmed to one of a set of two or more possible states). For example, memory cells 205 can be operable to store one bit of information (e.g., a logic 0 or a logic 1) at a time. In some examples, memory cells 205 (e.g., multi-level memory cells) can be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some examples, memory cells 205 can be arranged in an array, such as the memory array 170 described with reference to FIG. 1

[0035] ​The memory cells 205 can store a state (e.g., a polarization state or a dielectric charge) that represents a programmable state in a capacitor. In a FeRAM architecture, the memory cells 205 can include a capacitor 240 that includes a ferroelectric material to store a charge and / or a polarization that represents a programmable state. The memory cells 205 can include a logic storage component, such as the capacitor 240, and a switching component 245. The capacitor 240 can be an example of a ferroelectric capacitor. A first node of the capacitor 240 can be coupled with the switching component 245, and a second node of the capacitor 240 can be coupled with the plate line 220. The switching component 245 can be an example of a transistor or any other type of switching device that selectively establishes or cancels electronic communication between two components.

[0036] The memory die 200 can include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a pattern, such as a grid-like pattern. The access lines can be conductive lines that are coupled with the memory cells 205 and can be used to perform access operations on the memory cells 205. In some examples, the word lines 210 can be referred to as row lines. In some examples, the digit lines 215 can be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or the like, can be interchangeable without loss of understanding or operation. The memory cells 205 can be positioned at intersections of the word lines 210, the digit lines 215, and / or the plate lines 220.

[0037] Operations, such as reads and writes, can be performed on the memory cells 205 by activating or selecting access lines, such as the word lines 210, the digit lines 215, and / or the plate lines 220. A single memory cell 205 can be accessed at an intersection thereof by biasing (e.g., applying a voltage to) the word lines 210, the digit lines 215, or the plate lines 220. Activating or selecting the word lines 210, the digit lines 215, or the plate lines 220 can include applying a voltage to the respective lines.

[0038] Access to the memory cells 205 can be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 can receive a row address from a local memory controller 265 and activate the word lines 210 based on the received row address. The column decoder 230 receives a column address from the local memory controller 265 and activates the digit lines 215 based on the received column address. The plate driver 235 can receive a plate address from the local memory controller 265 and activate the plate lines 220 based on the received plate address.

[0039] Selecting or deselecting the memory cell 205 can be accomplished by activating or deactivating the switching component 245. The capacitor 240 can be in electronic communication with the digit line 215 using the switching component 245. For example, the capacitor 240 can be isolated from the digit line 215 when the switching component 245 is deactivated, and the capacitor 240 can be coupled with the digit line 215 when the switching component 245 is activated.

[0040] The word line 210 can be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 can be in electronic communication with a gate of the switching component 245 of the memory cell 205, and can be operable to control the switching component 245 of the memory cell. In some architectures, the word line 210 can be in electronic communication with a node of the capacitor of the memory cell 205, and the memory cell 205 can not include a switching component.

[0041] The digit line 215 can be a conductive line connecting the memory cell 205 with the sensing component 250. In some architectures, the memory cell 205 can be selectively coupled with the digit line 215 during portions of an access operation. For example, the word line 210 and the switching component 245 of the memory cell 205 can be used to selectively couple and / or isolate the capacitor 240 of the memory cell 205 with the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0042] The plate line 220 can be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. The plate line 220 can be in electronic communication with a node (e.g., cell bottom) of the capacitor 240. The plate line 220 can cooperate with the digit line 215 to bias the capacitor 240 during an access operation of the memory cell 205.

[0043] The sensing component 250 can determine a state (e.g., polarization state or charge) stored on the capacitor 240 of the memory cell 205 and determine a logic state of the memory cell 205 based on the detected state. The sensing component 250 can include one or more sense amplifiers to amplify a signal output of the memory cell 205. The sensing component 250 can compare a signal received from the memory cell 205 across the digit line 215 to a reference signal 255 (e.g., reference voltage). The detected logic state of the memory cell 205 can be provided as an output of the sensing component 250 (e.g., to the input / output 260) and can be indicated to another component of the memory device 110 including the memory die 200.

[0044] The local memory controller 265 can control the operation of the memory cells 205 through various components, such as the row decoder 225, the column decoder 230, the plate drivers 235, and the sensing components 250. The local memory controller 265 can be a reference FIG. 1 The described example of the local memory controller 165. In some examples, one or more of the row decoder 225, the column decoder 230, and the plate drivers 235 and sensing components 250 can be co-located with the local memory controller 265. The local memory controller 265 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., the external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 265 can generate row signals and column address signals to activate a target word line 210, a target digit line 215, and a target plate line 220. The local memory controller 265 can also generate and control various voltages or currents used during the operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein can vary and can be different for the various operations discussed in operating the memory die 200.

[0045] The local memory controller 265 can be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations can include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, the access operations can be performed or otherwise coordinated by the local memory controller 265 in response to various access commands (e.g., from the host device 105). The local memory controller 265 can be operable to perform other access operations not listed here or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0046] The local memory controller 265 can be used to perform read operations (e.g., sense operations) on one or more memory cells 205 of the memory die 200. During a read operation, a logical state stored in a memory cell 205 of the memory die 200 can be determined. The local memory controller 265 can identify a target memory cell 205 on which the read operation is to be performed. The local memory controller 265 can identify a target word line 210, a target digit line 215, and a target plate line 220 coupled with the target memory cell 205. The local memory controller 265 can activate the target word line 210, the target digit line 215, and the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 can transfer a signal to the sense component 250 in response to biasing the access lines. The sense component 250 can amplify the signal. The local memory controller 265 can activate the sense component 250 (e.g., latch sense component) and in turn compare the signal received from the memory cell 205 to the reference 255. Based on the comparison, the sense component 250 can determine the logical state stored on the memory cell 205.

[0047] In some cases, the sense component 250 can include a set of sense circuits coupled with the digit lines 215, respectively. The set of sense circuits of the sense component 250 can include respective first branches of a shared differential amplifier and can share a common second branch of the shared differential amplifier. In some cases, the set of sense circuits can also include a common node that can be selectively coupled with the respective first branch of each sense circuit. Additionally, each sense circuit can include a transistor coupled with the common node to sink current (e.g., tail current) as part of detecting a first logical state. For example, as part of an access operation, the respective latch of each sense circuit can be initialized to a second logical state and the common node can undergo a voltage ramp to determine the state stored in the memory cell 205 using the voltage of the digit line 215 coupled with the memory cell 205 and the sense circuit. If the memory cell 205 stores the first logical state and the voltage of the common node falls below the threshold of the transistor positioned between the first branch and the common node, the first branch of the sense circuit can electrically couple with the common node and allow current to flow to the first branch, which can activate the gate of the set transistor for the latch. Thus, the set transistor can switch the state of the latch to the first logical state. Alternatively, if the memory cell 205 stores the second logical state, the voltage of the common node can not fall below the voltage of the digit line, which can fail to activate the set transistor and the state of the latch can not switch. Thus, the second branch of the differential amplifier shared among the set of sense circuits can reduce current consumption and thus improve the efficiency of the sense operation.

[0048] FIG. 3 An example of a sensing circuit 300 that supports sensing components with common nodes is shown in accordance with examples disclosed herein. In some cases, the sensing circuit 300 can include or can be included in a sensing component 250 as described with reference to FIG. 2 The sensing circuit 300 can include a plurality of sense amplifiers 305, such as sense amplifier 305-a through sense amplifier 305-n. Each sense amplifier 305 can be operable to determine a state stored in a memory cell coupled with a digit line 315, which can be an example of a digit line 215 as described with reference to FIG. 2 In some cases, the sensing circuit 300 can be included in a memory device, such as a FeRAM device or a NAND device. During a sensing operation, the digit line can be biased to a first voltage if the memory cell stores a first state, or a second voltage if the memory cell stores a second state. For example, the digit line can be coupled with the memory cell and a current can flow between the memory cell and the digit line. A magnitude of the current can depend on the state stored in the memory cell. Thus, a voltage of the digit line after being coupled with the memory cell can depend on the state stored in the memory cell. In some examples, the state of the memory cell can be sensed by the sense amplifier 305, such as using a differential amplifier, and stored in a respective latch 323.

[0049] In some cases, each sense amplifier 305 can include a respective first branch 310. The first branch can include a first transistor 325 having a gate coupled with the digit line 315. In some examples, the first transistor 325 can be an example of an n-type metal-oxide-semiconductor field-effect transistor (MOSFET). That is, the first transistor 325 can be configured to be activated (e.g., become conductive, electrically couple a source node and a drain node) if a voltage difference between the gate of the first transistor 325 and a terminal of the first transistor 325 exceeds a threshold voltage. In some cases, the first branch 310 can include a second transistor 330 having a gate coupled with a first reference node 335, which can be set to a bias voltage by a bias circuit (not shown). In some cases, the second transistor 330 can be an example of a p-type MOSFET. That is, the second transistor 330 can be configured to be activated (e.g., become conductive, electrically couple a source node and a drain node) if a voltage difference between the gate of the first transistor 325 and a terminal (e.g., a source terminal or a drain terminal) of the first transistor 325 is below a threshold voltage.

[0050] In some cases, the second transistor 330 can be configured to supply current to the sense amplifier 305-a (e.g., to the first branch 310 of the sense amplifier 305-a). For example, the source terminal of the second transistor 330 can be coupled with a supply voltage. If the voltage difference between the first reference node 335 and the drain terminal of the second transistor is high (e.g., above a threshold voltage of the second transistor 330), current can flow through the second transistor 330 to the first branch 310. In some instances, the current supplied by the second transistor can be relatively small (e.g., approximately 10 nanoamperes (nA)).

[0051] Additionally, the sense circuit 300 can include a second branch 320. The second branch 320 can be shared between the sense amplifiers 305, e.g., via a common node 340. In some instances, the second branch can include a third transistor 345 having a gate coupled with the first reference node 335, which can be an example of a p-type MOSFET. In some instances, the current supplied by the third transistor 345 can be greater than the current supplied by the second transistor 330. For example, the current supplied by the third transistor 345 can be approximately an integer multiple of the current supplied by the second transistor 330, where the integer multiple can be less than the number of sense amplifiers 305. In some cases, the integer multiple can depend on the number of sense amplifiers that can be simultaneously switched (e.g., statistically) from a first logic state to a second logic state. In some cases, the second branch 320 can include a fourth transistor 350 having a gate coupled with a reference voltage. That is, the first transistor 325 can be a first input transistor for a differential amplifier, and the fourth transistor 350 can be a second input transistor for the differential amplifier.

[0052] In some cases, each sense amplifier 305 can include a fifth transistor 355 to selectively couple the respective first branch 310 with the common node 340. For example, the respective first branch 310 and the common node 340 can be coupled with terminals of the fifth transistor 355, and the gate of the fifth transistor 355 can be coupled with the first node 360 of the latch 323. The fifth transistor 355 can be configured to be activated (e.g., to couple the first branch 310 with the common node 340) if the latch stores an initial state.

[0053] For example, the sixth transistor 365 can be configured to receive a reset or initialization signal to couple the first node 360 of the latch 323 with a power supply voltage 368, which can activate the fifth transistor 355. In some cases, applying the reset or initialization signal can store an initial state in the latch 323. For example, in the initial state of the latch 323, the first node 360 of the latch can be set to the power supply voltage 368. Additionally or alternatively, the fifth transistor 355 can be configured to isolate or decouple the first branch 310 from the second branch 320. In some examples, the latch 323 can be an example of a set of cross-coupled inverters. Thus, the initial state of the latch 323 can be stored (e.g., on the first node 360) until the state of the latch 323 is switched using the tenth transistor 328. Thus, if the state stored in the latch 323 switches, the voltage of the first node 360 can switch accordingly and the fifth transistor 355 can be deactivated, which can isolate or decouple the first branch 310 from the common node 340.

[0054] In some cases, the state of the latch 323 can switch (e.g., from the initial state to the second state) if the voltage of the digit line 315 and the voltage of the common node 340 satisfy a threshold. For example, during a sensing operation, the common node 340 can be configured to experience a voltage ramp, which can decrease the voltage of the common node 340 (e.g., linearly). If the difference between the voltage of the digit line 315 and the voltage of the common node 340 reaches a threshold voltage (e.g., the threshold of the first transistor 325), the first transistor 325 can activate, which in turn can activate the tenth transistor 328. Activating the tenth transistor 328 can couple the second node 370 of the latch 323 with a power supply voltage 338 to raise the voltage of the second node 370 (e.g., to overdrive the transistor in the latch that maintains the latch in the initial state). Thus, the state of the latch 323 can switch, and the first branch 310 can be isolated or decoupled from the second branch 320. In some cases, the latch 323 can include a set of cross-coupled inverters. Additionally, the pull-down transistor of the latch 323 can be smaller than the pull-up transistor (e.g., transistor 328) coupled with the first node 360 of the latch 323.

[0055] In some examples, the common node can be biased to an initial or starting voltage via a seventh transistor 380. For example, a gate of the seventh transistor 380 can be configured to receive an initialization or reset signal to activate the seventh transistor 380 and couple the common node 340 with a power node 383 that is maintained at an initial voltage. In some cases, the initial voltage can be greater than a voltage of the digit line 315. After biasing the common node 340 to the initial voltage, the seventh transistor 380 can be deactivated and the common node 340 can be caused to float. In some examples, a voltage ramp of the common node can be at least partially due to a second current drawn from the common node 340 by an eighth transistor 385. For example, the third transistor 345 can supply a current to the common node 340 and the eighth transistor 385 can couple the common node 340 with a virtual ground voltage, e.g., through a ninth transistor 395, to draw current (e.g., tail current) from the common node 340. Further, a gate of the eighth transistor 385 can be coupled with a second reference node 390, which in some cases can control a magnitude of the second current. In some cases, the current delivered via each eighth transistor 385 can be greater than the current supplied via the third transistor 345 (e.g., approximately 2 microamperes (pA)), in addition or alternatively, a voltage ramp of the common node 340 can be controlled via a reference voltage applied to the fourth transistor 350. For example, the current supplied by the third transistor 345 can be greater than the total current supplied by the eighth transistor 385 (e.g., the eighth transistor 385 in each sense amplifier 305). Thus, if a voltage difference between the gate of the fourth transistor 350 and the common node 340 is greater than a threshold value, the fourth transistor 350 will pull up the common node 340 to the threshold value.

[0056] FIG. 4 An example of a timing diagram 400 supporting a sense component having a common node is shown in accordance with examples disclosed herein. In some cases, the timing diagram 400 can be implemented by circuitry included in a memory device or memory system, such as the sense circuit 300 as described with reference to FIG. 3 The timing diagram 400 can show voltages 410 of one or more components or nodes of the sense circuit 300, such as a voltage of a common node 415, which can be an example of the common node 340 as described with reference to FIG. 3 Additionally, the timing diagram 400 can show voltages of nodes of a latch 420-a, such as a second node 370 of the latch 323 as described with reference to FIG. 3 The timing diagram 400 can be used as part of a sense operation to determine one or more states, such as a codeword, stored in a corresponding one or more memory cells.

[0057] In some cases, the timing diagram can include a first phase 425, which can be an instance of an initialization phase. During the first phase 425, a reset signal 430 can initialize one or more components of the sensing circuit 300. For example, the reset signal 430 can cause the sensing circuit 300 to bias a voltage of the common node 415 to a first voltage 435, and can cause the latch 323 to store an initial value (e.g., a logic "0").

[0058] For example, the reset signal 430 can activate the seventh transistor 380 to bias the voltage of the common node 415 to the first voltage 435. In some cases, activating the seventh transistor 380 can couple the common node 340 to a power node 383, which can be held or maintained at the first voltage 435. Additionally, the reset signal 430 can activate the sixth transistor 365 to store an initial state in the latch 323, such as by coupling the first node 360 of the latch 323 to the power voltage 368. Thus, the voltage of the first node 360 of the latch 323 can be high, which can activate the fifth transistor 355. Accordingly, as part of the first phase 425, the fifth transistor 355 can couple the first branch 310 to the common node 340 (e.g., by coupling the first transistor 325 to the common node 340). In some cases, during the first phase 425, the bias voltage of the first reference node 335 can activate the second transistor 330 to supply a first current to the first branch 310.

[0059] In some cases, the timing diagram 400 can include a second phase 440. During the second phase 440, the reset signal 430 can transition (e.g., from a low state to a high state). Accordingly, the common node 340 can be isolated from the power node 383, and the voltage of the common node 415 can float (e.g., initially at the first voltage 435). Subsequently, the voltage of the common node 415 can begin to decrease or ramp down. In some instances, because the common node 340 can be shared among the plurality of sense amplifiers 305, each sense amplifier 305 can share the same voltage of the common node 415.

[0060] In some examples, the ramp of the voltage of the common node 415 can be at least partially due to the coupling with the virtual ground. For example, as part of the second phase 440, the reference current signal 445 can become active (e.g., transition from a low state to a high state). The reference current signal 445 can be applied to the gate of the ninth transistor 395. Thus, activating the reference current signal 445 can activate the ninth transistor 395 to couple the common node 340 with the virtual ground. Thus, current can be drawn from the common node 340 (e.g., via the eighth transistor 385), which can contribute to the ramp of the voltage of the common node 415. Additionally or alternatively, the ramp of the voltage of the common node 415 can be due to a corresponding ramp of the reference voltage applied to the fourth transistor 350. For example, during the second phase 440, the reference voltage can ramp down to control the current drawn from the common node 340 by the third transistor 345. Thus, the voltage of the common node 415 can decrease along with the reference voltage.

[0061] In some cases, the voltage of the digit line 315 can correspond to a first logic value (e.g., a logic "1"). In these cases, during the second phase 440, the voltage of the common node 415 can reach a threshold voltage 450. If the first state is to be stored, the threshold voltage 450 can be a threshold that is lower than the voltage of the digit line 315. Thus, if the voltage of the common node 415 becomes lower than the threshold voltage 450 (e.g., if the voltage difference between the common node 340 and the digit line 315 satisfies the threshold), the first transistor 325 can activate. Thus, the voltage of the node 370 of the latch 420-a can, for example, rise to a high voltage 420-b, which can switch the state of the latch 323. Additionally, in response to the state switch of the latch 323, the first node 360 of the latch 323 can rise, and the fifth transistor 355 can be deactivated to isolate the first branch 310 from the common node 340.

[0062] Additionally or alternatively, the voltage of the digit line 315 can correspond to a second logic value (e.g., a logic "0"). In these cases, the threshold voltage 450 can be lower than a final voltage of the common node 415 (e.g., a final voltage 455). Thus, the first transistor 325 can not activate and the voltage of the node of the latch 420-a can not transition to a high state. Thus, the state of the latch 323 can not switch, and thus, a second current can not be drawn through the fifth transistor 355.

[0063] In some examples, the sensing circuit 300 and timing diagram 400 can be configured to determine a plurality of levels (e.g., more than two levels) stored in a memory cell. For example, the sensing circuit 300 can include additional circuitry corresponding to additional threshold voltages 450. Thus, the first transistor 325 can be activated at different threshold voltages 450 depending on the state stored in the memory cell. In some cases, the sensing circuitry 300 can include a plurality of latches corresponding to a plurality of levels, and additional threshold voltages can correspond to transistors used to switch respective states of the plurality of latches. Thus, a voltage ramp can be used to determine one of a plurality of levels stored in a memory cell.

[0064] In some cases, the ramp of the voltage of the common node 415 during the third phase can end after the voltage of the common node 415 reaches a target voltage 455, which can correspond to the end of a read operation. In some cases, the target voltage 455 can correspond to a threshold voltage of the fourth transistor 350. Thus, after the voltage of the common node 415 reaches the target voltage 455, the fourth transistor 350 can be deactivated, and the ramp of the voltage of the common node 415 can end. Additionally or alternatively, the ramp of the voltage of the common node 415 can end in response to the reference current signal 445 switching from a high state to a low state. For example, if the reference current signal 445 switches to a low state, the ninth transistor 395 can be deactivated, which can isolate the common node 340 from the virtual ground. Thus, no current can be drawn from the common node 340, and the voltage of the common node 415 can be maintained at or near the target voltage 455.

[0065] In some examples, the codeword sensed using the timing diagram 400 (e.g., the set of states stored in a memory cell coupled with a respective sense amplifier 305) can be an example of a balanced codeword. That is, the codeword can include approximately an equal number of logical “1” states and logical “0” states. Thus, during the second phase 440, approximately half of the latches 323 of the plurality of sense amplifiers 305 can switch and draw the second current, while the other approximately half of the latches 323 can not switch. Thus, the tail current consumed by the sensing circuit 300 operating according to the timing diagram 400 can be approximately half of the tail current consumed by a sensing circuit that does not include a common node 340.

[0066] FIG. 5 A block diagram 500 showing a memory device 520 supporting a sensing component with a common node is shown in accordance with the examples disclosed herein. The memory device 520 can be as described with reference to FIG. 1, for example. The memory device 520 includes a plurality of memory cells 505, a plurality of sense amplifiers 510, and a common node 515. The plurality of memory cells 505 can be as described with reference to FIG. 1, for example. The plurality of sense amplifiers 510 can be as described with reference to FIG. 1, for example. The common node 515 can be as described with reference to FIG. 1, for example. FIGS. 1-4Examples of aspects of the described memory device. The memory device 520, or various components thereof, can be examples of means for performing various aspects of sensing components with common nodes as described herein. For example, the memory device 520 can include a coupling control component 525, a current source component 530, a current sink component 535, a voltage ramp component 540, an initialization component 545, or any combination thereof. Each of these components can communicate, directly or indirectly (e.g., via one or more buses), with one another.

[0067] The coupling control component 525 can be configured as, or otherwise support, means for coupling a first transistor with a first node of a sense amplifier based at least in part on activating a second transistor coupled with a latch of the sense amplifier, where activating the second transistor is based at least in part on a first state of the latch. The current source component 530 can be configured as, or otherwise support, means for sourcing a first current to the first transistor based at least in part on activating a third transistor, where the third transistor is coupled with a first bias voltage and the first transistor. The current sink component 535 can be configured as, or otherwise support, means for sinking a second current from the first node based at least in part on activating a fourth transistor, where a voltage ramp of the first node is based at least in part on the second current. In some examples, the coupling control component 525 can be configured as, or otherwise support, means for activating the first transistor based at least in part on a voltage difference between the first node and a digit line satisfying a threshold, the voltage difference based at least in part on the voltage ramp, where the first transistor causes the latch to switch from the first state to a second state based at least in part on the voltage difference between the first node and the digit line satisfying the threshold.

[0068] In some examples, the voltage ramp component 540 can be configured as, or otherwise support, means for applying a second voltage ramp to a fifth transistor coupled with the first node, where the voltage ramp of the first node is based at least in part on the second voltage ramp.

[0069] In some examples, the current source component 530 can be configured as, or otherwise support, means for sourcing a third current to a terminal of the fifth transistor, where a combined current including the second current from a plurality of sense amplifiers is sourced by the third current prior to activation of first transistors of the plurality of sense amplifiers.

[0070] In some examples, the voltage ramp component 540 can be configured as, or otherwise support, means for initiating a voltage ramp based at least in part on coupling a fourth transistor with a virtual ground voltage via a fifth transistor having a gate coupled with a reference current.

[0071] In some examples, the coupling control component 525 can be configured as or otherwise support means for isolating the first transistor from the first node based at least in part on deactivating the second transistor, where activating the second transistor is based at least in part on switching the latch from the first state to the second state.

[0072] In some examples, the initialization component 545 can be configured as or otherwise support means for initiating the first state of the latch via an activation voltage, where coupling the first transistor with the first node is based at least in part on the initiating.

[0073] In some examples, the voltage ramp component 540 can be configured as or otherwise support means for biasing the first node to an initial voltage of a voltage ramp via a fifth transistor coupled with the initial voltage and the first node. In some examples, the coupling control component 525 can be configured as or otherwise support means for isolating the first node from the initial voltage based at least in part on applying a signal to a gate of the fifth transistor, where the voltage ramp is based at least in part on drawing a second current from the first node.

[0074] FIG. 6 A flow diagram illustrating a method 600 that supports a sensing component with a common node in accordance with examples as disclosed herein is shown. The operations of method 600 can be implemented by a memory device or its components as described herein. For example, the operations of method 600 can be performed by a memory device as described with reference to FIGS. 1-4. FIGS. 1-5 In some examples, a memory device can execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device can perform aspects of the functions described below using special-purpose hardware.

[0075] At 605, the method can include coupling a first transistor with a first node of a sense amplifier based at least in part on activating a second transistor coupled with a latch of the sense amplifier, where activating the second transistor is based at least in part on a first state of the latch. The operations of 605 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 605 can be performed by a coupling control component 525 as described with reference to FIGS. 1-4. FIG. 5

[0076] At 610, the method can include supplying a first current to the first transistor based at least in part on activating a third transistor, where the third transistor is coupled with a first bias voltage and the first transistor. The operations of 610 can be performed in accordance with examples as disclosed herein. In some examples, aspects of the operations of 610 can be performed by a current source component 530 as described with reference to FIGS. 1-4. FIG. 5

[0077] ​​At 615, the method can include drawing a second current from the first node based at least in part on activating the fourth transistor, where a voltage ramp of the first node is based at least in part on the second current. The operations of 615 can be performed according to examples as disclosed herein. In some examples, aspects of the operations of 615 can be performed by a current sink component 535 as described with reference to FIG. 5

[0078] At 620, the method can include activating the first transistor based at least in part on a voltage difference between the first node and the digit line satisfying a threshold, the voltage difference based at least in part on the voltage ramp, where the first transistor causes the latch to switch from the first state to the second state based at least in part on the voltage difference between the first node and the digit line satisfying the threshold. The operations of 620 can be performed according to examples as disclosed herein. In some examples, aspects of the operations of 620 can be performed by a coupling control component 525 as described with reference to FIG. 5

[0079] In some examples, an apparatus described herein can perform one or more methods, such as method 600. The apparatus can include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing aspects of the present disclosure, or any combination thereof:

[0080] Aspect 1 : A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: coupling a first transistor with a first node of a sense amplifier based at least in part on activating a second transistor coupled with a latch of the sense amplifier, where activating the second transistor is based at least in part on a first state of the latch; supplying a first current to the first transistor based at least in part on activating a third transistor, where the third transistor is coupled with a first bias voltage and the first transistor; drawing a second current from the first node based at least in part on activating a fourth transistor, where a voltage ramp of the first node is based at least in part on the second current; and activating the first transistor based at least in part on a voltage difference between the first node and a digit line satisfying a threshold, the voltage difference based at least in part on the voltage ramp, where the first transistor causes the latch to switch from the first state to a second state based at least in part on the voltage difference between the first node and the digit line satisfying the threshold.

[0081] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuitry, logic, means, or instructions for, or any combination thereof: applying a second voltage ramp to a fifth transistor coupled with the first node, where the voltage ramp of the first node is based at least in part on the second voltage ramp. ​​

[0082] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of Aspect 2, further including operations, features, circuitry, logic, means, or instructions for, or any combination of the same, supplying a third current to a terminal of the fifth transistor, wherein the combined current including the second current from the plurality of sense amplifiers is supplied by the third current prior to activation of the first transistor of the plurality of sense amplifiers.

[0083] Aspect 4: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1-3, further including operations, features, circuitry, logic, means, or instructions for, or any combination of the same, coupling the fourth transistor to a virtual ground voltage based at least in part on the fifth transistor having a gate coupled with a reference current.

[0084] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1-4, further including operations, features, circuitry, logic, means, or instructions for, or any combination of the same, isolating the first transistor from the first node based at least in part on deactivating the second transistor, wherein activating the second transistor is based at least in part on switching the latch from the first state to the second state.

[0085] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1-5, further including operations, features, circuitry, logic, means, or instructions for, or any combination of the same, initiating the first state of the latch via an activation voltage, wherein coupling the first transistor with the first node is based at least in part on the initiating.

[0086] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of any of Aspects 1-6, further including operations, features, circuitry, logic, means, or instructions for, or any combination of the same, biasing the first node to an initial voltage of a voltage ramp via the fifth transistor coupled with the initial voltage and the first node, and isolating the first node from the initial voltage based at least in part on applying a signal to a gate of the fifth transistor, wherein the voltage ramp is based at least in part on drawing the second current from the first node.

[0087] It should be noted that the methods described herein are possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0088] An apparatus is described. The following provides an overview of aspects of an apparatus as described herein:

[0089] Aspect 8: An apparatus comprising: a memory cell; a sense amplifier coupled with the memory cell via a digit line, the sense amplifier comprising: a latch; a first transistor having a gate coupled with the digit line, wherein a first state of the latch couples the first transistor with a first node and a second state of the latch decouples the first transistor from the first node; a second transistor having a gate coupled with a first bias voltage, a terminal of the second transistor coupled with a terminal of the first transistor, wherein the second transistor is configured to provide a first current; and a third transistor having a first terminal coupled with the first node, wherein the third transistor is configured to sink a second current from the first node; and a fourth transistor coupled with the sense amplifier and configured to provide a voltage ramp on the first node, wherein the first transistor is configured to switch the latch from the first state to the second state based at least in part on a voltage difference between the digit line and the first node satisfying a threshold.

[0090] Aspect 9: The apparatus of aspect 8, wherein a gate of the fourth transistor is coupled with a reference voltage configured to provide a second voltage ramp, and the voltage ramp on the first node is based at least in part on the second voltage ramp.

[0091] Aspect 10: The apparatus of any one of aspects 8-9, further comprising: a fifth transistor coupled with the sense amplifier and configured to bias the first node to an initial voltage of the voltage ramp, wherein a gate of the fifth transistor is coupled with an activation voltage and a terminal of the fifth transistor is coupled with the initial voltage.

[0092] Aspect 11 : The apparatus of any one of aspects 8-10, wherein the sense amplifier further comprises: a fifth transistor having a first terminal coupled with the first transistor, a second terminal coupled with the first node, and a gate coupled with the latch, wherein the fifth transistor is configured to couple the first transistor with the first node based at least in part on the first state of the latch.

[0093] Aspect 12: The apparatus of aspect 11, wherein the fifth transistor is further configured to isolate the first transistor from the first node based at least in part on the latch switching from the first state to the second state.

[0094] Aspect 13: The apparatus of any one of aspects 8-12, wherein a second terminal of the second transistor is coupled with a supply voltage, and the first current is based at least in part on the supply voltage.

[0095] Aspect 14: The apparatus of any one of aspects 8-13, further comprising: a fifth transistor coupled with a second terminal of the third transistor and a virtual ground voltage, wherein the fifth transistor is configured to sink a third current from the third transistors of a plurality of sense amplifiers.

[0096] Aspect 15: The apparatus of any one of aspects 8 through 14, wherein the sense amplifier further includes: a fifth transistor coupled having a gate coupled with a terminal of the second transistor and a terminal coupled with a supply voltage, wherein the fifth transistor is configured to couple the first node of the latch with the supply voltage based at least in part on a voltage difference between the digit line and the first node satisfying a threshold; and a sixth transistor having a gate coupled with an activation voltage and a terminal coupled with the supply voltage, wherein the sixth transistor is configured to couple the second node of the latch with the supply voltage based at least in part on the activation voltage.

[0097] Aspect 16: The apparatus of any one of aspects 8 through 15, further comprising: a fifth transistor having a gate coupled with a first bias voltage, a first terminal coupled with a terminal of the fourth transistor, and a second terminal coupled with a supply voltage.

[0098] Aspect 17: The apparatus of any one of aspects 8 through 16, wherein the memory cell includes a volatile memory cell.

[0099] Aspect 18: The apparatus of any one of aspects 8 through 17, wherein the memory cell includes a non-volatile memory cell.

[0100] An apparatus is described. Summaries of aspects of apparatus as described herein are provided below:

[0101] Aspect 19: An apparatus comprising: a plurality of memory cells; a plurality of sense amplifiers coupled with the plurality of memory cells via a plurality of digit lines, respectively, wherein each sense amplifier of the plurality of sense amplifiers includes: a latch; a first branch of a plurality of first branches of a differential amplifier, the first branch including a first transistor having a gate coupled with a digit line of the plurality of digit lines and a second transistor having a gate coupled with a first bias voltage, wherein the second transistor is configured to supply a first current to a terminal of the first transistor, and wherein a first state of the latch couples the first transistor with a first node and a second state of the latch decouples the first transistor from the first node; and a third transistor having a gate coupled with a second bias voltage and a terminal coupled with the first node, wherein the third transistor is configured to sink a second current from the first node; and a second branch of the differential amplifier including a fourth transistor having a gate coupled with the first bias voltage and a fifth transistor having a gate coupled with a reference voltage and a terminal coupled with the first node of the plurality of sense amplifiers, wherein for each sense amplifier, the first transistor is configured to switch the latch from the first state to the second state based at least in part on a voltage ramp on the first node causing a voltage difference between the digit line associated with each sense amplifier and the first node to satisfy a threshold.

[0102] Aspect 20: The apparatus of Aspect 19, wherein the reference voltage is configured to provide a second voltage ramp to a gate of the fifth transistor, and the voltage ramp on the first node is based at least in part on the second voltage ramp.

[0103] Aspect 21 : The apparatus of any one of Aspects 19-20, wherein the first node is common to each of the plurality of sense amplifiers.

[0104] Aspect 22: The apparatus of Aspect 21, further comprising: a sixth transistor coupled with the first node and configured to bias the first node to an initial voltage of the voltage ramp, wherein a gate of the sixth transistor is coupled with an activation voltage and a terminal of the sixth transistor is coupled with the initial voltage.

[0105] Aspect 23: The apparatus of any one of Aspects 19-22, wherein each of the plurality of sense amplifiers further comprises: a sixth transistor having a first terminal coupled with the first transistor, a second terminal coupled with the first node, and a gate coupled with a latch, wherein the sixth transistor is configured to couple the first transistor with the first node based at least in part on a first state of the latch.

[0106] Aspect 24: The apparatus of Aspect 23, wherein the sixth transistor is further configured to isolate the first transistor from the first node based at least in part on the latch switching from the first state to a second state.

[0107] Aspect 25: The apparatus of any one of Aspects 19-24, wherein the plurality of states stored in the plurality of memory cells are balanced codewords.

[0108] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0109] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which an electrical signal is supported to flow between the components. The components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there exists any conductive path between the components that can support the flow of a signal between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be an open circuit or a closed circuit at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of a signal between connected components can be interrupted for a period of time, e.g., using one or more intervening components such as switches or transistors.

[0110] The term "coupled" refers to the condition of components moving from an open circuit relationship between the components, in which a signal cannot currently pass between the components through a conductive path, to a closed circuit relationship between the components, in which a signal can pass between the components through a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows a signal to flow between the other components via a conductive path that previously did not permit the flow of a signal.

[0111] The term "isolated" refers to a relationship between components in which a signal cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, components that are isolated from each other by a switch positioned between the two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller effects a change that prevents a signal from flowing between the components using a conductive path that previously permitted the flow of a signal.

[0112] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term substantially) is not absolute but is close enough to the ideal characteristic so as to achieve the purpose of the characteristic.

[0113] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0114] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic elements by conductive materials, such as metals. The source and drain can be conductive and can include heavily doped, e.g., degenerate, semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "on" or "activated" if a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. A transistor can be "off' or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0115] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0116] In the appended figures, similar components or features can have similar reference labels. Further, various components of the same type can be distinguished by following the convention of using a first reference label in combination with a second reference label that distinguishes among different instances of that component. For example, a first instance of a component might be referred to as "22," whereas a second instance of that same type of component might be referred to as "22a." The components can also be distinguished using only the first reference label in some cases.

[0117] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transferred across a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations thereof. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0118] The various illustrative blocks and modules described in connection with the present disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0119] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a referring to a closed set of conditions. For example, an exemplary step that is described as “based on condition A” can be based on both condition A and condition B without deviating from the scope of the present disclosure. In other words, as used herein, the phrase “based on” is interpreted similarly to the phrase “based at least in part on.”

[0120] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0121] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: a memory cell; a sense amplifier coupled with the memory cell via a digit line, the sense amplifier comprising: a latch; a first transistor having a gate coupled with the digit line, wherein a first state of the latch couples the first transistor with a first node and a second state of the latch decouples the first transistor from the first node; a second transistor having a gate coupled with a first bias voltage, a terminal of the second transistor coupled with a terminal of the first transistor, wherein the second transistor is configured to provide a first current; a third transistor having a first terminal coupled with the first node, wherein the third transistor is configured to sink a second current from the first node; and a fourth transistor coupled with the sense amplifier and configured to provide a voltage ramp on the first node, wherein the first transistor is configured to switch the latch from the first state to the second state based at least in part on a voltage difference between the digit line and the first node satisfying a threshold.

2. The memory device of claim 1, wherein a gate of the fourth transistor is coupled with a reference voltage configured to provide a second voltage ramp, and the voltage ramp on the first node is based at least in part on the second voltage ramp.

3. The memory device of claim 1, further comprising: a fifth transistor coupled with the sense amplifier and configured to bias the first node to an initial voltage of the voltage ramp, wherein a gate of the fifth transistor is coupled with an activation voltage and a terminal of the fifth transistor is coupled with the initial voltage.

4. The memory device of claim 1, wherein the sense amplifier further comprises: a fifth transistor having a first terminal coupled with the first transistor, a second terminal coupled with the first node, and a gate coupled with the latch, wherein the fifth transistor is configured to couple the first transistor with the first node based at least in part on the first state of the latch.

5. The memory device of claim 4, wherein the fifth transistor is further configured to isolate the first transistor from the first node based at least in part on the latch switching from the first state to the second state.

6. The memory device of claim 1, wherein a second terminal of the second transistor is coupled with a supply voltage, and the first current is based at least in part on the supply voltage.

7. The memory device of claim 1, further comprising: a fifth transistor coupled with a second terminal of the third transistor and a virtual ground voltage, wherein the fifth transistor is configured to sink a third current from the third transistors of a plurality of sense amplifiers.

8. The memory device of claim 1, wherein the sense amplifier further comprises: a fifth transistor having a gate coupled with the terminal of the second transistor and a terminal coupled with a power supply voltage, wherein the fifth transistor is configured to couple a first node of the latch with the power supply voltage based at least in part on the voltage difference between the digit line and the first node satisfying the threshold; and a sixth transistor having a gate coupled with an activation voltage and a terminal coupled with the power supply voltage, wherein the sixth transistor is configured to couple a second node of the latch with the power supply voltage based at least in part on the activation voltage.

9. The memory device of claim 1, further comprising: a fifth transistor having a gate coupled with the first bias voltage, a first terminal coupled with a terminal of the fourth transistor, and a second terminal coupled with a power supply voltage.

10. The memory device of claim 1, wherein the memory cells comprise volatile memory cells.

11. The memory device of claim 1, wherein the memory cells comprise non-volatile memory cells.

12. A memory device, comprising: a plurality of memory cells; a plurality of sense amplifiers respectively coupled with the plurality of memory cells via a plurality of digit lines, wherein each sense amplifier of the plurality of sense amplifiers comprises: a latch; a first branch of a plurality of first branches of a differential amplifier, the first branch comprising a first transistor having a gate coupled with a digit line of the plurality of digit lines and a second transistor having a gate coupled with a first bias voltage, wherein the second transistor is configured to supply a first current to a terminal of the first transistor, and wherein a first state of the latch couples the first transistor with a first node and a second state of the latch decouples the first transistor from the first node; a third transistor having a gate coupled with a second bias voltage and a terminal coupled with the first node, wherein the third transistor is configured to sink a second current from the first node; and a second branch of the differential amplifier comprising a fourth transistor having a gate coupled with the first bias voltage and a fifth transistor having a gate coupled with a reference voltage and a terminal coupled with the first node of the plurality of sense amplifiers, wherein for each sense amplifier, the first transistor is configured to switch the latch from the first state to the second state based at least in part on a voltage difference between a digit line associated with the each sense amplifier and the first node satisfying a threshold based at least in part on a voltage ramp on the first node.

13. The memory device of claim 12, wherein the reference voltage is configured to provide a second voltage ramp to the gate of the fifth transistor, and the voltage ramp on the first node is based at least in part on the second voltage ramp.

14. The memory device of claim 12, wherein the first node is common to each sense amplifier of the plurality of sense amplifiers.

15. The memory device of claim 14, further comprising: a sixth transistor coupled with the first node and configured to bias the first node to an initial voltage of the voltage ramp, wherein a gate of the sixth transistor is coupled with an activation voltage and a terminal of the sixth transistor is coupled with the initial voltage.

16. The memory device of claim 12, wherein each sense amplifier of the plurality of sense amplifiers further comprises: a sixth transistor having a first terminal coupled with the first transistor, a second terminal coupled with the first node, and a gate coupled with the latch, wherein the sixth transistor is configured to couple the first transistor with the first node based at least in part on the first state of the latch.

17. The memory device of claim 16, wherein the sixth transistor is further configured to isolate the first transistor from the first node based at least in part on the latch switching from the first state to a second state.

18. The memory device of claim 12, wherein a plurality of states stored in the plurality of memory cells are balanced codewords.

19. A method performed by a memory device, comprising: coupling a first transistor with a first node of a sense amplifier based at least in part on activating a second transistor coupled with a latch of the sense amplifier, wherein activating the second transistor is based at least in part on a first state of the latch; supplying a first current to the first transistor based at least in part on activating a third transistor, wherein the third transistor is coupled with a first bias voltage and the first transistor; sinking a second current from the first node based at least in part on activating a fourth transistor, wherein a voltage ramp of the first node is based at least in part on the second current; and activating the first transistor based at least in part on a voltage difference between the first node and a digit line satisfying a threshold, the voltage difference based at least in part on the voltage ramp, wherein the first transistor causes the latch to switch from the first state to a second state based at least in part on the voltage difference between the first node and the digit line satisfying the threshold.

20. The method of claim 19, further comprising: applying a second voltage ramp to a fifth transistor coupled with the first node, wherein the voltage ramp of the first node is based at least in part on the second voltage ramp.

21. The method of claim 20, further comprising: supplying a third current to a terminal of the fifth transistor, wherein a combined current including the second current from a plurality of sense amplifiers is supplied by the third current prior to activation of the first transistors of the plurality of sense amplifiers.

22. The method of claim 19, further comprising: initiating the voltage ramp based at least in part on coupling the fourth transistor with a virtual ground voltage via a fifth transistor having a gate coupled with a reference current.

23. The method of claim 19, further comprising: isolating the first transistor from the first node based at least in part on deactivating the second transistor, wherein activating the second transistor is based at least in part on switching the latch from the first state to the second state.

24. The method of claim 19, further comprising: initiating the first state of the latch via an activation voltage, wherein coupling the first transistor with the first node is based at least in part on the initiating.

25. The method of claim 19, further comprising: biasing the first node to an initial voltage of the voltage ramp via a fifth transistor coupled with the initial voltage and the first node; and isolating the first node from the initial voltage based at least in part on applying a signal to a gate of the fifth transistor, wherein the voltage ramp is based at least in part on drawing the second current from the first node.

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