Performance adjustment of memory devices

Abstract

This application relates to performance adjustment for memory devices. In some examples, a memory system can receive a command (e.g., a read command or a write command) that includes an indicator. The indicator can indicate that the memory system is to suppress one or more portions of the command. For example, the command can be received by an interface of the memory system, and the controller can indicate that the memory system is to suppress one or more operations performed by a processor of the memory system, a memory controller of the memory system, or both. In suppressing one or more operations associated with the command, the memory system can output a response to a test system, which can allow the test system to adjust one or more performance aspects of the memory system.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 646,256, filed by GE on December 28, 2021, entitled “Performance Tuning for a Memory Device,” which is assigned to the assignee and is expressly incorporated herein by reference. Technical Field

[0003] This technical field relates to performance tuning of memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to typically correspond to one of two supported states, logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even without an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory system including an interface, a processor, and a memory controller, wherein: the interface is configured such that the apparatus: receives a read command, the read command including an indicator for partial execution of the read command; and performs a first operation associated with the read command at least in part based on receiving the read command, the first operation including generating an entry associated with the read command for a command queue of the processor based on one or more parameters of the read command; and at least one of the processor or the memory controller is configured such that the apparatus: suppresses one or more additional operations associated with the read command at least in part based on executing the first operation and based on the indicator for partial execution of the read command; and outputs a response indicating completion of the read command at least in part based on executing the first operation and suppressing the one or more additional operations, wherein the response includes padding data generated at least in part based on suppressing the one or more additional operations.

[0007] Describe a device. The device may include: a memory system including an interface, a processor, and a memory controller, wherein: the interface is configured such that the device: receives a write command, the write command including an indicator for partial execution of the write command; and performs, at least in part, a first operation associated with the write command based on receiving the write command, the first operation including generating an entry associated with the write command for a command queue of the processor based on one or more parameters of the write command; and at least one of the processor or the memory controller is configured such that the device: performs, at least in part, the first operation associated with the write command based on the interface and suppresses one or more additional operations associated with the write command based on the indicator for partial execution of the write command, wherein the one or more additional operations associated with the write command are suppressed by the processor, the memory controller, or both; and outputs a response indicating completion of the write command based, at least in part, on performing the first operation and suppressing the one or more additional operations.

[0008] Describing a non-transitory computer-readable medium. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a read command at an interface of a memory system including a processor and a memory controller, wherein the read command includes an indicator for partial execution of the read command; perform, at least partially based on the interface, a first operation associated with the read command, the first operation including generating an entry associated with the read command for a command queue of the processor based on one or more parameters of the read command; perform the first operation at least partially based on the interface and suppress one or more additional operations associated with the read command based on the indicator for partial execution of the read command, wherein the one or more additional operations associated with the read command are suppressed by the processor, the memory controller, or both; and output a response from the interface at least partially based on performing the first operation and suppressing the one or more additional operations, instructing the memory system to complete the read command, wherein the response includes padding data generated at least partially based on suppressing the one or more additional operations.

[0009] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a write command at an interface of a memory system including a processor and a memory controller, wherein the write command includes an indicator for partial execution of the write command; perform, at least in part based on the received write command, a first operation associated with the write command by the interface, the first operation including generating an entry associated with the write command for a command queue of the processor based on one or more parameters of the write command; perform, at least in part based on the interface, the first operation associated with the write command and suppress one or more additional operations associated with the write command based on the indicator for partial execution of the write command, wherein the one or more additional operations associated with the write command are suppressed by the processor, the memory controller, or both; and output a response instructing the memory system to complete the write command by the interface, at least in part based on the performance of the first operation and the suppression of the one or more additional operations. Attached Figure Description

[0010] Figure 1 Examples of systems that support performance tuning of memory devices, as disclosed herein, are shown.

[0011] Figure 2 Examples of systems that support performance tuning of memory devices, as disclosed herein, are shown.

[0012] Figure 3 An example of a process flowchart illustrating performance tuning of a memory device based on examples disclosed herein is shown.

[0013] Figure 4 An example of a process flowchart illustrating performance tuning of a memory device based on examples disclosed herein is shown.

[0014] Figure 5 A block diagram of a memory controller 1 that supports performance tuning of a memory device according to an example disclosed herein is shown.

[0015] Figure 6 A block diagram of a memory controller 2 that supports performance tuning of a memory device according to an example disclosed herein is shown.

[0016] Figure 7 and 8 The flowchart illustrates one or more methods for supporting performance tuning of memory devices, based on examples as disclosed herein. Detailed Implementation

[0017] Some memory systems may contain various hardware or software components for executing commands received from a host system or test apparatus. For example, a memory system may include a front-end (e.g., a hardware interface), a flash translation layer (e.g., (FTL), a processor), and a back-end (e.g., a memory controller) configured to receive and execute various commands. In some cases, it may be necessary to perform test operations on the memory system to determine whether errors occurred at different hardware or software components during command execution, which can allow the host system or test apparatus to tune aspects of the memory system's performance. However, in conventional memory systems, an error may only be notified to the host system or test apparatus that it occurred while processing a command. In other words, the host system or test apparatus may not be able to specifically identify where the error occurred.

[0018] This document describes a memory system configured to suppress commands. In some instances, the memory system may receive commands (e.g., read commands, write commands) from a host system or test apparatus. The commands may include indicators instructing the memory system to suppress one or more operations associated with executing the command. For example, the indicators may include a first value that instructs the memory system to suppress operations performed by its front-end layer (FTL) (e.g., its processor) and back-end layer (e.g., its memory controller). In other instances, the indicators may indicate a second value that instructs the memory system to suppress operations performed by its back-end layer. In any instance, the memory system may be configured to generate a response indicating that the command has been completed, even if the command has not been fully executed. Therefore, by suppressing one or more operations associated with executing the command, the host system or test apparatus can identify where a performance problem occurs. For example, the host system or test apparatus can determine whether the performance problem occurs in the front-end, FTL, or back-end layer, which can allow the host system or test apparatus to adjust the performance of the memory system to improve its overall performance.

[0019] First, refer to Figure 1 and 2 The features of this disclosure are described within the context of the system described. (See references...) Figure 3 and 4 The features of this disclosure are described in the context of a process flowchart. Further references are provided. Figure 5-8 Device diagrams and flowcharts relating to performance tuning of memory devices are shown and described in the context of the device diagrams and flowcharts. These and other features of this disclosure are described.

[0020] Figure 1 An example of a system 100 that supports performance tuning of a memory device according to examples disclosed herein is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0021] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0022] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or any other computing device containing memory and processing means.

[0023] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a controller or control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed via the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0024] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0025] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0026] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface), and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or updating data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0027] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0028] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0029] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, data may be stored in local memory 120, and the data may be available in local memory 120 for subsequent retrieval or operation (e.g., update) by the host system 105 according to a caching strategy (e.g., reduced latency relative to memory device 130).

[0030] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on external controllers (e.g., implemented by host system 105) or one or more local controllers 135 that may be internal to memory device 130 to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 managed at least in part by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0031] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0032] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0033] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0034] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity for supporting circuitry.

[0035] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, a single block 170 may be referred to as a physical block, and virtual block 180 may refer to a group of blocks 170 within which parallel operations may occur. For example, parallel operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as virtual block 180. In some cases, a virtual block may contain blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory devices 130-a and 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be “block 0” of plane 165-a, block 170-b may be “block 0” of plane 165-b, etc.). In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0036] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (e.g., simultaneously programmed or read as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., simultaneously erased as part of a single erase operation). Additionally, in some cases, NAND memory cells can be erased before they are rewritten with new data. Therefore, for example, in some cases, page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0038] In some cases, an L2P mapping table can be maintained, and data can be marked as valid or invalid at the page granularity level. Page 175 may contain valid data, invalid data, or no data. Invalid data can be outdated data because the latest version or a newer version of the data is stored in a different page 175 of memory device 130. Invalid data may have been previously programmed into an invalid page 175, but may no longer be associated with a valid logical address, such as a logical address referenced by host system 105. Valid data can be the latest version of such data stored on memory device 130. Page 175 that does not contain data can be a page 175 that has not been written to or has been erased.

[0039] System 100 may include any number of non-transitory computer-readable media that support performance tuning of the memory device. For example, host system 105, memory system controller 115, or memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0040] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0041] In some instances, memory system controller 115 (e.g., a portion of memory system controller 115, an interface to memory system controller 115) may be configured to receive commands from host system 105. The commands may include indicators that instruct memory system controller 115 to suppress one or more portions of the commands. For example, the indicator may be a first value that instructs memory system controller 115 to suppress command aspects related to determining the physical address of the memory device 130 associated with the command and executing the command (e.g., reading or writing data associated with the command). In other instances, the indicator may be a second value that instructs memory system controller to suppress command aspects related to execution.

[0042] When suppressing a command, the memory system controller 115 can generate a response for output (e.g., transfer) to the host system 105. In the case of a read command, the memory system controller 115 can generate padding data (e.g., data not read from the physical address of the memory device 130 corresponding to the read command) to output along with the response. The memory system controller 115 can output a response (containing padding data in the case of receiving a read command) that can indicate to the host system 105 that the command has been executed.

[0043] By partially executing commands (e.g., read or write commands), host system 105 can identify performance issues related to operations performed by aspects of memory system controller 115. Therefore, host system 105 can adjust the performance of memory system 110, which can improve the overall performance of memory system 110.

[0044] Figure 2 An example of a system 200 supporting performance tuning of a memory device, as disclosed herein, is shown. System 200 may be as described in the references... Figure 1 An example of system 100 described in the description of the present invention. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may implement references to Figure 1The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0045] Memory system 210 may include memory device 240 for storing, for example, data transferred between memory system 210 and host system 205 in response to receiving an access command from host system 205, as described herein. Memory device 240 may include, as referenced... Figure 1 The memory device 240 may include one or more memory devices. For example, memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-point, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0046] Memory system 210 may include a memory controller 230 for controlling the transfer of data directly to and from memory device 240, such as for storing data, retrieving data, and determining memory locations where data is to be stored and retrieved. The memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, for example, different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may be implemented as described in reference [reference missing]. Figure 1 Aspects of the local controller 135 described.

[0047] The memory system 210 may additionally include an interface 220 for communicating with the host system 205, and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and memory controller 230 can be used, for example, to transfer data between the host system 205 and the memory device 240 as shown by the data path 250, and can be collectively referred to as the data path components.

[0048] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling bursts of commands, and once the burst has stopped, the buffered data can be stored or transmitted (or both). Buffer 225 may include relatively fast memory (e.g., some type of volatile memory such as SRAM or DRAM), or hardware accelerators, or both, to allow for rapid storage of data into and from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0049] Temporary storage of data within buffer 225 refers to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., it may be overwritten by data from an additional access command). Furthermore, buffer 225 can be a non-cached buffer. That is, host system 205 may not read data directly from buffer 225. For example, a read command can be added to a queue without requiring an address to be matched against an address already in buffer 225 (e.g., no cached address matching or lookup operation is needed).

[0050] The memory system 210 may additionally include a memory system controller 215 for executing commands received from the host system 205 and controlling data path components when moving data. The memory system controller 215 may be as described in reference... Figure 1 An example of a memory system controller 115 is described. Bus 235 can be used for communication between system components.

[0051] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. For example, this may be advantageous if the memory system 210 processes more than one access command from the host system 205 in parallel. As examples of possible implementations, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, queues (if used) may be located anywhere within the memory system 210.

[0052] Data transferred between host system 205 and memory device 240 may take a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0053] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered the front end of memory system 210. Upon receiving each access command, interface 220 can transmit the command to memory system controller 215, for example, via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0054] The memory system controller 215 can determine that an access command has been received based on communication from interface 220. In some cases, the memory system controller 215 can determine that an access command has been received by retrieving a command from command queue 260. After, for example, the command has been retrieved from command queue 260 by memory system controller 215, the command can be removed from the command queue. In some cases, the memory system controller 215 can cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0055] After confirming that an access command has been received, the memory system controller 215 can execute the access command. For a read command, this could mean obtaining data from the memory device 240 and transferring data to the host system 205. For a write command, this could mean receiving data from the host system 205 and moving data to the memory device 240.

[0056] In either case, the memory system controller 215 may use the buffer 225, particularly for temporary storage of data received from or sent to the host system 205. The buffer 225 can be considered an intermediate point of the memory system 210. In some cases, buffer address management (e.g., pointers to address locations within the buffer 225) may be performed by hardware (e.g., dedicated circuitry) in the interface 220, the buffer 225, or the memory controller 230.

[0057] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the write command, for example via firmware (e.g., controller firmware).

[0058] In some cases, buffer queue 265 can be used to control a stream of commands associated with data stored in buffer 225, the stream of commands including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 can be moved to buffer queue 265 via memory system controller 215 and can remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating the location in buffer 225 that stores data associated with each command can be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least some portions of the access commands can be processed in parallel.

[0059] If buffer 225 has sufficient space to store the write data, memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "ready to transfer" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0060] Once the written data has been stored in buffer 225 via interface 220, the data can be transferred from buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the data transfer to memory device 240 has been completed.

[0061] In some cases, memory queue 270 can be used to assist in the transfer of write data. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain entries for each access command. In some instances, memory queue 270 may additionally contain: a buffer pointer (e.g., an address) indicating where in buffer 225 the data associated with the command is stored; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location within buffer 225 from which data is obtained, either from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the location of stored data within memory device 240 (e.g., for wear leveling, garbage collection, etc.). Entries can be added to memory queue 270, for example, via memory system controller 215. After the data transfer is complete, the entry can be removed from the storage queue 270, for example, via the storage controller 230 or the memory system controller 215.

[0062] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space available in buffer 225 to store the data associated with the read command, for example via firmware (e.g., controller firmware).

[0063] In some cases, buffer queue 265 can be used to supplement buffer storage of data associated with read commands in a manner similar to that discussed above regarding write commands. For example, if buffer 225 has sufficient space to store read data, memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Memory controller 230 can indicate to memory system controller 215, for example, via bus 235, when data transfer to buffer 225 has been completed.

[0064] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of data retrieved from the memory device 240 from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location of data stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of stored data in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0065] Once data has been stored in buffer 225 by storage controller 230, it can be transferred out of buffer 225 and sent to host system 205. For example, storage system controller 215 may enable interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 may process commands from command queue 260 and may indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 has been completed.

[0066] The memory system controller 215 can execute received commands in a sequence (e.g., according to the first-in-first-out order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of buffer 225, as discussed above. While the data is moved into buffer 225 and stored therein, the command can remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), the command can be removed from buffer queue 265, for example, via the memory system controller 215. If the command is removed from buffer queue 265, the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0067] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, garbage collection, error control (e.g., error detection or error correction), encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. In some cases, one or more adjacent LBAs may correspond to non-adjacent physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0068] In some instances, memory system controller 215 (e.g., a portion of memory system controller 215, an interface of memory system controller 215) may be configured to receive commands from host system 205. The commands may include indicators that instruct memory system controller 215 to suppress one or more portions of the commands. For example, the indicator may be a first value that instructs memory system controller 215 to suppress command aspects related to determining the physical address of the memory device 240 associated with the command and executing the command (e.g., reading or writing data associated with the command). In other instances, the indicator may be a second value that instructs memory system controller to suppress command aspects related to execution.

[0069] When suppressing commands, the memory system controller 215 can generate a response for output (e.g., transmission) to the host system 205. In the case of a read command, the memory system controller 215 can generate padding data (e.g., data not read from the physical address of the memory device 240 corresponding to the read command) to output along with the response. The memory system controller 215 can output a response (containing padding data in the case of receiving a read command) that can indicate to the host system 205 that the command has been executed.

[0070] By partially executing commands (e.g., read or write commands), host system 205 can identify performance issues related to operations performed by aspects of memory system controller 215. Therefore, host system 205 can adjust the performance of memory system 210, which can improve the overall performance of memory system 210.

[0071] Figure 3 An example of a process flowchart 300 supporting performance tuning of a memory device according to examples disclosed herein is shown. Process flowchart 300 may illustrate operations performed at test system 305 and memory system 310. In some cases, memory system 310 may include interface 315, processor 320, and memory controller 325. Interface 315 may include or be associated with a command queue (e.g., a first command queue, not shown). Interface 315 may be... Figure 2 An instance of interface 220. Storage controller 325 may be associated with a command queue (e.g., a second command queue, not shown). Storage controller 325 may be... Figure 2 An instance of storage controller 230. Processor 320 may be... Figure 2 An example of the memory system controller 215. Furthermore, the test system 305 can be a host system configured to transmit read commands to the memory system 310 (e.g., as referenced). Figure 1 An example of the host system 105 described herein. As described herein, a read command transmitted from the test system 305 to the memory system 310 may contain an indicator instructing the memory system to execute the command or partially execute the command. By partially executing the read command, the test system 305 can identify performance problems related to operations performed by the interface 315, the processor 320, or the memory controller 325. Therefore, the test system 305 can tune the performance of the memory system 310, which can improve the overall performance of the memory system 310.

[0072] As described herein, test system 305 may be a host system configured to transmit read commands to memory system 310 (e.g., as referenced). Figure 1 An example of the host system 105 described. In some cases, a read command may be formatted as a packet called a UFS Protocol Information Unit (UPIU) or comprised of said packet. A UPIU may contain one or more fields for indicators (e.g., reserved fields). For example, said fields may contain indicators having one of several values. In some instances, a first value may indicate that the memory system 310 suppresses operations performed by the processor 320 and the storage controller 325, a second value may indicate that the memory system 310 suppresses operations performed by the storage controller 325, and a third value may indicate that the memory system 310 does not suppress any operations (e.g., to execute a read command).

[0073] In other instances, test system 305 may transmit indicators using specific commands, different command protocols, or by using specific pins (e.g., a specific subset of pins). In any of these cases, the value of the indicator may instruct memory system 310 to suppress operations performed by processor 320 and memory controller 325, or not to suppress any operations (e.g., to execute a read command). By suppressing specific operations associated with read commands, test system 305 can identify performance problems associated with memory system 310 and can adjust aspects of memory system 310 to improve its overall performance.

[0074] Interface 315 may be an instance of the front end of memory system 310. In some instances, interface 315 may receive commands from test system 305 and may generate internal commands for processor 320. For example, interface 315 may generate internal commands that instruct processor 320 to perform a read operation (or a portion of a read operation) at a logical address in memory system 310. In some cases, when generating internal commands, interface 315 may store the commands in a command queue associated with interface 315 (e.g., a first command queue, not shown).

[0075] In other instances, portions of the read operation performed separately by processor 320 and memory controller 325 can be suppressed, allowing interface 315 to generate a response instructing memory system 310 to complete the read command. In such cases, interface 315 can generate padding data and output both the response and the padding data to test system 305. As used herein, padding data can refer to data generated by interface 315 (or another component of memory system 310) or otherwise not read from the memory cell corresponding to the logical address of the received read command. Therefore, padding data can be used to satisfy the received read command, allowing test system 305 to identify performance issues related to memory system 310 and adjust aspects of memory system 310 to improve its overall performance.

[0076] Processor 320 may be an instance of the FTL of memory system 310. In some instances, processor 320 may retrieve commands (e.g., internal commands) from a command queue associated with interface 315. As described herein, internal commands may be associated with logical addresses of memory system 310, and therefore processor 320 may determine the physical address of memory system 310 based on the logical address. In some cases, processor 320 may then pass the read command and physical address to memory controller 325 (or memory controller 325 may retrieve the read command and physical address from processor 320).

[0077] In other instances, portions of the read operation performed additionally by the storage controller 325 can be suppressed, and thus the processor 320 can transmit signaling to the interface 315 to indicate that it has executed the corresponding portion of the read command. In such cases, as described above, the interface 315 can generate response and fill data for output to the test system 305.

[0078] The memory controller 325 may be an instance of the backend of the memory system 310. In some instances, the memory controller 325 may retrieve commands (e.g., internal commands containing the physical address of the memory system 310) from the processor 320. For example, the memory controller 325 may retrieve commands from the processor 320 and may store the commands in a command queue associated with the memory controller 325 (e.g., a second command queue, not shown). When storing commands in the command queue, the memory controller 325 may access a portion of the memory system 310 corresponding to the physical address. In such cases, after reading data from the physical address, the data may be transferred to the processor 320, and the processor 320 may transfer the data to the interface 315 for output to the test system 305. However, in some cases, it may be undesirable to perform the entire read operation during a test operation because the test system 305 may not be able to identify where performance problems occur within the memory system 310. In other words, it may be desirable to suppress some read commands so that test system 305 can determine whether any performance problems occur in specific parts of memory system 310 (e.g., at interface 315, processor 320, or memory controller 325).

[0079] At 330, test system 305 can transmit a read command to memory system 310. The read command can be received by interface 315. As described herein, the read command may contain an indicator instructing memory system 310 to perform the command or suppress one or more operations associated with the read command. For illustrative purposes only, the read command transmitted at 330 may contain a first value that instructs memory system 310 to suppress operations performed by processor 320 and memory controller 325.

[0080] At 335, interface 315 can perform a first operation associated with a read command. In some cases, the first operation may include generating an internal command (e.g., an entry) for processor 320. The first operation may also include interface 315 storing the entry into a command queue (e.g., a first queue, not shown) from which processor 320 can retrieve the entry. In some cases, the entry may contain a logical address associated with the read command, such that if processor 320 retrieves the entry, processor 320 can determine the physical address of memory system 310 from which the read operation was performed.

[0081] At 340, interface 315 can recognize the value of the indicator contained in the read command. Alternatively, in some instances, interface 315 can recognize the value of the indicator before performing the first operation (e.g., at 335). As described herein, for illustrative purposes only, a read command received from test system 305 (e.g., at 330) may indicate a first value that may instruct memory system 310 to suppress operations performed by processor 320 and memory controller 325. Suppressing operations performed by both processor 320 and memory controller 325 may herein be referred to as suppressing a second operation associated with the read command.

[0082] At 345, processor 320 and storage controller 325 can suppress a second operation associated with a read command. In some instances, processor 320 and storage controller 325 can be instructed to avoid performing the second operation based on signaling transmitted from interface 315 (not shown) or because no signaling is transmitted from interface 315. For example, interface 315 can typically generate signaling instructing processor 320 to retrieve an entry from a command queue. Therefore, by avoiding the transmission of such signaling, processor 320 and, consequently, storage controller 325 can avoid performing the second operation. In other instances, interface 315 can proactively generate signaling (not shown) instructing processor 320 to avoid retrieving an entry from a command queue, which in turn allows processor 320 and storage controller 325 to avoid performing the second operation. Storage controller 325's avoidance of performing the second operation can also suppress a third operation of the storage controller dependent on the second operation.

[0083] At 350, interface 315 can generate padding data and a response to transmit to test system 305. The response and padding data can indicate the completion of a read command, although the second operation is suppressed. By transmitting a response with padding data, a read command (e.g., transmitted at 330) can be satisfied even though the data is not read from the physical address of memory system 310 corresponding to the read command. At 355, interface 315 can transmit (e.g., output) a response to test system 305.

[0084] In some cases (not shown), the test system 305 can adjust one or more performance metrics of the memory system 310 based on the received response (e.g., at 355). For example, if any error occurs during a read operation corresponding to a read command, the test system 305 can identify an error occurring at interface 315 because the operations performed by processor 320 and memory controller 325 are suppressed. Alternatively, the test system 305 can debug errors related to timing parameters of the memory system 310 (or interface 315, specifically) by determining the duration elapsed between transmitting a read command (e.g., at 330) and receiving a response (e.g., at 355). Therefore, the test system 305 can tune the performance of the memory system 310, which can improve its overall performance.

[0085] In another instance, at 360, test system 305 can transmit a read command (e.g., a second read command) to memory system 310. The second read command can be received by interface 315. As described herein, the read command may contain an indicator instructing memory system 310 to perform the command or suppress one or more operations associated with the read command. For illustrative purposes only, the second read command transmitted at 330 may contain a second value that instructs memory system 310 to suppress an operation performed by memory controller 325.

[0086] At 365, interface 315 can perform a first operation associated with the second read command. In some cases, the first operation may include generating an internal command (e.g., an entry) for processor 320. The first operation may also include interface 315 storing the entry into a command queue (e.g., a first queue, not shown) from which processor 320 can retrieve the entry. In some cases, the entry may contain a logical address associated with the second read command, such that if processor 320 retrieves the entry, processor 320 can determine the physical address of memory system 310 from which the read operation was performed.

[0087] At 370, interface 315 can identify the value of the indicator included in the second read command. Alternatively, in some instances, interface 315 can identify the value of the indicator before performing the first operation (e.g., at 365). As described herein, for illustrative purposes only, the second read command received from test system 305 (e.g., at 330) may indicate a second value that may instruct memory system 310 to suppress the operation performed by memory controller 325. Suppressing the operation performed by memory controller 325 may herein be referred to as suppressing a third operation associated with the second read command.

[0088] At 375, processor 320 can perform a second operation associated with the second read command. Processor 320 can perform the second operation by retrieving an entry from the storage queue of interface 315 and determining the physical address of memory system 310 associated with the second read command. In some instances, processor 320 can determine the physical address of memory system 310 by utilizing a lookup table stored in the memory array of memory system 310 (not shown), or by utilizing a portion of a lookup table stored in the memory associated with processor 320 (not shown).

[0089] At 380, the storage controller 325 can suppress a third operation associated with the second read command. In some instances, the storage controller 325 can be instructed to avoid performing a third operation based on signaling transmitted from the processor 320 (not shown) or because no signaling is transmitted from the processor 320. For example, the processor 320 can typically generate signaling to convey an entry (containing a physical address) to the storage controller 325. Therefore, by avoiding the transmission of such signaling, the storage controller 325 can avoid performing a third operation. In other instances, the processor 320 can proactively generate signaling (not shown) instructing the storage controller 325 to avoid storing the entry in a storage queue (e.g., a second storage queue, not shown).

[0090] At 385, processor 320 can transmit a signaling to interface 315 indicating the completion of the second operation. At 390, interface 315 can generate padding data and a response to transmit to test system 305. The response and padding data can indicate the completion of the second read command, even though the third operation is suppressed. By transmitting the response and padding data, the second read command can be satisfied (e.g., transmitted at 360) even though no data is read from the physical address of memory system 310 corresponding to the second read command. At 395, interface 315 can transmit (e.g., output) a response to test system 305.

[0091] In some cases (not shown), the test system 305 can adjust one or more performance metrics of the memory system 310 based on the received response (e.g., at 395). For example, if any error occurs during a read operation corresponding to a second read command, the test system 305 can identify an error occurring at interface 315 or processor 320 because the operation performed by the memory controller 325 is suppressed. Alternatively, the test system 305 can debug errors related to the timing parameters of the memory system 310 by determining the duration elapsed between transmitting the read command (e.g., at 360) and receiving the response (e.g., at 395). Therefore, the test system 305 can adjust the performance of the memory system 310, which can improve its overall performance.

[0092] Figure 4An example of a process flowchart 400 supporting performance tuning of a memory device according to examples disclosed herein is shown. Process flowchart 400 may illustrate operations performed at test system 405 and memory system 410. In some cases, memory system 410 may include interface 415, processor 420, and memory controller 425. Interface 415 may include or be associated with a command queue (e.g., a first command queue, not shown). Interface 415 may be... Figure 2 An instance of interface 220. Storage controller 425 may be associated with a command queue (e.g., a second command queue, not shown). Storage controller 425 may be... Figure 2 An instance of storage controller 230. Processor 420 may be... Figure 2 An example of the memory system controller 215. Furthermore, the test system 405 can be a host system configured to transmit write commands to the memory system 410 (e.g., as referenced). Figure 1 An example of the host system 105 described herein. As described herein, write commands transmitted from test system 405 to memory system 410 may contain indicators instructing the memory system to execute the command or partially execute the command. By partially executing the write command, test system 405 can identify performance issues related to operations performed by interface 415, processor 420, or memory controller 425. Therefore, test system 405 can tune the performance of memory system 410, which can improve the overall performance of memory system 410.

[0093] As described herein, test system 405 may be a host system configured to transmit write commands to memory system 410 (e.g., as referenced). Figure 1 An example of the host system 105 described. In some cases, write commands may be formatted as packets called UPIUs or consist of said packets. A UPIU may contain one or more fields for indicators (e.g., reserved fields). For example, said fields may contain indicators having one of a plurality of values. In some instances, a first value may indicate that the memory system 410 suppresses operations performed by the processor 420 and the memory controller 425, a second value may indicate that the memory system 410 suppresses operations performed by the memory controller 425, and a third value may indicate that the memory system 410 does not suppress any operations (e.g., to execute a write command).

[0094] In other instances, test system 405 may use specific commands, different command protocols, or transmit indicators by using specific pins (e.g., a specific subset of pins). In any of these cases, the value of the indicator may instruct memory system 410 to suppress operations performed by processor 420 and memory controller 425, or not to suppress any operations (e.g., to execute a write command). By suppressing specific operations associated with write commands, test system 405 can identify performance problems associated with memory system 410 and can adjust aspects of memory system 410 to improve its overall performance.

[0095] Interface 415 may be an instance of the front end of memory system 410. In some instances, interface 415 may receive commands from test system 405 and may generate internal commands for processor 420. For example, interface 415 may generate internal commands that instruct processor 420 to perform a write operation (or a portion of a write operation) at a logical address in memory system 410. In some cases, when generating internal commands, interface 415 may store the commands in a command queue associated with interface 415 (e.g., a first command queue, not shown).

[0096] In other instances, portions of the write operation performed separately by the processor 420 and the memory controller 425 can be suppressed, so that the interface 415 can generate a response instructing the memory system 410 to complete the write command. In such cases, the data contained in the write command may not be written to the memory system 410.

[0097] Processor 420 may be an instance of the FTL of memory system 410. In some instances, processor 420 may retrieve commands (e.g., internal commands) from a command queue associated with interface 415. As described herein, internal commands may be associated with logical addresses of memory system 410, and therefore processor 420 may determine the physical address of memory system 410 based on the logical address. In some cases, processor 420 may then communicate the write command and physical address to memory controller 425 (or memory controller 425 may retrieve the write command and physical address from processor 420).

[0098] In other instances, portions of the write operation performed additionally by the memory controller 425 can be suppressed, and thus the processor 420 can transmit signaling to the interface 415 to indicate that it has executed the corresponding portion of the write command. In such cases, as described above, the interface 415 can generate a response for output to the test system 405, and the data associated with the write command may not be written to the memory system 410.

[0099] The memory controller 425 may be an instance of the backend of the memory system 410. In some instances, the memory controller 425 may retrieve commands (e.g., internal commands containing the physical address of the memory system 410) from the processor 420. For example, the memory controller 425 may retrieve commands from the processor 420 and may store the commands in a command queue associated with the memory controller 425 (e.g., a second command queue, not shown). While storing the commands in the command queue, the memory controller 425 may write data to a portion of the memory system 410 corresponding to the physical address. In such cases, after writing the data to the physical address, signaling indicating that the write operation is complete may be transmitted to the processor 420, and the processor 420 may transmit the indication to the interface 415. The interface 415 may then output a response to the test system 405. However, in some cases, it may not be desirable to perform the entire write operation during a test operation, as the test system 405 may not be able to identify where performance problems occur within the memory system 410. In other words, it may be desirable to suppress some write commands so that test system 405 can determine whether any performance problems occur in specific parts of memory system 410 (e.g., at interface 415, processor 420, or memory controller 425).

[0100] At 430, test system 405 can transmit a write command to memory system 410. The write command can be received by interface 415. As described herein, the write command may include indicators instructing memory system 410 to perform the command or suppress one or more operations associated with the write command. For illustrative purposes only, the write command transmitted at 430 may include a first value that instructs memory system 410 to suppress operations performed by processor 420 and memory controller 425.

[0101] At 435, interface 415 can perform a first operation associated with a write command. In some cases, the first operation may include generating an internal command (e.g., an entry) for processor 420. The first operation may also include interface 415 storing the entry into a command queue (e.g., a first queue, not shown) from which processor 420 can retrieve the entry. In some cases, the entry may contain a logical address associated with the write command, such that if processor 420 retrieves the entry, processor 420 can determine the physical address of the memory system 410 to which the associated data will be written.

[0102] At 440, interface 415 can recognize the value of the indicator contained in the write command. Alternatively, in some instances, interface 415 can recognize the value of the indicator before performing the first operation (e.g., at 435). As described herein, for illustrative purposes only, a write command received from test system 405 (e.g., at 430) may indicate a first value that may instruct memory system 410 to suppress the operation performed by processor 420 and memory controller 425. Suppressing the operation performed by both processor 420 and memory controller 425 may herein be referred to as suppressing a second operation associated with the write command.

[0103] At 445, processor 420 and storage controller 425 can suppress a second operation associated with a write command. In some instances, processor 420 and storage controller 425 can be instructed to avoid performing the second operation based on signaling transmitted from interface 415 (not shown) or because no signaling is transmitted from interface 415. For example, interface 415 can typically generate signaling instructing processor 420 to retrieve an entry from a command queue. Therefore, by avoiding the transmission of such signaling, processor 420 and, consequently, storage controller 425 can avoid performing the second operation. In other instances, interface 415 can proactively generate signaling (not shown) instructing processor 420 to avoid retrieving an entry from a command queue, which in turn allows processor 420 and storage controller 425 to avoid performing the second operation. Storage controller 425's avoidance of performing the second operation can also suppress a third operation of the storage controller dependent on the second operation.

[0104] At 450, interface 415 can generate a response for transmission to test system 405. The response can indicate the completion of a write command, although the second operation is suppressed. By transmitting the response to test system 405, test system 405 can assume that the write operation has been completed, even though data has not been written to the physical address of the memory system 410 corresponding to the write command. At 455, interface 415 can transmit (e.g., output) a response to test system 405.

[0105] In some cases (not shown), the test system 405 can adjust one or more performance metrics of the memory system 410 based on the received response (e.g., at 455). For example, if any error occurs during a write operation corresponding to a write command, the test system 405 can identify an error occurring at interface 415 because the operations performed by processor 420 and memory controller 425 are suppressed. Alternatively, the test system 405 can debug errors related to timing parameters of the memory system 410 (or interface 415, specifically) by determining the duration elapsed between transmitting a write command (e.g., at 430) and receiving a response (e.g., at 455). Therefore, the test system 405 can tune the performance of the memory system 410, which can improve its overall performance.

[0106] In another example, at 460, test system 405 may transmit a write command (e.g., a second write command) to memory system 410. The second write command may be received by interface 415. As described herein, the write command may include an indicator instructing memory system 410 to perform the command or suppress one or more operations associated with the write command. For illustrative purposes only, the second write command transmitted at 440 may include a second value that may instruct memory system 410 to suppress an operation performed by memory controller 425.

[0107] At 465, interface 415 can perform a first operation associated with the second write command. In some cases, the first operation may include generating an internal command (e.g., an entry) for processor 420. The first operation may also include interface 415 storing the entry into a command queue (e.g., a first queue, not shown) from which processor 420 can retrieve the entry. In some cases, the entry may contain a logical address associated with the second write command, such that if processor 420 retrieves the entry, processor 420 can determine the physical address of memory system 410 from which the write operation was performed.

[0108] At 470, interface 415 can identify the value of the indicator included in the second write command. Alternatively, in some instances, interface 415 can identify the value of the indicator before performing the first operation (e.g., at 465). As described herein, for illustrative purposes only, the second write command received from test system 405 (e.g., at 440) may indicate a second value that may instruct memory system 410 to suppress the operation performed by memory controller 425. Suppressing the operation performed by memory controller 425 may herein be referred to as suppressing a third operation associated with the second write command.

[0109] At 475, processor 420 may perform a second operation associated with the second write command. In some instances, processor 420 may perform the second operation by retrieving an entry from the storage queue of interface 415 and determining the physical address of memory system 410 associated with the second write command. In some instances, processor 420 may determine the physical address of memory system 410 by utilizing a lookup table stored in the memory array of memory system 410 (not shown), or by utilizing a portion of a lookup table stored in the memory associated with processor 420 (not shown).

[0110] At 480, the storage controller 425 can suppress a third operation associated with the second write command. In some instances, the storage controller 425 can be instructed to avoid performing a third operation based on signaling transmitted from the processor 420 (not shown) or because no signaling is transmitted from the processor 420. For example, the processor 420 can typically generate signaling to convey an entry (containing a physical address) to the storage controller 425. Therefore, by avoiding the transmission of such signaling, the storage controller 425 can avoid performing a third operation. In other instances, the processor 420 can proactively generate signaling (not shown) instructing the storage controller 425 to avoid storing the entry in a storage queue (e.g., a second storage queue, not shown).

[0111] At 485, processor 420 can transmit a signaling to interface 415 indicating the completion of the second operation. At 490, interface 415 can generate a response to transmit to test system 405. The response can indicate the completion of the second write command, even though the third operation is suppressed. By transmitting the response to test system 405, test system 405 can assume that the second write operation has been completed, even though data has not been written to the physical address of memory system 410 corresponding to the second write command. At 495, interface 415 can transmit (e.g., output) a response to test system 405.

[0112] In some cases (not shown), the test system 405 can adjust one or more performance metrics of the memory system 410 based on the received response (e.g., at 495). For example, if any error occurs during a write operation corresponding to a second write command, the test system 405 can identify an error occurring at interface 415 or processor 420 because the operation performed by the memory controller 425 is suppressed. Alternatively, the test system 405 can debug errors related to the timing parameters of the memory system 410 by determining the duration elapsed between transmitting the write command (e.g., at 460) and receiving the response (e.g., at 495). Therefore, the test system 405 can adjust the performance of the memory system 410, which can improve its overall performance.

[0113] Figure 5A block diagram 500 illustrates a memory controller 520 that supports performance tuning of a memory device according to an example disclosed herein. The memory controller 520 may be as described in the reference... Figures 1 to 4 Examples of aspects of the described memory controller. Memory controller 520 or its various components may be examples of means for performing various aspects of performance tuning of the memory device as described herein. For example, memory controller 520 may include receiving component 525, command component 530, suppression component 535, output component 540, retrieval component 545, storage component 550, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0114] The receiving component 525 may be configured or otherwise supported to receive a read command at an interface of a memory system including a processor and a memory controller, wherein the read command includes an indicator for partial execution of the read command.

[0115] Command component 530 may be configured or otherwise support a component for performing the following operations: executing a first operation associated with a read command by an interface based at least in part on a received read command, the first operation comprising generating an entry associated with the read command based on one or more parameters of the read command from a command queue for the processor.

[0116] In some instances, the indicator contains a second value, and the command component 530 may be configured or otherwise support a component for performing a second operation associated with a read command by the processor based at least in part on retrieving an entry from the command queue.

[0117] Suppression component 535 may be configured or otherwise support a component for performing the following operations: suppressing one or more additional operations associated with a read command based at least in part on an indicator that performs a first operation based on an interface and on a partial execution of a read command, wherein the one or more additional operations associated with the read command are suppressed by a processor, a memory controller, or both.

[0118] In some instances, the indicator contains a first value, and the suppression component 535 may be configured or otherwise support components for performing the following operations: suppressing a second operation of the processor associated with a read command and a third operation of the memory controller associated with a read command, at least in part based on the indicator containing the first value, wherein the output response performs the first operation at least in part based on the interface, the processor suppresses the second operation, and the memory controller suppresses the third operation.

[0119] In some instances, the indicator contains a second value, and the suppression component 535 may be configured or otherwise support a component for performing the following operation: the storage controller suppresses a third operation associated with a read command at least in part based on the indicator containing the second value, wherein the output response is at least in part based on the interface performing the first operation, the processor performing the second operation, and the storage controller suppressing the third operation.

[0120] Output component 540 may be configured or otherwise support a component for performing the following operations: outputting a response indicating that the memory system has completed a read command, based at least in part on performing a first operation and suppressing one or more additional operations, wherein the response includes padding data generated at least in part based on suppressing one or more additional operations.

[0121] In some instances, the indicator contains a second value, and the retrieval component 545 may be configured or otherwise supported to perform the following operation: retrieving an entry from the command queue by the processor performing a first operation based at least in part on the interface and the first value of the indicator.

[0122] In some instances, to support the suppression of third operations associated with read commands, storage component 550 may be configured or otherwise supported to prevent entries associated with read commands from being stored in a second command queue.

[0123] In some instances, the second operation associated with the read command involves mapping the logical address associated with the read command to a physical address in the memory system. In some instances, the third operation associated with the read command involves reading data from one or more non-volatile memory cells associated with the physical address in the memory system.

[0124] Figure 6 A block diagram 600 illustrates a memory controller 620 that supports performance tuning of a memory device according to an example disclosed herein. The memory controller 620 may be as described in the reference... Figures 1 to 4 Examples of aspects of the described memory controller. Memory controller 620 or its various components may be examples of means for performing various aspects of performance tuning of the memory device as described herein. For example, memory controller 620 may include receiving component 625, command component 630, suppression component 635, output component 640, retrieval component 645, storage component 650, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0125] The receiving component 625 may be configured or otherwise support a component for performing the following operation: receiving a write command at an interface of a memory system including a processor and a memory controller, wherein the write command includes an indicator of partial execution of the write command.

[0126] Command component 630 may be configured or otherwise support a component for performing the following operation: performing a first operation associated with a write command by an interface based at least in part on a received write command, the first operation comprising generating an entry associated with the write command based on one or more parameters of the write command from a command queue for the processor.

[0127] In some instances, the indicator contains a second value, and the command component 630 may be configured or otherwise support a component for performing a second operation associated with a write command by the processor based at least in part on retrieving an entry from the command queue.

[0128] The suppression component 635 may be configured or otherwise support a component for performing the following operations: suppressing one or more additional operations associated with a write command by performing at least part of a first operation associated with the write command based on an interface and based on an indicator of partial execution of the write command, wherein the one or more additional operations associated with the write command are suppressed by a processor, a storage controller, or both.

[0129] In some instances, the indicator contains a first value, and the suppression component 635 may be configured or otherwise support components for performing the following operations: suppressing a second operation of the processor associated with a read command and a third operation of the storage controller associated with a write command, at least in part based on the indicator containing the first value, wherein the output response performs the first operation at least in part based on the interface, the processor suppresses the second operation, and the storage controller suppresses the third operation.

[0130] In some instances, the indicator contains a second value, and the suppression component 635 may be configured or otherwise support a component for performing the following operation: the storage controller suppresses a third operation associated with a write command based at least in part on the indicator containing the second value, wherein the output response is based at least in part on the interface performing the first operation, the processor performing the second operation, and the storage controller suppressing the third operation.

[0131] Output component 640 may be configured or otherwise support a component for performing the following operations: outputting a response indicating that the memory system has completed a write command, based at least in part on performing a first operation and suppressing one or more additional operations.

[0132] In some instances, the indicator contains a second value, and the retrieval component 645 may be configured or otherwise support a component for retrieving an entry from a command queue by having the processor perform a first operation at least in part based on the interface and the first value of the indicator.

[0133] In some instances, to support the suppression of third operations associated with write commands, storage component 650 may be configured or otherwise support components for preventing entries associated with write commands from being stored in a second command queue.

[0134] In some instances, the second operation associated with the write command involves mapping the logical address associated with the write command to a physical address in the memory system.

[0135] In some instances, the write component 655 may be configured or otherwise support a component for performing the following operations: at least in part based on suppressing a third operation associated with the write command to avoid writing data associated with the write command to one or more memory cells of the memory system.

[0136] In some instances, the third operation associated with the write command involves writing data to one or more non-volatile memory cells associated with physical addresses in the memory system.

[0137] Figure 7 A flowchart is shown illustrating a method 700 for supporting performance tuning of a memory device according to examples disclosed herein. Operation of method 700 may be implemented by a memory controller or its components as described herein. For example, operation of method 700 may be performed by, as referenced... Figures 1 to 5 The described memory controller performs the function. In some instances, the memory controller can execute a set of instructions to control the functional elements of the device, thereby performing the described function. Alternatively, the memory controller can use dedicated hardware to perform aspects of the described function.

[0138] At 705, a read command can be received, the read command containing an indicator for partial execution of the read command. For example, the read command can be received at an interface of a memory system including a processor and a memory controller. Operation of 705 can be performed according to examples as disclosed herein. In some instances, aspects of operation of 705 can be provided by reference to [reference needed]. Figure 5 The described receiving component 525 is used to perform this action.

[0139] In 710, a first operation associated with a read command can be performed, at least in part, based on the receipt of the read command. The first operation may include generating an entry associated with the read command based on one or more parameters of the read command. For example, the first operation can be performed by an interface and the read command can be generated against the processor's command queue. The operation of 710 can be performed according to examples as disclosed herein. In some instances, aspects of the operation of 710 can be provided by references... Figure 5 The command component 530 is described and executed.

[0140] In 715, one or more additional operations associated with a read command can be suppressed at least in part based on an indicator that performs a first operation and is based on partial execution of the read command. For example, one or more additional operations associated with a read command can be suppressed at least in part based on an indicator that performs a first operation and is based on partial execution of the read command, wherein the suppression of one or more additional operations associated with the read command is performed by a processor, a memory controller, or both. The operation of 715 can be performed according to examples as disclosed herein. In some instances, aspects of the operation of 715 can be determined by reference to [reference needed]. Figure 5 The suppression component 535 described is used to perform this.

[0141] At 720, a response indicating completion of a read command can be output, at least in part, based on performing a first operation and suppressing one or more additional operations. The response may include padding data generated, at least in part, based on suppressing one or more additional operations. For example, the interface can output a response indicating completion of a read command, at least in part, based on performing a first operation and suppressing one or more additional operations. The operation of 720 can be performed according to examples as disclosed herein. In some instances, aspects of the operation of 720 can be derived from references... Figure 5 The output component 540 is described for execution.

[0142] In some instances, the apparatus described herein can perform one or more methods, such as method 700. The apparatus may include features, circuitry, logic, components, or instructions (a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0143] Aspect 1: The device, comprising features, circuitry, logic, components, or instructions, or any combination thereof, is configured to: receive a read command at an interface to a memory system comprising a processor and a memory controller, wherein the read command includes an indicator for partial execution of the read command; perform, at least partially based on the interface, a first operation associated with the read command, the first operation including generating an entry associated with the read command based on one or more parameters of the read command in a command queue for the processor; suppress one or more additional operations associated with the read command based at least partially based on the interface and based on the indicator for partial execution of the read command, wherein the one or more additional operations associated with the read command are suppressed by the processor, the memory controller, or both; and output a response from the interface at least partially based on the execution of the first operation and the suppression of the one or more additional operations, instructing the memory system to complete the read command, wherein the response includes padding data generated at least partially based on the suppression of the one or more additional operations.

[0144] Aspect 2: The apparatus according to Aspect 1, wherein the indicator includes a first value, and the method, apparatus, and non-transitory computer-readable medium further includes operations, features, circuitry, logic, components, or instructions or any combination thereof for: suppressing a second operation of the processor associated with the read command and a third operation of the memory controller associated with the read command, at least in part based on the indicator including the first value, wherein outputting the response is performed at least in part based on the interface, the processor suppressing the second operation, and the memory controller suppressing the third operation.

[0145] Aspect 3: An apparatus according to any one of Aspects 1 to 2, wherein the indicator includes a second value, and the method, apparatus, and non-transitory computer-readable medium further includes operations, features, circuit systems, logic, components, or instructions or any combination thereof for: retrieving the entry from the command queue by the processor performing the first operation at least in part based on the interface and the first value of the indicator; performing a second operation associated with the read command by the processor at least in part based on retrieving the entry from the command queue; and suppressing a third operation associated with the read command by the storage controller at least in part based on the indicator including the second value, wherein outputting the response is at least in part based on the interface performing the first operation, the processor performing the second operation, and the storage controller suppressing the third operation.

[0146] Aspect 4: The device according to aspect 3, wherein suppressing the third operation associated with the read command further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof, for: preventing the entry associated with the read command from being stored in the second command queue.

[0147] Aspect 5: The device according to any one of aspects 3 to 4 further includes operations, features, circuit systems, logic, components or instructions or any combination thereof for: the second operation associated with the read command includes mapping a logical address associated with the read command to a physical address of the memory system.

[0148] Aspect 6: The device according to any one of aspects 3 to 5 further includes operations, features, circuit systems, logic, components or instructions or any combination thereof for: the third operation associated with the read command comprising reading data from one or more non-volatile memory cells associated with the physical address of the memory system.

[0149] Figure 8 A flowchart is shown illustrating a method 800 for supporting performance tuning of a memory device according to examples disclosed herein. Operation of method 800 may be implemented by a memory controller or its components as described herein. For example, operation of method 800 may be performed by, as referenced... Figures 1 to 4 The memory controller described in section 6 executes the functions described herein. In some instances, the memory controller may execute a set of instructions to control the functional elements of the device, thereby performing the functions described. Alternatively, the memory controller may use dedicated hardware to perform aspects of the functions described.

[0150] At 805, a write command may be received, the write command containing an indicator for partial execution of the write command. For example, the write command may be received at an interface of a memory system including a processor and a memory controller. Operation of 805 may be performed according to examples as disclosed herein. In some instances, aspects of operation of 805 may be provided by reference to [reference needed]. Figure 6 The described receiving component 625 is used to perform this action.

[0151] In 810, a first operation associated with a write command can be performed at least in part based on the receipt of the write command. The first operation may include generating an entry associated with the write command based on one or more parameters of the write command. For example, the interface can perform the first operation associated with the write command at least in part based on the receipt of the write command, and the first operation may be generated against the processor's command queue. The operation of 810 can be performed according to examples as disclosed herein. In some instances, aspects of the operation of 810 may be provided by references... Figure 6 The command component 630 is described and executed.

[0152] In 815, one or more additional operations associated with a write command can be suppressed, at least in part, based on the execution of a first operation associated with the write command and based on an indicator of partial execution of the write command. For example, the interface can execute the first operation associated with the write command, and one or more additional operations associated with the write command can be suppressed by the processor, the memory controller, or both. The operation of 815 can be performed according to examples as disclosed herein. In some instances, aspects of the operation of 815 can be determined by reference to [reference]. Figure 6 The suppression component 635 described is used to perform this.

[0153] In 820, a response indicating completion of a write command can be output, at least in part, based on performing a first operation and suppressing one or more additional operations. For example, the interface can output a response indicating that the memory system has completed a write command. The operation of 820 can be performed according to examples as disclosed herein. In some instances, aspects of the operation of 820 can be derived from references... Figure 6 The output component 640 is described for execution.

[0154] In some instances, the apparatus described herein can perform one or more methods, such as method 800. The apparatus may include features, circuitry, logic, components, or instructions (a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0155] Aspect 7: The device, comprising features, circuitry, logic, components, or instructions, or any combination thereof, is configured to: receive a write command at an interface to a memory system comprising a processor and a memory controller, wherein the write command includes an indicator of partial execution of the write command; perform, at least in part based on the received write command, a first operation associated with the write command by the interface, the first operation comprising generating an entry associated with the write command for a command queue for the processor based on one or more parameters of the write command; perform, at least in part based on the interface, the first operation associated with the write command and based on the indicator of partial execution of the write command to suppress one or more additional operations associated with the write command, wherein the one or more additional operations associated with the write command are suppressed by the processor, the memory controller, or both; and output a response instructing the memory system to complete the write command by the interface, at least in part based on the performance of the first operation and the suppression of the one or more additional operations.

[0156] Aspect 8: The apparatus of aspect 7, wherein the indicator comprises a first value, and the method, apparatus, and non-transitory computer-readable medium further comprises operations, features, circuitry, logic, components, or instructions or any combination thereof, for: suppressing a second operation of the processor associated with the read command and a third operation of the storage controller associated with the write command, at least in part based on the indicator comprising the first value, wherein outputting the response is performed at least in part based on the interface performing the first operation, the processor suppressing the second operation, and the storage controller suppressing the third operation.

[0157] Aspect 9: An apparatus according to any one of Aspects 7 to 8, wherein the indicator includes a second value, and the method, apparatus, and non-transitory computer-readable medium further includes operations, features, circuit systems, logic, components, or instructions or any combination thereof for: retrieving the entry from the command queue by the processor performing the first operation at least in part based on the interface and the first value of the indicator; performing a second operation associated with the write command by the processor at least in part based on retrieving the entry from the command queue; and suppressing a third operation associated with the write command by the storage controller at least in part based on the indicator including the second value, wherein outputting the response is at least in part based on the interface performing the first operation, the processor performing the second operation, and the storage controller suppressing the third operation.

[0158] Aspect 10: The device according to aspect 9, wherein suppressing the third operation associated with the write command further comprises an operation, feature, circuit system, logic, component or instruction or any combination thereof, for: preventing the entry associated with the write command from being stored in the second command queue.

[0159] Aspect 11: The device according to any one of aspects 9 to 10 further includes operations, features, circuit systems, logic, components or instructions or any combination thereof for: the second operation associated with the write command includes mapping a logical address associated with the write command to a physical address of the memory system.

[0160] Aspect 12: The device according to aspect 11 further includes operations, features, circuitry, logic, components, or instructions or any combination thereof for: at least in part based on suppressing the third operation associated with the write command to avoid writing data associated with the write command to one or more memory cells of the memory system.

[0161] Aspect 13: The device according to any one of aspects 9 to 12 further includes operations, features, circuit systems, logic, components or instructions or any combination thereof for: the third operation associated with the write command includes writing data to one or more non-volatile memory cells associated with the physical address of the memory system.

[0162] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0163] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, signals may represent buses of signals, which may have various bit widths.

[0164] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0165] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0166] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. If a controller isolates two components, it achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0167] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0168] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0169] Additionally, the terms "directly in response to" or "directly responding to" can refer to a condition or action occurring as a direct result of a previous condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a previous condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) "directly in response to" or "directly responding to" such other condition or action.

[0170] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0171] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may comprise heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0172] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0173] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral distinguishing them from each other. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0174] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0175] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0176] As used herein, the word "or" in a list of items included in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0177] Computer-readable media includes both non-transitory computer storage media and communication media that include any media facilitating the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. Combinations of these are also included within the scope of computer-readable media.

[0178] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: a memory system including an interface, one or more processors, and a storage controller, wherein: the interface is configured to cause the device to: receive a read command, the read command including an indicator of partial execution of the read command, the partial execution corresponding to refraining from performing a first operation of a plurality of operations associated with the read command and performing a second operation of the plurality of operations associated with the read command; and perform, based at least in part on receiving the read command, the second operation associated with the read command, the second operation including generating, for a command queue of the one or more processors, an entry associated with the read command based on one or more parameters of the read command; the storage controller is configured to cause the memory device to: refrain, based at least in part on the interface performing the second operation and on the indicator of partial execution of the read command, from performing the first operation associated with the read command; and the one or more processors are configured to cause the memory device to: output, based at least in part on the interface performing the second operation and the storage controller refraining from the first operation, a response indicating completion of the read command, wherein the response includes padding data generated based at least in part on the storage controller refraining from the first operation.

2. The memory device of claim 1, wherein the indicator includes a first value, and wherein at least one of the one or more processors or the storage controller is configured to cause the memory device to: refrain, based at least in part on the indicator including the first value, from a third operation of the one or more processors associated with the read command and a fourth operation of the storage controller associated with the read command, wherein outputting the response is based at least in part on the interface performing the second operation, the one or more processors refraining from the third operation, and the storage controller refraining from the fourth operation.

3. The memory device of claim 1, wherein the indicator includes a second value, and wherein: the one or more processors are configured to cause the memory device to: retrieve the entry from the command queue based at least in part on the interface performing the second operation and the second value of the indicator; and perform, based at least in part on retrieving the entry from the command queue, a third operation associated with the read command; and the storage controller is configured to cause the memory device to: refrain, based at least in part on the indicator including the second value, from a fourth operation associated with the read command, wherein outputting the response is based at least in part on the interface performing the second operation, the one or more processors performing the third operation, and the storage controller refraining from the fourth operation.

4. The memory device of claim 1, wherein the storage controller includes a second command queue, and wherein the storage controller is configured to refrain from the first operation associated with the read command by: the storage controller is configured to cause the memory device to: refrain, based at least in part on the interface performing the second operation and on the indicator of partial execution of the read command, from performing the first operation associated with the read command; and the one or more processors are configured to cause the memory device to: output, based at least in part on the interface performing the second operation and the storage controller refraining from the first operation, a response indicating completion of the read command, wherein the response includes padding data generated based at least in part on the storage controller refraining from the first operation. avoid storing the entry associated with the read command to the second command queue.

5. The memory device of claim 3, wherein the third operation associated with the read command comprises mapping a logical address associated with the read command to a physical address of the memory system.

6. The memory device of claim 5, wherein the fourth operation associated with the read command comprises reading data from one or more non-volatile memory cells associated with the physical address of the memory system.

7. A memory device, comprising: a memory system comprising an interface, one or more processors, and a storage controller, wherein: the interface is configured to cause the memory device to: receive a write command, the write command comprising an indicator of partial execution of the write command, the partial execution corresponding to refraining from performing a first operation of a plurality of operations associated with the write command and performing a second operation of the plurality of operations associated with the write command; and perform, based at least in part on receiving the write command, the second operation associated with the write command, the second operation comprising generating, for a command queue of the one or more processors, an entry associated with the write command based on one or more parameters of the write command; and the storage controller is configured to cause the memory device to: refrain, based at least in part on the interface performing the second operation and based on the indicator of partial execution of the write command, from performing the first operation associated with the write command; and the one or more processors are configured to cause the memory device to: output, based at least in part on the interface performing the second operation and the storage controller refraining from performing the first operation, a response indicating completion of the write command.

8. The memory device of claim 7, wherein the indicator comprises a first value, and wherein at least one of the one or more processors or the storage controller is configured to cause the memory device to: refrain, based at least in part on the indicator comprising the first value, from performing a third operation of the one or more processors associated with the write command and a fourth operation of the storage controller associated with the write command, wherein outputting the response is based at least in part on the interface performing the second operation, the one or more processors refraining from performing the third operation, and the storage controller refraining from performing the fourth operation.

9. The memory device of claim 7, wherein the indicator comprises a second value, and wherein: the one or more processors are configured to cause the memory device to: retrieve the entry from the command queue based at least in part on the interface performing the second operation and the second value of the indicator; and perform, based at least in part on retrieving the entry from the command queue, a third operation associated with the write command; and the storage controller is configured to cause the memory device to: inhibiting a fourth operation associated with the write command based at least in part on the indicator comprising the second value, wherein outputting the response is based at least in part on the interface performing the second operation, the one or more processors performing the third operation, and the storage controller inhibiting the fourth operation.

10. The memory device of claim 7, wherein the storage controller comprises a second command queue, and wherein the storage controller is configured to inhibit the first operation associated with the write command by: avoiding storing the entry associated with the write command to the second command queue.

11. The memory device of claim 9, wherein the third operation associated with the write command comprises mapping a logical address associated with the write command to a physical address of the memory system.

12. The memory device of claim 11, wherein at least one of the one or more processors or the storage controller is configured to cause the memory device to: avoid writing data associated with the write command to one or more memory units of the memory system based at least in part on inhibiting the fourth operation associated with the write command.

13. The memory device of claim 11, wherein the fourth operation associated with the write command comprises writing data to one or more non-volatile memory units associated with the physical address of the memory system.

14. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: receive, at an interface of a memory system comprising one or more second processors and a storage controller, a read command, wherein the read command comprises an indicator of partial execution of the read command, the partial execution corresponding to inhibiting a first operation of a plurality of operations associated with the read command and performing a second operation of the plurality of operations associated with the read command; execute, by the interface, the second operation associated with the read command based at least in part on receiving the read command, the second operation comprising generating, for a command queue of the one or more second processors, an entry associated with the read command based on one or more parameters of the read command; inhibit, by the storage controller, the first operation associated with the read command based at least in part on the interface executing the second operation and on the indicator of partial execution of the read command; and output, by the interface, a response indicating completion of the read command by the memory system based at least in part on the interface executing the second operation and the storage controller inhibiting the first operation, wherein the response comprises padding data generated based at least in part on the storage controller inhibiting the first operation.

15. The non-transitory computer-readable medium of claim 14, wherein the indicator comprises a first value, and wherein the instructions, which when executed by the one or more processors of the electronic device, further cause the electronic device to: inhibit, based at least in part on the indicator comprising the first value, a third operation of the one or more second processors associated with the read command and a fourth operation of the storage controller associated with the read command, wherein outputting the response is based at least in part on the interface performing the second operation, the one or more second processors inhibiting the third operation, and the storage controller inhibiting the fourth operation.

16. The non-transitory computer-readable medium of claim 14, wherein the indicator comprises a second value, and wherein the instructions, which when executed by the one or more processors of the electronic device, further cause the electronic device to: retrieve, by the one or more second processors, the entry from the command queue based at least in part on the interface performing the second operation and the second value of the indicator; perform, by the one or more second processors, a third operation associated with the read command based at least in part on retrieving the entry from the command queue; and inhibit, by the storage controller, a fourth operation associated with the read command based at least in part on the indicator comprising the second value, wherein outputting the response is based at least in part on the interface performing the second operation, the one or more second processors performing the third operation, and the storage controller inhibiting the fourth operation.

17. The non-transitory computer-readable medium of claim 14, wherein the instructions that inhibit the first operation associated with the read command, which when executed by the one or more processors of the electronic device, further cause the electronic device to: avoid storing the entry associated with the read command to a storage queue.

18. The non-transitory computer-readable medium of claim 16, wherein the third operation associated with the read command comprises mapping a logical address associated with the read command to a physical address of the memory system.

19. The non-transitory computer-readable medium of claim 18, wherein the fourth operation associated with the read command comprises reading data from one or more non-volatile memory cells associated with the physical address of the memory system.

20. A non-transitory computer-readable medium storing code comprising instructions that, when executed by one or more processors of an electronic device, cause the electronic device to: receive, at an interface of a memory system comprising one or more second processors and a storage controller, a write command, wherein the write command comprises an indicator of partial execution of the write command, the partial execution corresponding to inhibiting a first operation of a plurality of operations associated with the write command and performing a second operation of the plurality of operations associated with the write command; perform, by the interface, the second operation based at least in part on the interface receiving the write command, the second operation including generating, for a command queue of the one or more second processors, an entry associated with the write command based on one or more parameters of the write command; inhibit, by the storage controller, the first operation associated with the write command based at least in part on the interface performing the second operation associated with the write command and the indicator of partial execution of the write command; and output, by the interface, a response indicating completion of the write command by the memory system based at least in part on the interface performing the second operation and the storage controller inhibiting the first operation.

21. The non-transitory computer-readable medium of claim 20, wherein the indicator comprises a first value, and wherein the instructions, which when executed by the one or more processors of the electronic device, further cause the electronic device to: inhibit, based at least in part on the indicator comprising the first value, a third operation of the one or more second processors associated with the write command and a fourth operation of the storage controller associated with the write command, wherein outputting the response is based at least in part on the interface performing the second operation, the one or more second processors inhibiting the third operation, and the storage controller inhibiting the fourth operation.

22. The non-transitory computer-readable medium of claim 20, wherein the indicator comprises a second value, and wherein the instructions, which when executed by the one or more processors of the electronic device, further cause the electronic device to: retrieve, by the one or more second processors, the entry from the command queue based at least in part on the interface performing the second operation and the second value of the indicator; perform, by the one or more second processors, a third operation associated with the write command based at least in part on retrieving the entry from the command queue; and inhibit, by the storage controller, a fourth operation associated with the write command based at least in part on the indicator comprising the second value, wherein outputting the response is based at least in part on the interface performing the second operation, the one or more second processors performing the third operation, and the storage controller inhibiting the fourth operation.

23. The non-transitory computer-readable medium of claim 20, wherein the instructions that inhibit the first operation associated with the write command, which when executed by the one or more processors of the electronic device, further cause the electronic device to: avoid storing the entry associated with the write command to a storage queue.

24. The non-transitory computer-readable medium of claim 22, wherein the third operation associated with the write command comprises mapping a logical address associated with the write command to a physical address of the memory system.

25. The non-transitory computer-readable medium of claim 24, wherein the instructions, which when executed by the one or more processors of the electronic device, further cause the electronic device to: avoid writing data associated with the write command to one or more memory cells of the memory system based at least in part on suppressing the fourth operation associated with the write command.

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